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ATMEGA128A-AUR

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Microchip Tech Microcontrollers (MCU/MPU/SOC), TQFP-64(14x14). Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.

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ATMEGA128A-AUR

Microchip Tech · Microcontrollers (MCU/MPU/SOC) · TQFP-64(14x14)

ATMEGA128A-AUR from Microchip Tech, in a TQFP-64(14x14). Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 PEN input Programming enable pin for SPI Serial Programming mode, internally pulled high; holding it low during Power-on Reset enters SPI programming mode, no function in normal operation.
2 PE0 bidirectional Port E bit 0 bi-directional I/O with internal pull-up; alternate functions RXD0/PDI.
3 PE1 bidirectional Port E bit 1 bi-directional I/O with internal pull-up; alternate functions TXD0/PDO.
4 PE2 bidirectional Port E bit 2 bi-directional I/O with internal pull-up; alternate functions XCK0/AIN0.
5 PE3 bidirectional Port E bit 3 bi-directional I/O with internal pull-up; alternate functions OC3A/AIN1.
6 PE4 bidirectional Port E bit 4 bi-directional I/O with internal pull-up; alternate functions OC3B/INT4.
7 PE5 bidirectional Port E bit 5 bi-directional I/O with internal pull-up; alternate functions OC3C/INT5.
8 PE6 bidirectional Port E bit 6 bi-directional I/O with internal pull-up; alternate functions T3/INT6.
9 PE7 bidirectional Port E bit 7 bi-directional I/O with internal pull-up; alternate functions ICP3/INT7.
10 PB0 bidirectional Port B bit 0 bi-directional I/O with internal pull-up; alternate function SS.
11 PB1 bidirectional Port B bit 1 bi-directional I/O with internal pull-up; alternate function SCK.
12 PB2 bidirectional Port B bit 2 bi-directional I/O with internal pull-up; alternate function MOSI.
13 PB3 bidirectional Port B bit 3 bi-directional I/O with internal pull-up; alternate function MISO.
14 PB4 bidirectional Port B bit 4 bi-directional I/O with internal pull-up; alternate function OC0.
15 PB5 bidirectional Port B bit 5 bi-directional I/O with internal pull-up; alternate function OC1A.
16 PB6 bidirectional Port B bit 6 bi-directional I/O with internal pull-up; alternate function OC1B.
17 PB7 bidirectional Port B bit 7 bi-directional I/O with internal pull-up; alternate functions OC2/OC1C.
18 PG3 bidirectional Port G bit 3 bi-directional I/O with internal pull-up; alternate function TOSC2 (oscillator pin).
19 PG4 bidirectional Port G bit 4 bi-directional I/O with internal pull-up; alternate function TOSC1 (oscillator pin).
20 RESET input Reset input; a low level longer than the minimum pulse length generates a reset even if the clock is not running.
21 VCC power_in Digital supply voltage.
22 GND power_in Ground.
23 XTAL2 output Output from the inverting Oscillator amplifier.
24 XTAL1 input Input to the inverting Oscillator amplifier and input to the internal clock operating circuit.
25 PD0 bidirectional Port D bit 0 bi-directional I/O with internal pull-up; alternate functions SCL/INT0.
26 PD1 bidirectional Port D bit 1 bi-directional I/O with internal pull-up; alternate functions SDA/INT1.
27 PD2 bidirectional Port D bit 2 bi-directional I/O with internal pull-up; alternate functions RXD1/INT2.
28 PD3 bidirectional Port D bit 3 bi-directional I/O with internal pull-up; alternate functions TXD1/INT3.
29 PD4 bidirectional Port D bit 4 bi-directional I/O with internal pull-up; alternate function ICP1.
30 PD5 bidirectional Port D bit 5 bi-directional I/O with internal pull-up; alternate function XCK1.
31 PD6 bidirectional Port D bit 6 bi-directional I/O with internal pull-up; alternate function T1.
32 PD7 bidirectional Port D bit 7 bi-directional I/O with internal pull-up; alternate function T2.
33 PG0 bidirectional Port G bit 0 bi-directional I/O with internal pull-up; alternate function WR external memory write strobe.
34 PG1 bidirectional Port G bit 1 bi-directional I/O with internal pull-up; alternate function RD external memory read strobe.
35 PC0 bidirectional Port C bit 0 bi-directional I/O with internal pull-up; external memory address A8.
36 PC1 bidirectional Port C bit 1 bi-directional I/O with internal pull-up; external memory address A9.
37 PC2 bidirectional Port C bit 2 bi-directional I/O with internal pull-up; external memory address A10.
38 PC3 bidirectional Port C bit 3 bi-directional I/O with internal pull-up; external memory address A11.
39 PC4 bidirectional Port C bit 4 bi-directional I/O with internal pull-up; external memory address A12.
40 PC5 bidirectional Port C bit 5 bi-directional I/O with internal pull-up; external memory address A13.
41 PC6 bidirectional Port C bit 6 bi-directional I/O with internal pull-up; external memory address A14.
42 PC7 bidirectional Port C bit 7 bi-directional I/O with internal pull-up; external memory address A15.
43 PG2 bidirectional Port G bit 2 bi-directional I/O with internal pull-up; alternate function ALE external memory address latch enable.
44 PA7 bidirectional Port A bit 7 bi-directional I/O with internal pull-up; external memory address/data AD7.
45 PA6 bidirectional Port A bit 6 bi-directional I/O with internal pull-up; external memory address/data AD6.
46 PA5 bidirectional Port A bit 5 bi-directional I/O with internal pull-up; external memory address/data AD5.
47 PA4 bidirectional Port A bit 4 bi-directional I/O with internal pull-up; external memory address/data AD4.
48 PA3 bidirectional Port A bit 3 bi-directional I/O with internal pull-up; external memory address/data AD3.
49 PA2 bidirectional Port A bit 2 bi-directional I/O with internal pull-up; external memory address/data AD2.
50 PA1 bidirectional Port A bit 1 bi-directional I/O with internal pull-up; external memory address/data AD1.
51 PA0 bidirectional Port A bit 0 bi-directional I/O with internal pull-up; external memory address/data AD0.
52 VCC power_in Digital supply voltage.
53 GND power_in Ground.
54 PF7 bidirectional Port F bit 7, ADC input channel 7 or I/O; JTAG TDI, pull-up activated even during Reset if JTAG is enabled.
55 PF6 bidirectional Port F bit 6, ADC input channel 6 or I/O; JTAG TDO, tri-stated unless TAP states that shift out data are entered.
56 PF5 bidirectional Port F bit 5, ADC input channel 5 or I/O; JTAG TMS, pull-up activated even during Reset if JTAG is enabled.
57 PF4 bidirectional Port F bit 4, ADC input channel 4 or I/O; JTAG TCK, pull-up activated even during Reset if JTAG is enabled.
58 PF3 bidirectional Port F bit 3, analog input ADC3 to the A/D Converter or digital I/O.
59 PF2 bidirectional Port F bit 2, analog input ADC2 to the A/D Converter or digital I/O.
60 PF1 bidirectional Port F bit 1, analog input ADC1 to the A/D Converter or digital I/O.
61 PF0 bidirectional Port F bit 0, analog input ADC0 to the A/D Converter or digital I/O.
62 AREF input Analog reference pin for the A/D Converter.
63 GND power_in Ground.
64 AVCC power_in Supply voltage pin for Port F and the A/D Converter; must be connected to VCC even if ADC is unused, through a low-pass filter if ADC is used.

Key specifications

Parameter Value
Manufacturer Microchip Tech
Package TQFP-64(14x14)
Category Embedded Processors & Controllers
Pins 64

Electrical characteristics

Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).

Parameter Symbol Min Typ Max Unit Conditions Page
Power supply voltage 2.7 5.5 V Speed 16 MHz 6
Speed grade (operating frequency) 0 16 MHz 2
Operational temperature range (Industrial) -40 85 °C Industrial operational range 6

CAD (KiCad official)

  • Symbol: ATMEGA128A-AUR
  • Footprint: Package_QFP:TQFP-64_14x14mm_P0.8mm
  • 3D model: TQFP-64(14x14) (KiCad packages3D, STEP)
  • 3D model files: atmega128a-aur-etched.step / atmega128a-aur-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); atmega128a-aur.step / atmega128a-aur.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: Microchip Tech datasheet (20 pp, sha256 3e7097d1b104e6eb, retrieved 2026-10-20, tier: lcsc)
  • Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-sonnet-5-5 (text+vision), consensus claude-opus-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF