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ATMEGA1281V-8MU

Microchip Tech · Pre-ordered MCUs · QFN-64(9x9)

ATMEGA1281V-8MU from Microchip Tech, in a QFN-64(9x9). Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin	Name	Type	Function
1	PG5 (OC0B)	bidirectional	Port G bit 5, an I/O pin with internal pull-up whose alternate function is the Timer/Counter0 Output Compare B output OC0B.
2	PE0 (RXD0/PCINT8/PDI)	bidirectional	Port E bit 0, an I/O pin with internal pull-up whose alternate functions are USART0 receive RXD0, pin change interrupt 8 and PDI.
3	PE1 (TXD0/PDO)	bidirectional	Port E bit 1, an I/O pin with internal pull-up whose alternate functions are USART0 transmit TXD0 and PDO.
4	PE2 (XCK0/AIN0)	bidirectional	Port E bit 2, an I/O pin with internal pull-up whose alternate functions are USART0 external clock XCK0 and analog comparator input AIN0.
5	PE3 (OC3A/AIN1)	bidirectional	Port E bit 3, an I/O pin with internal pull-up whose alternate functions are Timer/Counter3 output compare A OC3A and analog comparator input AIN1.
6	PE4 (OC3B/INT4)	bidirectional	Port E bit 4, an I/O pin with internal pull-up whose alternate functions are Timer/Counter3 output compare B OC3B and external interrupt 4.
7	PE5 (OC3C/INT5)	bidirectional	Port E bit 5, an I/O pin with internal pull-up whose alternate functions are Timer/Counter3 output compare C OC3C and external interrupt 5.
8	PE6 (T3/INT6)	bidirectional	Port E bit 6, an I/O pin with internal pull-up whose alternate functions are Timer/Counter3 clock input T3 and external interrupt 6.
9	PE7 (ICP3/CLKO/INT7)	bidirectional	Port E bit 7, an I/O pin with internal pull-up whose alternate functions are Timer/Counter3 input capture ICP3, system clock output CLKO and external interrupt 7.
10	PB0 (SS/PCINT0)	bidirectional	Port B bit 0, an I/O pin with internal pull-up that serves as the SPI Slave Select input (active low) and pin change interrupt 0.
11	PB1 (SCK/PCINT1)	bidirectional	Port B bit 1, an I/O pin with internal pull-up that serves as the SPI clock (master output, slave input) and pin change interrupt 1.
12	PB2 (MOSI/PCINT2)	bidirectional	Port B bit 2, an I/O pin with internal pull-up that serves as SPI master data output / slave data input and pin change interrupt 2.
13	PB3 (MISO/PCINT3)	bidirectional	Port B bit 3, an I/O pin with internal pull-up that serves as SPI master data input / slave data output and pin change interrupt 3.
14	PB4 (OC2A/PCINT4)	bidirectional	Port B bit 4, an I/O pin with internal pull-up whose alternate functions are Timer/Counter2 output compare A OC2A and pin change interrupt 4.
15	PB5 (OC1A/PCINT5)	bidirectional	Port B bit 5, an I/O pin with internal pull-up whose alternate functions are Timer/Counter1 output compare A OC1A and pin change interrupt 5.
16	PB6 (OC1B/PCINT6)	bidirectional	Port B bit 6, an I/O pin with internal pull-up whose alternate functions are Timer/Counter1 output compare B OC1B and pin change interrupt 6.
17	PB7 (OC0A/OC1C/PCINT7)	bidirectional	Port B bit 7, an I/O pin with internal pull-up whose alternate functions are Timer/Counter0 output compare A OC0A, Timer/Counter1 output compare C OC1C and pin change interrupt 7.
18	PG3 (TOSC2)	bidirectional	Port G bit 3, an I/O pin with internal pull-up that becomes the inverting output of the Timer/Counter2 oscillator amplifier (TOSC2) when AS2 is set.
19	PG4 (TOSC1)	bidirectional	Port G bit 4, an I/O pin with internal pull-up that becomes the input of the Timer/Counter2 inverting oscillator amplifier (TOSC1) when AS2 is set.
20	RESET	input	Reset pin (RESET); during parallel programming 11.5V to 12.5V is applied to RESET to enter programming mode.
21	VCC	power_in	Digital supply voltage.
22	GND	power_in	Ground.
23	XTAL2	output	Crystal oscillator pin XTAL2, the inverting oscillator amplifier output.
24	XTAL1	input	Crystal oscillator pin XTAL1, the oscillator amplifier / external clock input, which is also pulsed during parallel programming.
25	PD0 (SCL/INT0)	bidirectional	Port D bit 0, an I/O pin with internal pull-up that serves as external interrupt 0 and the 2-wire interface clock SCL (open-drain driver with spike filter for spikes shorter than 50ns).
26	PD1 (SDA/INT1)	bidirectional	Port D bit 1, an I/O pin with internal pull-up that serves as external interrupt 1 and the 2-wire interface data SDA (open-drain driver with spike filter for spikes shorter than 50ns).
27	PD2 (RXD1/INT2)	bidirectional	Port D bit 2, an I/O pin with internal pull-up whose alternate functions are USART1 receive RXD1 and external interrupt 2.
28	PD3 (TXD1/INT3)	bidirectional	Port D bit 3, an I/O pin with internal pull-up whose alternate functions are USART1 transmit TXD1 and external interrupt 3.
29	PD4 (ICP1)	bidirectional	Port D bit 4, an I/O pin with internal pull-up that can act as the Timer/Counter1 input capture pin ICP1.
30	PD5 (XCK1)	bidirectional	Port D bit 5, an I/O pin with internal pull-up that serves as USART1 external clock XCK1, an output if DDD5 is set and an input if cleared.
31	PD6 (T1)	bidirectional	Port D bit 6, an I/O pin with internal pull-up that serves as the Timer/Counter1 clock input T1.
32	PD7 (T0)	bidirectional	Port D bit 7, an I/O pin with internal pull-up that serves as the Timer/Counter0 clock input T0.
33	PG0 (WR)	bidirectional	Port G bit 0, an I/O pin with internal pull-up that serves as the external data memory write strobe WR.
34	PG1 (RD)	bidirectional	Port G bit 1, an I/O pin with internal pull-up that serves as the external data memory read strobe RD.
35	PC0 (A8)	bidirectional	Port C bit 0, an I/O pin with internal pull-up that serves as external memory address bit 8.
36	PC1 (A9)	bidirectional	Port C bit 1, an I/O pin with internal pull-up that serves as external memory address bit 9.
37	PC2 (A10)	bidirectional	Port C bit 2, an I/O pin with internal pull-up that serves as external memory address bit 10.
38	PC3 (A11)	bidirectional	Port C bit 3, an I/O pin with internal pull-up that serves as external memory address bit 11.
39	PC4 (A12)	bidirectional	Port C bit 4, an I/O pin with internal pull-up that serves as external memory address bit 12.
40	PC5 (A13)	bidirectional	Port C bit 5, an I/O pin with internal pull-up that serves as external memory address bit 13.
41	PC6 (A14)	bidirectional	Port C bit 6, an I/O pin with internal pull-up that serves as external memory address bit 14.
42	PC7 (A15)	bidirectional	Port C bit 7, an I/O pin with internal pull-up that serves as external memory address bit 15.
43	PG2 (ALE)	bidirectional	Port G bit 2, an I/O pin with internal pull-up that serves as the external data memory Address Latch Enable signal ALE.
44	PA7 (AD7)	bidirectional	Port A bit 7, an I/O pin with internal pull-up that serves as external memory address and data bit 7.
45	PA6 (AD6)	bidirectional	Port A bit 6, an I/O pin with internal pull-up that serves as external memory address and data bit 6.
46	PA5 (AD5)	bidirectional	Port A bit 5, an I/O pin with internal pull-up that serves as external memory address and data bit 5.
47	PA4 (AD4)	bidirectional	Port A bit 4, an I/O pin with internal pull-up that serves as external memory address and data bit 4.
48	PA3 (AD3)	bidirectional	Port A bit 3, an I/O pin with internal pull-up that serves as external memory address and data bit 3.
49	PA2 (AD2)	bidirectional	Port A bit 2, an I/O pin with internal pull-up that serves as external memory address and data bit 2.
50	PA1 (AD1)	bidirectional	Port A bit 1, an I/O pin with internal pull-up that serves as external memory address and data bit 1.
51	PA0 (AD0)	bidirectional	Port A bit 0, an I/O pin with internal pull-up that serves as external memory address and data bit 0.
52	VCC	power_in	Digital supply voltage.
53	GND	power_in	Ground.
54	PF7 (ADC7/TDI)	bidirectional	Port F bit 7, ADC input channel 7 or JTAG Test Data In, with the pull-up active even during reset when JTAG is enabled.
55	PF6 (ADC6/TDO)	bidirectional	Port F bit 6, ADC input channel 6 or JTAG Test Data Out, which is tri-stated unless TAP states that shift out data are entered.
56	PF5 (ADC5/TMS)	bidirectional	Port F bit 5, ADC input channel 5 or JTAG Test Mode Select, with the pull-up active even during reset when JTAG is enabled.
57	PF4 (ADC4/TCK)	bidirectional	Port F bit 4, ADC input channel 4 or JTAG Test Clock, with the pull-up active even during reset when JTAG is enabled.
58	PF3 (ADC3)	bidirectional	Port F bit 3, ADC input channel 3, usable as an I/O pin when the A/D Converter is not used.
59	PF2 (ADC2)	bidirectional	Port F bit 2, ADC input channel 2, usable as an I/O pin when the A/D Converter is not used.
60	PF1 (ADC1)	bidirectional	Port F bit 1, ADC input channel 1, usable as an I/O pin when the A/D Converter is not used.
61	PF0 (ADC0)	bidirectional	Port F bit 0, ADC input channel 0, usable as an I/O pin when the A/D Converter is not used.
62	AREF	passive	Analog reference pin for the A/D Converter.
63	GND	power_in	Ground.
64	AVCC	power_in	Supply voltage pin for the A/D Converter (Port F).
65	EP	passive	Exposed pad (from the footprint; not named in the datasheet pin table).

Key specifications

Parameter	Value
Manufacturer	Microchip Tech
Package	QFN-64(9x9)
Category	Embedded Processors & Controllers
Pins	65

CAD (KiCad official)

Symbol: ATMEGA1281V-8MU
Footprint: Package_DFN_QFN:QFN-64-1EP_9x9mm_P0.5mm_EP6x6mm
3D model: QFN-64(9x9) (KiCad packages3D, STEP)
3D model files: atmega1281v-8mu-etched.step / atmega1281v-8mu-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); atmega1281v-8mu.step / atmega1281v-8mu.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

Datasheet: Microchip Tech datasheet (436 pp, sha256 978a018098bc1a13, retrieved 2026-10-28, tier: manufacturer)
Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-sonnet-5-5 (text+vision), consensus claude-opus-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF