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ATMEGA1281-16MU

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Microchip Tech MICROCHIP, QFN-64-EP(9x9). Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.

componentembedded processors & controllersatmega1281-16mufactory-2.0.0extractor-text

Verified ATMEGA1281-16MU

by Ray · last 31 Oct 2026 · 1 record · files match
SymbolFootprint3D modelPins

Verification log 1 record

31 Oct 2026RayPublished by the parts factory: tier mfr, 65 pinsfiles match
SymbolFootprint3D modelPinsfor all variants
  • ✓component-page-verify: PASS
  • ✓cad_props: Datasheet, MPN and distributor properties match page.json
  • ✓component: ATMEGA1281-16MU · QFN-64-EP(9x9) · 65 pins
  • ✓copper: 65 copper pads, none touching another net
  • ✓datasheet: all 65 pin names found in the 435-page datasheet
  • •distributor (warn): no ['mouser'] number
  • ✓family: QFN-64-1EP_9x9mm_P0.5mm_EP6x6mm
  • ✓files: 7 declared files present
  • ✓hero: docs/hero.png 4000x2500
  • ✓lbr: OK: /tmp/cpv-mgjzfn4s/x.lbr is a valid EAGLE .lbr with complete deviceset
  • ✓license: CC-BY-SA-4.0
  • ✓models_3d: 2 records
  • •package_fit (skip): no component.package_dims on the page: the model is unchecked against the datasheet drawing
  • ✓pads: 65 pins = 65 pads
  • ✓pose: 2 STEP(s) Z-up, seated, centred
  • ✓symbol: 65 pins agree
  • ✓visibility: public, source open
Evidencedatasheet
Verified files✓ atmega1281-16mu.kicad_sym✓ atmega1281-16mu.kicad_mod✓ atmega1281-16mu.step
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ATMEGA1281-16MU

Microchip Tech · MICROCHIP · QFN-64-EP(9x9)

ATMEGA1281-16MU from Microchip Tech, in a QFN-64-EP(9x9). Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 PG5 bidirectional Port G bit 5 I/O with internal pull-up; alternate function OC0B (Timer/Counter0 output compare B / PWM).
2 PE0 bidirectional Port E bit 0 I/O with internal pull-up; alternate functions RXD0/PCINT8/PDI.
3 PE1 bidirectional Port E bit 1 I/O with internal pull-up; alternate functions TXD0/PDO.
4 PE2 bidirectional Port E bit 2 I/O with internal pull-up; alternate functions XCK0/AIN0.
5 PE3 bidirectional Port E bit 3 I/O with internal pull-up; alternate functions OC3A/AIN1.
6 PE4 bidirectional Port E bit 4 I/O with internal pull-up; alternate functions OC3B/INT4.
7 PE5 bidirectional Port E bit 5 I/O with internal pull-up; alternate functions OC3C/INT5.
8 PE6 bidirectional Port E bit 6 I/O with internal pull-up; alternate functions T3/INT6.
9 PE7 bidirectional Port E bit 7 I/O with internal pull-up; alternate functions ICP3/CLKO/INT7.
10 PB0 bidirectional Port B bit 0 I/O with internal pull-up; alternate functions SS/PCINT0 (SPI slave select input).
11 PB1 bidirectional Port B bit 1 I/O with internal pull-up; alternate functions SCK/PCINT1 (SPI clock).
12 PB2 bidirectional Port B bit 2 I/O with internal pull-up; alternate functions MOSI/PCINT2 (SPI data).
13 PB3 bidirectional Port B bit 3 I/O with internal pull-up; alternate functions MISO/PCINT3 (SPI data).
14 PB4 bidirectional Port B bit 4 I/O with internal pull-up; alternate functions OC2A/PCINT4.
15 PB5 bidirectional Port B bit 5 I/O with internal pull-up; alternate functions OC1A/PCINT5.
16 PB6 bidirectional Port B bit 6 I/O with internal pull-up; alternate functions OC1B/PCINT6.
17 PB7 bidirectional Port B bit 7 I/O with internal pull-up; alternate functions OC0A/OC1C/PCINT7.
18 PG3 bidirectional Port G bit 3 I/O with internal pull-up; alternate function TOSC2 (RTC oscillator output when AS2 set).
19 PG4 bidirectional Port G bit 4 I/O with internal pull-up; alternate function TOSC1 (RTC oscillator input when AS2 set).
20 RESET input Active-low reset input; pin is shown with overbar in pinout.
21 VCC power_in Digital supply voltage.
22 GND power_in Ground.
23 XTAL2 output Oscillator/clock circuit pin XTAL2.
24 XTAL1 input Oscillator/clock circuit pin XTAL1 (also used for external clock input).
25 PD0 bidirectional Port D bit 0 I/O with internal pull-up; alternate functions SCL/INT0 (2-wire clock, open-drain when TWI enabled).
26 PD1 bidirectional Port D bit 1 I/O with internal pull-up; alternate functions SDA/INT1 (2-wire data, open-drain when TWI enabled).
27 PD2 bidirectional Port D bit 2 I/O with internal pull-up; alternate functions RXD1/INT2.
28 PD3 bidirectional Port D bit 3 I/O with internal pull-up; alternate functions TXD1/INT3.
29 PD4 bidirectional Port D bit 4 I/O with internal pull-up; alternate function ICP1.
30 PD5 bidirectional Port D bit 5 I/O with internal pull-up; alternate function XCK1.
31 PD6 bidirectional Port D bit 6 I/O with internal pull-up; alternate function T1.
32 PD7 bidirectional Port D bit 7 I/O with internal pull-up; alternate function T0.
33 PG0 bidirectional Port G bit 0 I/O with internal pull-up; alternate function WR (external memory write strobe).
34 PG1 bidirectional Port G bit 1 I/O with internal pull-up; alternate function RD (external memory read strobe).
35 PC0 bidirectional Port C bit 0 I/O with internal pull-up; alternate function A8 (external memory address).
36 PC1 bidirectional Port C bit 1 I/O with internal pull-up; alternate function A9 (external memory address).
37 PC2 bidirectional Port C bit 2 I/O with internal pull-up; alternate function A10 (external memory address).
38 PC3 bidirectional Port C bit 3 I/O with internal pull-up; alternate function A11 (external memory address).
39 PC4 bidirectional Port C bit 4 I/O with internal pull-up; alternate function A12 (external memory address).
40 PC5 bidirectional Port C bit 5 I/O with internal pull-up; alternate function A13 (external memory address).
41 PC6 bidirectional Port C bit 6 I/O with internal pull-up; alternate function A14 (external memory address).
42 PC7 bidirectional Port C bit 7 I/O with internal pull-up; alternate function A15 (external memory address).
43 PG2 bidirectional Port G bit 2 I/O with internal pull-up; alternate function ALE (external memory address latch enable).
44 PA7 bidirectional Port A bit 7 I/O with internal pull-up; alternate function AD7 (external memory address/data).
45 PA6 bidirectional Port A bit 6 I/O with internal pull-up; alternate function AD6 (external memory address/data).
46 PA5 bidirectional Port A bit 5 I/O with internal pull-up; alternate function AD5 (external memory address/data).
47 PA4 bidirectional Port A bit 4 I/O with internal pull-up; alternate function AD4 (external memory address/data).
48 PA3 bidirectional Port A bit 3 I/O with internal pull-up; alternate function AD3 (external memory address/data).
49 PA2 bidirectional Port A bit 2 I/O with internal pull-up; alternate function AD2 (external memory address/data).
50 PA1 bidirectional Port A bit 1 I/O with internal pull-up; alternate function AD1 (external memory address/data).
51 PA0 bidirectional Port A bit 0 I/O with internal pull-up; alternate function AD0 (external memory address/data).
52 VCC power_in Digital supply voltage.
53 GND power_in Ground.
54 PF7 bidirectional Port F bit 7; ADC7 analog input or JTAG TDI.
55 PF6 bidirectional Port F bit 6; ADC6 analog input or JTAG TDO (tri-stated unless shifting data).
56 PF5 bidirectional Port F bit 5; ADC5 analog input or JTAG TMS.
57 PF4 bidirectional Port F bit 4; ADC4 analog input or JTAG TCK.
58 PF3 bidirectional Port F bit 3; ADC3 analog input channel 3.
59 PF2 bidirectional Port F bit 2; ADC2 analog input channel 2.
60 PF1 bidirectional Port F bit 1; ADC1 analog input channel 1.
61 PF0 bidirectional Port F bit 0; ADC0 analog input channel 0.
62 AREF input Analog reference pin for the A/D converter.
63 GND power_in Ground.
64 AVCC power_in Supply voltage pin for the A/D converter.
65 EP power_in Exposed center pad, internally connected to GND; should be soldered or glued to the board for mechanical stability.

Key specifications

Parameter Value
Manufacturer Microchip Tech
Package QFN-64-EP(9x9)
Category Embedded Processors & Controllers
Pins 65

Electrical characteristics

Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).

Parameter Symbol Min Typ Max Unit Conditions Page
Operating temperature range (Industrial) -40 85 °C ATmega1281-16MU, Industrial 409
Power supply voltage VCC 2.7 5.5 V 16 MHz speed grade ordering code ATmega1281-16MU 409
Clock frequency at 2.7V - 5.5V 0 8 MHz ATmega1281, 2.7V - 5.5V 1
Clock frequency at 4.5V - 5.5V 0 16 MHz ATmega1281, 4.5V - 5.5V 1
Minimum pulse width for asynchronous external interrupt tINT 50 ns 110
Programming Enable Voltage VPP 11.5 12.5 V Parallel programming, VCC = 5V ±10% 338
Programming Enable Current IPP 250 µA Parallel programming, VCC = 5V ±10% 338
Data and Control Valid before XTAL1 High tDVXH 67 ns VCC = 5V ±10% 338
XTAL1 Low to XTAL1 High tXLXH 200 ns VCC = 5V ±10% 338
XTAL1 Pulse Width High tXHXL 150 ns VCC = 5V ±10% 338
Data and Control Hold after XTAL1 Low tXLDX 67 ns VCC = 5V ±10% 338
XTAL1 Low to WR Low tXLWL 0 ns VCC = 5V ±10% 338
XTAL1 Low to PAGEL high tXLPH 0 ns VCC = 5V ±10% 338
PAGEL low to XTAL1 high tPLXH 150 ns VCC = 5V ±10% 338
BS1 Valid before PAGEL High tBVPH 67 ns VCC = 5V ±10% 338
PAGEL Pulse Width High tPHPL 150 ns VCC = 5V ±10% 338
BS1 Hold after PAGEL Low tPLBX 67 ns VCC = 5V ±10% 338
BS2/1 Hold after WR Low tWLBX 67 ns VCC = 5V ±10% 338
PAGEL Low to WR Low tPLWL 67 ns VCC = 5V ±10% 338
BS2/1 Valid to WR Low tBVWL 67 ns VCC = 5V ±10% 338
WR Pulse Width Low tWLWH 150 ns VCC = 5V ±10% 338
WR Low to RDY/BSY Low tWLRL 0 1 µs VCC = 5V ±10% 338
WR Low to RDY/BSY High tWLRH 3.7 4.5 ms Valid for Write Flash, Write EEPROM, Write Fuse bits and Write Lock bits commands 338
WR Low to RDY/BSY High for Chip Erase tWLRH_CE 7.5 9 ms Valid for Chip Erase command 338
XTAL1 Low to OE Low tXLOL 0 ns VCC = 5V ±10% 338
BS1 Valid to DATA valid tBVDV 0 250 ns VCC = 5V ±10% 338
OE Low to DATA Valid tOLDV 250 ns VCC = 5V ±10% 338
OE High to DATA Tri-stated tOHDZ 250 ns VCC = 5V ±10% 338

CAD (KiCad official)

  • Symbol: ATMEGA1281-16MU
  • Footprint: Package_DFN_QFN:QFN-64-1EP_9x9mm_P0.5mm_EP6x6mm
  • 3D model: QFN-64-EP(9x9) (KiCad packages3D, STEP)
  • 3D model files: atmega1281-16mu-etched.step / atmega1281-16mu-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); atmega1281-16mu.step / atmega1281-16mu.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: Microchip Tech datasheet (435 pp, sha256 48878ac033dc6185, retrieved 2026-10-31, tier: manufacturer)
  • Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-sonnet-5-5 (text), consensus claude-sonnet-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF