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ATF1508AS-7AX100

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Microchip Tech CPLD/FPGA, TQFP-100(14x14). Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.

componentembedded processors & controllersatf1508as-7ax100factory-2.0.0extractor-text

Verified ATF1508AS-7AX100

by Ray · last 30 Oct 2026 · 1 record · files match
SymbolFootprint3D modelPins

Verification log 1 record

30 Oct 2026RayPublished by the parts factory: tier lcsc, 100 pinsfiles match
SymbolFootprint3D modelPinsfor all variants
  • ✓component-page-verify: PASS
  • ✓cad_props: Datasheet, MPN and distributor properties match page.json
  • ✓component: ATF1508AS-7AX100 · TQFP-100(14x14) · 100 pins
  • ✓copper: 100 copper pads, none touching another net
  • ✓datasheet: all 100 pin names found in the 31-page datasheet
  • ✓distributor: lcsc C1521282, digikey ATF1508AS-7AX100-ND, mouser 556-AF1508AS7AX100
  • ✓family: TQFP-100_14x14mm_P0.5mm
  • ✓files: 7 declared files present
  • ✓hero: docs/hero.png 4000x2500
  • ✓lbr: OK: /tmp/cpv-ig5_rflt/x.lbr is a valid EAGLE .lbr with complete deviceset
  • ✓license: CC-BY-SA-4.0
  • ✓models_3d: 2 records
  • •package_fit (skip): no component.package_dims on the page: the model is unchecked against the datasheet drawing
  • ✓pads: 100 pins = 100 pads
  • ✓pose: 2 STEP(s) Z-up, seated, centred
  • ✓symbol: 100 pins agree
  • ✓visibility: public, source open
Evidencedatasheet
Verified files✓ atf1508as-7ax100.kicad_sym✓ atf1508as-7ax100.kicad_mod✓ atf1508as-7ax100.step
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ATF1508AS-7AX100

Microchip Tech · CPLD/FPGA · TQFP-100(14x14)

ATF1508AS-7AX100 from Microchip Tech, in a TQFP-100(14x14). Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 I/O/PD1 bidirectional Macrocell MC3 (PLB A) I/O pin that also serves as power-down pin PD1; its output level is set by VCCIO (+5 V or 3.3 V).
2 I/O bidirectional Macrocell MC1 (PLB A) I/O pin; its output level is set by VCCIO (+5 V or 3.3 V).
3 VCCIO power_in VCC pin for the output drivers of the I/O pins (+5 V or 3.3 V).
4 I/O/TDI bidirectional Macrocell MC32 (PLB B) I/O pin that also serves as JTAG TDI for boundary-scan testing and in-system programming, with a pull-up option on TDI.
5 I/O bidirectional Macrocell MC30 (PLB B) I/O pin; its output level is set by VCCIO (+5 V or 3.3 V).
6 I/O bidirectional Macrocell MC29 (PLB B) I/O pin; its output level is set by VCCIO (+5 V or 3.3 V).
7 I/O bidirectional Macrocell MC27 (PLB B) I/O pin; its output level is set by VCCIO (+5 V or 3.3 V).
8 I/O bidirectional Macrocell MC25 (PLB B) I/O pin; its output level is set by VCCIO (+5 V or 3.3 V).
9 I/O bidirectional Macrocell MC24 (PLB B) I/O pin; its output level is set by VCCIO (+5 V or 3.3 V).
10 I/O bidirectional Macrocell MC22 (PLB B) I/O pin; its output level is set by VCCIO (+5 V or 3.3 V).
11 GND power_in Ground pin.
12 I/O bidirectional Macrocell MC21 (PLB B) I/O pin; its output level is set by VCCIO (+5 V or 3.3 V).
13 I/O bidirectional Macrocell MC19 (PLB B) I/O pin; its output level is set by VCCIO (+5 V or 3.3 V).
14 I/O bidirectional Macrocell MC17 (PLB B) I/O pin; its output level is set by VCCIO (+5 V or 3.3 V).
15 I/O/TMS bidirectional Macrocell MC48 (PLB C) I/O pin that also serves as JTAG TMS for boundary-scan testing and in-system programming, with a pull-up option on TMS.
16 I/O bidirectional Macrocell MC46 (PLB C) I/O pin; its output level is set by VCCIO (+5 V or 3.3 V).
17 I/O bidirectional Macrocell MC45 (PLB C) I/O pin; its output level is set by VCCIO (+5 V or 3.3 V).
18 VCCIO power_in VCC pin for the output drivers of the I/O pins (+5 V or 3.3 V).
19 I/O bidirectional Macrocell MC43 (PLB C) I/O pin; its output level is set by VCCIO (+5 V or 3.3 V).
20 I/O bidirectional Macrocell MC41 (PLB C) I/O pin; its output level is set by VCCIO (+5 V or 3.3 V).
21 I/O bidirectional Macrocell MC40 (PLB C) I/O pin; its output level is set by VCCIO (+5 V or 3.3 V).
22 I/O bidirectional Macrocell MC38 (PLB C) I/O pin; its output level is set by VCCIO (+5 V or 3.3 V).
23 I/O bidirectional Macrocell MC37 (PLB C) I/O pin; its output level is set by VCCIO (+5 V or 3.3 V).
24 I/O bidirectional Macrocell MC35 (PLB C) I/O pin; its output level is set by VCCIO (+5 V or 3.3 V).
25 I/O bidirectional Macrocell MC33 (PLB C) I/O pin; its output level is set by VCCIO (+5 V or 3.3 V).
26 GND power_in Ground pin.
27 I/O bidirectional Macrocell MC64 (PLB D) I/O pin; its output level is set by VCCIO (+5 V or 3.3 V).
28 I/O bidirectional Macrocell MC62 (PLB D) I/O pin; its output level is set by VCCIO (+5 V or 3.3 V).
29 I/O bidirectional Macrocell MC61 (PLB D) I/O pin; its output level is set by VCCIO (+5 V or 3.3 V).
30 I/O bidirectional Macrocell MC59 (PLB D) I/O pin; its output level is set by VCCIO (+5 V or 3.3 V).
31 I/O bidirectional Macrocell MC57 (PLB D) I/O pin; its output level is set by VCCIO (+5 V or 3.3 V).
32 I/O bidirectional Macrocell MC56 (PLB D) I/O pin; its output level is set by VCCIO (+5 V or 3.3 V).
33 I/O bidirectional Macrocell MC54 (PLB D) I/O pin; its output level is set by VCCIO (+5 V or 3.3 V).
34 VCCIO power_in VCC pin for the output drivers of the I/O pins (+5 V or 3.3 V).
35 I/O bidirectional Macrocell MC53 (PLB D) I/O pin; its output level is set by VCCIO (+5 V or 3.3 V).
36 I/O bidirectional Macrocell MC51 (PLB D) I/O pin; its output level is set by VCCIO (+5 V or 3.3 V).
37 I/O bidirectional Macrocell MC49 (PLB D) I/O pin; its output level is set by VCCIO (+5 V or 3.3 V).
38 GND power_in Ground pin.
39 VCCINT power_in Internal VCC pin for the device (+5 V).
40 I/O bidirectional Macrocell MC65 (PLB E) I/O pin; its output level is set by VCCIO (+5 V or 3.3 V).
41 I/O/PD2 bidirectional Macrocell MC67 (PLB E) I/O pin that also serves as power-down pin PD2; its output level is set by VCCIO (+5 V or 3.3 V).
42 I/O bidirectional Macrocell MC69 (PLB E) I/O pin; its output level is set by VCCIO (+5 V or 3.3 V).
43 GND power_in Ground pin.
44 I/O bidirectional Macrocell MC70 (PLB E) I/O pin; its output level is set by VCCIO (+5 V or 3.3 V).
45 I/O bidirectional Macrocell MC72 (PLB E) I/O pin; its output level is set by VCCIO (+5 V or 3.3 V).
46 I/O bidirectional Macrocell MC73 (PLB E) I/O pin; its output level is set by VCCIO (+5 V or 3.3 V).
47 I/O bidirectional Macrocell MC75 (PLB E) I/O pin; its output level is set by VCCIO (+5 V or 3.3 V).
48 I/O bidirectional Macrocell MC77 (PLB E) I/O pin; its output level is set by VCCIO (+5 V or 3.3 V).
49 I/O bidirectional Macrocell MC78 (PLB E) I/O pin; its output level is set by VCCIO (+5 V or 3.3 V).
50 I/O bidirectional Macrocell MC80 (PLB E) I/O pin; its output level is set by VCCIO (+5 V or 3.3 V).
51 VCCIO power_in VCC pin for the output drivers of the I/O pins (+5 V or 3.3 V).
52 I/O bidirectional Macrocell MC81 (PLB F) I/O pin; its output level is set by VCCIO (+5 V or 3.3 V).
53 I/O bidirectional Macrocell MC83 (PLB F) I/O pin; its output level is set by VCCIO (+5 V or 3.3 V).
54 I/O bidirectional Macrocell MC85 (PLB F) I/O pin; its output level is set by VCCIO (+5 V or 3.3 V).
55 I/O bidirectional Macrocell MC86 (PLB F) I/O pin; its output level is set by VCCIO (+5 V or 3.3 V).
56 I/O bidirectional Macrocell MC88 (PLB F) I/O pin; its output level is set by VCCIO (+5 V or 3.3 V).
57 I/O bidirectional Macrocell MC89 (PLB F) I/O pin; its output level is set by VCCIO (+5 V or 3.3 V).
58 I/O bidirectional Macrocell MC91 (PLB F) I/O pin; its output level is set by VCCIO (+5 V or 3.3 V).
59 GND power_in Ground pin.
60 I/O bidirectional Macrocell MC93 (PLB F) I/O pin; its output level is set by VCCIO (+5 V or 3.3 V).
61 I/O bidirectional Macrocell MC94 (PLB F) I/O pin; its output level is set by VCCIO (+5 V or 3.3 V).
62 I/O/TCK bidirectional Macrocell MC96 (PLB F) I/O pin that also serves as JTAG TCK for boundary-scan testing and in-system programming.
63 I/O bidirectional Macrocell MC97 (PLB G) I/O pin; its output level is set by VCCIO (+5 V or 3.3 V).
64 I/O bidirectional Macrocell MC99 (PLB G) I/O pin; its output level is set by VCCIO (+5 V or 3.3 V).
65 I/O bidirectional Macrocell MC101 (PLB G) I/O pin; its output level is set by VCCIO (+5 V or 3.3 V).
66 VCCIO power_in VCC pin for the output drivers of the I/O pins (+5 V or 3.3 V).
67 I/O bidirectional Macrocell MC102 (PLB G) I/O pin; its output level is set by VCCIO (+5 V or 3.3 V).
68 I/O bidirectional Macrocell MC104 (PLB G) I/O pin; its output level is set by VCCIO (+5 V or 3.3 V).
69 I/O bidirectional Macrocell MC105 (PLB G) I/O pin; its output level is set by VCCIO (+5 V or 3.3 V).
70 I/O bidirectional Macrocell MC107 (PLB G) I/O pin; its output level is set by VCCIO (+5 V or 3.3 V).
71 I/O bidirectional Macrocell MC109 (PLB G) I/O pin; its output level is set by VCCIO (+5 V or 3.3 V).
72 I/O bidirectional Macrocell MC110 (PLB G) I/O pin; its output level is set by VCCIO (+5 V or 3.3 V).
73 I/O/TDO bidirectional Macrocell MC112 (PLB G) I/O pin that also serves as JTAG TDO for boundary-scan testing and in-system programming.
74 GND power_in Ground pin.
75 I/O bidirectional Macrocell MC113 (PLB H) I/O pin; its output level is set by VCCIO (+5 V or 3.3 V).
76 I/O bidirectional Macrocell MC115 (PLB H) I/O pin; its output level is set by VCCIO (+5 V or 3.3 V).
77 I/O bidirectional Macrocell MC117 (PLB H) I/O pin; its output level is set by VCCIO (+5 V or 3.3 V).
78 I/O bidirectional Macrocell MC118 (PLB H) I/O pin; its output level is set by VCCIO (+5 V or 3.3 V).
79 I/O bidirectional Macrocell MC120 (PLB H) I/O pin; its output level is set by VCCIO (+5 V or 3.3 V).
80 I/O bidirectional Macrocell MC121 (PLB H) I/O pin; its output level is set by VCCIO (+5 V or 3.3 V).
81 I/O bidirectional Macrocell MC123 (PLB H) I/O pin; its output level is set by VCCIO (+5 V or 3.3 V).
82 VCCIO power_in VCC pin for the output drivers of the I/O pins (+5 V or 3.3 V).
83 I/O bidirectional Macrocell MC125 (PLB H) I/O pin; its output level is set by VCCIO (+5 V or 3.3 V).
84 I/O bidirectional Macrocell MC126 (PLB H) I/O pin; its output level is set by VCCIO (+5 V or 3.3 V).
85 I/O/GCLK3 bidirectional Macrocell MC128 (PLB H) I/O pin that also serves as global clock pin GCLK3.
86 GND power_in Ground pin.
87 INPUT/GCLK1 input Dedicated input that serves as global clock pin GCLK1.
88 INPUT/OE1 input Dedicated input that serves as global output enable pin OE1.
89 INPUT/GCLR input Dedicated input that serves as the global clear pin GCLR.
90 INPUT/OE2/GCLK2 input Dedicated input that serves as global output enable pin OE2 or global clock pin GCLK2.
91 VCCINT power_in Internal VCC pin for the device (+5 V).
92 I/O bidirectional Macrocell MC16 (PLB A) I/O pin; its output level is set by VCCIO (+5 V or 3.3 V).
93 I/O bidirectional Macrocell MC14 (PLB A) I/O pin; its output level is set by VCCIO (+5 V or 3.3 V).
94 I/O bidirectional Macrocell MC13 (PLB A) I/O pin; its output level is set by VCCIO (+5 V or 3.3 V).
95 GND power_in Ground pin.
96 I/O bidirectional Macrocell MC11 (PLB A) I/O pin; its output level is set by VCCIO (+5 V or 3.3 V).
97 I/O bidirectional Macrocell MC9 (PLB A) I/O pin; its output level is set by VCCIO (+5 V or 3.3 V).
98 I/O bidirectional Macrocell MC8 (PLB A) I/O pin; its output level is set by VCCIO (+5 V or 3.3 V).
99 I/O bidirectional Macrocell MC6 (PLB A) I/O pin; its output level is set by VCCIO (+5 V or 3.3 V).
100 I/O bidirectional Macrocell MC5 (PLB A) I/O pin; its output level is set by VCCIO (+5 V or 3.3 V).

Key specifications

Parameter Value
Manufacturer Microchip Tech
Package TQFP-100(14x14)
Category Embedded Processors & Controllers
Pins 100

Electrical characteristics

Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).

Parameter Symbol Min Typ Max Unit Conditions Page
Operating Temperature (Ambient), Commercial 0 70 °C Commercial range (ATF1508AS-7 AX100 is a commercial part) 14
VCCINT or VCCIO (5V) Power Supply VCCINT, VCCIO 4.75 5.25 V 5V ±5%, Commercial 14
VCCIO (3.3V) Power Supply VCCIO 2.7 3.6 V Commercial and industrial 14
Storage Temperature -65 150 °C 13
Temperature Under Bias -40 85 °C 13
Voltage on Any Pin with Respect to Ground -2 7 V 13
Voltage on Input Pins with Respect to Ground During Programming -2 14 V During programming 13
Programming Voltage with Respect to Ground -2 14 V 13
VCCIO Supply Voltage, 5.0V Device Output VCCIO 4.75 5.25 V 5.0V device output, Commercial 14
VCCIO Supply Voltage, 3.3V Device Output VCCIO 3 3.6 V 3.3V device output 14
Input Low Voltage VIL -0.3 0.8 V 14
Input High Voltage VIH 2 V Printed maximum is VCCIO + 0.3 V (not a fixed number) 14
Output Low Voltage (TTL) VOL 0.45 V VIN = VIH or VIL; VCCIO = MIN, IOL = 12 mA; Commercial 14
Output Low Voltage (CMOS) VOL 0.2 V VIN = VIH or VIL; VCC = MIN, IOL = 0.1 mA 14
Output High Voltage (TTL) VOH 2.4 V VIN = VIH or VIL; VCCIO = MIN, IOH = -4.0 mA 14
Input or I/O Low Leakage Current IIL -10 -2 µA VIN = VCC 14
Input or I/O High Leakage Current IIH 2 10 µA 14
Tri-state Output Off-state Current IOZ -40 40 µA VO = VCC or GND 14
Power Supply Current, Standby (Standard mode, Commercial) ICC1 160 mA VCC = Max; VIN = 0, VCC; Standard mode, Commercial 14
Power Supply Current, Power-down Mode ICC2 1 10 mA VCC = Max; VIN = 0, VCC; PD mode 14
Reduced-power Mode Supply Current (Standard mode, Commercial) ICC3 65 mA VCC = Max; VIN = 0, VCC; Standard mode, Commercial 14
Input Pin Capacitance CIN 8 10 pF VIN = 0V; f = 1.0 MHz 15
I/O Pin Capacitance CI/O 8 10 pF VOUT = 0V; f = 1.0 MHz 15
Input or Feedback to Non-registered Output (-7) tPD1 7.5 ns 19
I/O Input or Feedback to Non-registered Feedback (-7) tPD2 7 ns 19
Global Clock Setup Time (-7) tSU 6 ns 19
Global Clock Hold Time (-7) tH 0 ns 19
Global Clock Setup Time of Fast Input (-7) tFSU 3 ns 19
Global Clock Hold Time of Fast Input (-7) tFH 0.5 MHz Unit as printed in datasheet row 19
Global Clock to Output Delay (-7) tCOP 4.5 ns 19
Global Clock High Time (-7) tCH 3 ns 19
Global Clock Low Time (-7) tCL 3 ns 19
Array Clock Setup Time (-7) tASU 3 ns 19
Array Clock Hold Time (-7) tAH 2 ns 19
Array Clock Output Delay (-7) tACOP 7.5 ns 19
Array Clock High Time (-7) tACH 3 ns 19
Array Clock Low Time (-7) tACL 3 ns 19
Maximum Internal Global Clock Frequency (-7) fMAX 166.7 MHz 19
Foldback Term Delay (-7) tSEXP 4 ns 19
Logic Array Delay (-7) tLAD 3 ns 20
Logic Control Delay (-7) tLAC 3 ns 20
Internal Output Enable Delay (-7) tIOE 2 ns 20
Output Buffer and Pad Delay (-7) tOD1 2 ns Slow slew rate = OFF; VCCIO = 5V; CL = 35 pF 19
Output Buffer and Pad Delay (-7) tOD2 2.5 ns Slow slew rate = OFF; VCCIO = 3.3V; CL = 35 pF 20
Output Buffer and Pad Delay (-7) tOD3 5 ns Slow slew rate = ON; VCCIO = 5V or 3.3V; CL = 35 pF 20
Output Buffer Enable Delay (-7) tZX1 4 ns Slow slew rate = OFF; VCCIO = 5.0V; CL = 35 pF 20
Output Buffer Enable Delay (-7) tZX2 4.5 ns Slow slew rate = OFF; VCCIO = 3.3V; CL = 35 pF 20
Output Buffer Enable Delay (-7) tZX3 9 ns Slow slew rate = ON; VCCIO = 5.0V/3.3V; CL = 35 pF 20
Output Buffer Disable Delay (-7) tXZ 4 ns CL = 5 pF 20
Register Setup Time (-7) tSU 3 ns 20
Register Hold Time (-7) tH 2 ns 20
Register Setup Time of Fast Input (-7) tFSU 3 ns 20
Register Hold Time of Fast Input (-7) tFH 0.5 ns 20
Array Clock Delay (-7) tIC 3 ns 20
Register Enable Time (-7) tEN 3 ns 20
Register Preset Time (-7) tPRE 2 ns 20
Register Clear Time (-7) tCLR 2 ns 20
Reduced-power Adder (-7) tRPA 10 ns Added to tLAD, tLAC, tTIC, tACL, tSEXP for reduced-power macrocells (note 2) 20

CAD (KiCad official)

  • Symbol: ATF1508AS-7AX100
  • Footprint: Package_QFP:TQFP-100_14x14mm_P0.5mm
  • 3D model: TQFP-100(14x14) (KiCad packages3D, STEP)
  • 3D model files: atf1508as-7ax100-etched.step / atf1508as-7ax100-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); atf1508as-7ax100.step / atf1508as-7ax100.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: Microchip Tech datasheet (31 pp, sha256 cfb292132e1ac86b, retrieved 2026-10-30, tier: lcsc)
  • Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-haiku-5-5 (text), consensus claude-sonnet-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF