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ATF1508AS-10AU100

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Microchip Tech Programmable Logic Device (CPLDs/FPGAs), TQFP-100(14x14). Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.

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Verified ATF1508AS-10AU100

by Ray · last 31 Oct 2026 · 1 record · files match
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Verification log 1 record

31 Oct 2026RayPublished by the parts factory: tier lcsc, 100 pinsfiles match
SymbolFootprint3D modelPinsfor all variants
  • ✓component-page-verify: PASS
  • ✓cad_props: Datasheet, MPN and distributor properties match page.json
  • ✓component: ATF1508AS-10AU100 · TQFP-100(14x14) · 100 pins
  • ✓copper: 100 copper pads, none touching another net
  • ✓datasheet: all 100 pin names found in the 31-page datasheet
  • ✓distributor: lcsc C31179, digikey ATF1508AS-10AU100-ND, mouser 556-AF1508AS10AU100
  • ✓family: TQFP-100_14x14mm_P0.5mm
  • ✓files: 7 declared files present
  • ✓hero: docs/hero.png 4000x2500
  • ✓lbr: OK: /tmp/cpv-fcrqgi0p/x.lbr is a valid EAGLE .lbr with complete deviceset
  • ✓license: CC-BY-SA-4.0
  • ✓models_3d: 2 records
  • •package_fit (skip): no component.package_dims on the page: the model is unchecked against the datasheet drawing
  • ✓pads: 100 pins = 100 pads
  • ✓pose: 2 STEP(s) Z-up, seated, centred
  • ✓symbol: 100 pins agree
  • ✓visibility: public, source open
Evidencedatasheet
Verified files✓ atf1508as-10au100.kicad_sym✓ atf1508as-10au100.kicad_mod✓ atf1508as-10au100.step
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Contents

README

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ATF1508AS-10AU100

Microchip Tech · Programmable Logic Device (CPLDs/FPGAs) · TQFP-100(14x14)

ATF1508AS-10AU100 from Microchip Tech, in a TQFP-100(14x14). Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 I/O/PD1 bidirectional General-purpose I/O that doubles as power-down pin 1 (PD1).
2 I/O bidirectional General-purpose I/O pin (macrocell 1).
3 VCCIO power_in Supply for output drivers of the I/O pins, +5V or 3.3V.
4 I/O/TDI bidirectional General-purpose I/O that doubles as the JTAG TDI pin for boundary scan and in-system programming.
5 I/O bidirectional General-purpose I/O pin (macrocell 30).
6 I/O bidirectional General-purpose I/O pin (macrocell 29).
7 I/O bidirectional General-purpose I/O pin (macrocell 27).
8 I/O bidirectional General-purpose I/O pin (macrocell 25).
9 I/O bidirectional General-purpose I/O pin (macrocell 24).
10 I/O bidirectional General-purpose I/O pin (macrocell 22).
11 GND power_in Ground pin.
12 I/O bidirectional General-purpose I/O pin (macrocell 21).
13 I/O bidirectional General-purpose I/O pin (macrocell 19).
14 I/O bidirectional General-purpose I/O pin (macrocell 17).
15 I/O/TMS bidirectional General-purpose I/O that doubles as the JTAG TMS pin for boundary scan and in-system programming.
16 I/O bidirectional General-purpose I/O pin (macrocell 46).
17 I/O bidirectional General-purpose I/O pin (macrocell 45).
18 VCCIO power_in Supply for output drivers of the I/O pins, +5V or 3.3V.
19 I/O bidirectional General-purpose I/O pin (macrocell 43).
20 I/O bidirectional General-purpose I/O pin (macrocell 41).
21 I/O bidirectional General-purpose I/O pin (macrocell 40).
22 I/O bidirectional General-purpose I/O pin (macrocell 38).
23 I/O bidirectional General-purpose I/O pin (macrocell 37).
24 I/O bidirectional General-purpose I/O pin (macrocell 35).
25 I/O bidirectional General-purpose I/O pin (macrocell 33).
26 GND power_in Ground pin.
27 I/O bidirectional General-purpose I/O pin (macrocell 64).
28 I/O bidirectional General-purpose I/O pin (macrocell 62).
29 I/O bidirectional General-purpose I/O pin (macrocell 61).
30 I/O bidirectional General-purpose I/O pin (macrocell 59).
31 I/O bidirectional General-purpose I/O pin (macrocell 57).
32 I/O bidirectional General-purpose I/O pin (macrocell 56).
33 I/O bidirectional General-purpose I/O pin (macrocell 54).
34 VCCIO power_in Supply for output drivers of the I/O pins, +5V or 3.3V.
35 I/O bidirectional General-purpose I/O pin (macrocell 53).
36 I/O bidirectional General-purpose I/O pin (macrocell 51).
37 I/O bidirectional General-purpose I/O pin (macrocell 49).
38 GND power_in Ground pin.
39 VCCINT power_in Internal device supply, +5V.
40 I/O bidirectional General-purpose I/O pin (macrocell 65).
41 I/O/PD2 bidirectional General-purpose I/O that doubles as power-down pin 2 (PD2).
42 I/O bidirectional General-purpose I/O pin (macrocell 69).
43 GND power_in Ground pin.
44 I/O bidirectional General-purpose I/O pin (macrocell 70).
45 I/O bidirectional General-purpose I/O pin (macrocell 72).
46 I/O bidirectional General-purpose I/O pin (macrocell 73).
47 I/O bidirectional General-purpose I/O pin (macrocell 75).
48 I/O bidirectional General-purpose I/O pin (macrocell 77).
49 I/O bidirectional General-purpose I/O pin (macrocell 78).
50 I/O bidirectional General-purpose I/O pin (macrocell 80).
51 VCCIO power_in Supply for output drivers of the I/O pins, +5V or 3.3V.
52 I/O bidirectional General-purpose I/O pin (macrocell 81).
53 I/O bidirectional General-purpose I/O pin (macrocell 83).
54 I/O bidirectional General-purpose I/O pin (macrocell 85).
55 I/O bidirectional General-purpose I/O pin (macrocell 86).
56 I/O bidirectional General-purpose I/O pin (macrocell 88).
57 I/O bidirectional General-purpose I/O pin (macrocell 89).
58 I/O bidirectional General-purpose I/O pin (macrocell 91).
59 GND power_in Ground pin.
60 I/O bidirectional General-purpose I/O pin (macrocell 93).
61 I/O bidirectional General-purpose I/O pin (macrocell 94).
62 I/O/TCK bidirectional General-purpose I/O that doubles as the JTAG TCK pin for boundary scan and in-system programming.
63 I/O bidirectional General-purpose I/O pin (macrocell 97).
64 I/O bidirectional General-purpose I/O pin (macrocell 99).
65 I/O bidirectional General-purpose I/O pin (macrocell 101).
66 VCCIO power_in Supply for output drivers of the I/O pins, +5V or 3.3V.
67 I/O bidirectional General-purpose I/O pin (macrocell 102).
68 I/O bidirectional General-purpose I/O pin (macrocell 104).
69 I/O bidirectional General-purpose I/O pin (macrocell 105).
70 I/O bidirectional General-purpose I/O pin (macrocell 107).
71 I/O bidirectional General-purpose I/O pin (macrocell 109).
72 I/O bidirectional General-purpose I/O pin (macrocell 110).
73 I/O/TDO bidirectional General-purpose I/O that doubles as the JTAG TDO pin for boundary scan and in-system programming.
74 GND power_in Ground pin.
75 I/O bidirectional General-purpose I/O pin (macrocell 113).
76 I/O bidirectional General-purpose I/O pin (macrocell 115).
77 I/O bidirectional General-purpose I/O pin (macrocell 117).
78 I/O bidirectional General-purpose I/O pin (macrocell 118).
79 I/O bidirectional General-purpose I/O pin (macrocell 120).
80 I/O bidirectional General-purpose I/O pin (macrocell 121).
81 I/O bidirectional General-purpose I/O pin (macrocell 123).
82 VCCIO power_in Supply for output drivers of the I/O pins, +5V or 3.3V.
83 I/O bidirectional General-purpose I/O pin (macrocell 125).
84 I/O bidirectional General-purpose I/O pin (macrocell 126).
85 I/O/GCLK3 bidirectional General-purpose I/O that doubles as global clock pin 3 (GCLK3).
86 GND power_in Ground pin.
87 INPUT/GCLK1 input Dedicated input that doubles as global clock pin 1 (GCLK1).
88 INPUT/OE1 input Dedicated input that doubles as global output enable pin 1 (OE1).
89 INPUT/GCLR input Dedicated input that doubles as the global clear pin (GCLR).
90 INPUT/OE2/GCLK2 input Dedicated input that doubles as global output enable pin 2 (OE2) and global clock pin 2 (GCLK2).
91 VCCINT power_in Internal device supply, +5V.
92 I/O bidirectional General-purpose I/O pin (macrocell 16).
93 I/O bidirectional General-purpose I/O pin (macrocell 14).
94 I/O bidirectional General-purpose I/O pin (macrocell 13).
95 GND power_in Ground pin.
96 I/O bidirectional General-purpose I/O pin (macrocell 11).
97 I/O bidirectional General-purpose I/O pin (macrocell 9).
98 I/O bidirectional General-purpose I/O pin (macrocell 8).
99 I/O bidirectional General-purpose I/O pin (macrocell 6).
100 I/O bidirectional General-purpose I/O pin (macrocell 5).

Key specifications

Parameter Value
Manufacturer Microchip Tech
Package TQFP-100(14x14)
Category Single Chip Microcomputer/Microcontroller
Pins 100

Electrical characteristics

Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).

Parameter Symbol Min Typ Max Unit Conditions Page
Operating Temperature (Ambient), Industrial -40 85 °C Industrial 14
VCCINT or VCCIO (5V) Power Supply, Industrial VCCINT/VCCIO 4.5 5.5 V 5V ± 10%, Industrial 14
VCCIO (3.3V) Power Supply VCCIO 2.7 3.6 V Industrial 14
Supply Voltage 5.0V Device Output, Ind. VCCIO 4.5 5.5 V 5.0V Device Output, Ind. 14
Supply Voltage 3.3V Device Output VCCIO 3 3.6 V 3.3V Device Output 14
Input Low Voltage VIL -0.3 0.8 V 14
Input High Voltage VIH 2 V max printed as VCCIO + 0.3 14
Input or I/O Low Leakage Current IIL -2 -10 µA VIN = VCC 14
Input or I/O High Leakage Current IIH 2 10 µA VIN = VCC 14
Tri-state Output Off-state Current IOZ -40 40 µA VO = VCC or GND 14
Power Supply Current, Standby, Std Mode Ind. ICC1 180 mA VCC = Max, VIN = 0, VCC, Std Mode Ind. 14
Power Supply Current, Power-down Mode ICC2 1 10 mA VCC = Max, VIN = 0, VCC, PD Mode 14
Reduced-power Mode Supply Current, Std Mode Ind. ICC3 85 mA VCC = Max, VIN = 0, VCC, Std Mode Ind. 14
Output Low Voltage (TTL), Ind. VOL 0.45 V VIN = VIH or VIL, VCCIO = MIN, IOL = 12 mA 14
Output Low Voltage (CMOS), Ind. VOL 0.2 V VIN = VIH or VIL, VCC = MIN, IOL = 0.1 mA 14
Output High Voltage (TTL) VOH 2.4 V VIN = VIH or VIL, VCCIO = MIN, IOH = -4.0 mA 14
Input to Non-registered Output Delay (-10) tPD1 10 ns Input or Feedback to Non-registered Output 19
I/O Input to Non-registered Feedback (-10) tPD2 9 ns I/O Input or Feedback to Non-registered Feedback 19
Global Clock Setup Time (-10) tSU 7 ns Global Clock 19
Global Clock Hold Time (-10) tH 0 ns Global Clock 19
Global Clock Setup Time of Fast Input (-10) tFSU 3 ns 19
Global Clock to Output Delay (-10) tCOP 5 ns 19
Global Clock High Time (-10) tCH 4 ns 19
Global Clock Low Time (-10) tCL 4 ns 19
Array Clock Setup Time (-10) tASU 3 ns 19
Array Clock Hold Time (-10) tAH 3 ns 19
Array Clock Output Delay (-10) tACOP 10 ns 19
Array Clock High Time (-10) tACH 4 ns 19
Array Clock Low Time (-10) tACL 4 ns 19
Minimum Clock Global Period (-10) tCNT 10 ns 19
Maximum Internal Global Clock Frequency (-10) fCNT 100 MHz 19
Minimum Array Clock Period (-10) tACNT 10 ns 19
Maximum Internal Array Clock Frequency (-10) fACNT 100 MHz 19
Maximum Clock Frequency (-10) fMAX 125 MHz 19
Output Buffer and Pad Delay, slow slew OFF, 5V (-10) tOD1 1.5 ns Slow slew rate = OFF; VCCIO = 5V; CL = 35 pF 19
Output Buffer and Pad Delay, slow slew OFF, 3.3V (-10) tOD2 2 ns Slow slew rate = OFF; VCCIO = 3.3V; CL = 35 pF 19
Output Buffer and Pad Delay, slow slew ON (-10) tOD3 5.5 ns Slow slew rate = ON; VCCIO = 5V or 3.3V; CL = 35 pF 19
Output Buffer Enable Delay, slow slew OFF, 5.0V (-10) tZX1 5 ns Slow slew rate = OFF; VCCIO = 5.0V; CL = 35 pF 20
Output Buffer Enable Delay, slow slew OFF, 3.3V (-10) tZX2 5.5 ns Slow slew rate = OFF; VCCIO = 3.3V; CL = 35 pF 20
Output Buffer Enable Delay, slow slew ON (-10) tZX3 9 ns Slow slew rate = ON; VCCIO = 5.0V/3.3V; CL = 35 pF 20
Output Buffer Disable Delay (-10) tXZ 5 ns CL = 5 pF 20
Reduced-power Adder (-10) tRPA 11 ns 20
Temperature Under Bias -40 85 °C 13
Storage Temperature -65 150 °C 13
Voltage on Any Pin with Respect to Ground -2 7 V Min -0.6V DC, may undershoot to -2.0V for pulses <20 ns; max output pin VCC + 0.75V DC, overshoot to 7.0V for <20 ns 13
Voltage on Input Pins with Respect to Ground During Programming -2 14 V 13
Programming Voltage with Respect to Ground -2 14 V 13
Input Pin Capacitance CIN 8 10 pF VIN = 0V; f = 1.0 MHz 15
I/O Pin Capacitance CI/O 8 10 pF VOUT = 0V; f = 1.0 MHz 15

CAD (KiCad official)

  • Symbol: ATF1508AS-10AU100
  • Footprint: Package_QFP:TQFP-100_14x14mm_P0.5mm
  • 3D model: TQFP-100(14x14) (KiCad packages3D, STEP)
  • 3D model files: atf1508as-10au100-etched.step / atf1508as-10au100-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); atf1508as-10au100.step / atf1508as-10au100.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: Microchip Tech datasheet (31 pp, sha256 cfb292132e1ac86b, retrieved 2026-10-31, tier: lcsc)
  • Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-sonnet-5-5 (text), consensus claude-sonnet-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF