ATF1504ASVL-20AU44 from Microchip Tech, in a TQFP-44(10x10). Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model). Symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin	Name	Type	Function
1	I/O/TDI	bidirectional	Bidirectional I/O on macrocell 8 (PLC A) that serves as the JTAG TDI input, with a pull-up option on TDI selected as a design option.
2	I/O	bidirectional	Bidirectional I/O on macrocell 5 (PLC A) with programmable pin-keeper, programmable output slew rate and programmable open-collector options.
3	I/O	bidirectional	Bidirectional I/O on macrocell 4 (PLC A) with programmable pin-keeper, programmable output slew rate and programmable open-collector options.
4	GND	power_in	Ground pin for the device.
5	I/O/PD1	bidirectional	Bidirectional I/O on macrocell 3 (PLC A) that also serves as power-down pin PD1 for the pin-controlled standby mode (100 µA typical).
6	I/O	bidirectional	Bidirectional I/O on macrocell 1 (PLC A) with programmable pin-keeper, programmable output slew rate and programmable open-collector options.
7	I/O/TMS	bidirectional	Bidirectional I/O on macrocell 32 (PLC B) that serves as the JTAG TMS input, with a pull-up option on TMS selected as a design option.
8	I/O	bidirectional	Bidirectional I/O on macrocell 30 (PLC B) with programmable pin-keeper, programmable output slew rate and programmable open-collector options.
9	VCC	power_in	Supply voltage pin (VCC, VCCINT/VCCIO) for the device, operating range 3.0V to 3.6V.
10	I/O	bidirectional	Bidirectional I/O on macrocell 25 (PLC B) with programmable pin-keeper, programmable output slew rate and programmable open-collector options.
11	I/O	bidirectional	Bidirectional I/O on macrocell 24 (PLC B) with programmable pin-keeper, programmable output slew rate and programmable open-collector options.
12	I/O	bidirectional	Bidirectional I/O on macrocell 21 (PLC B) with programmable pin-keeper, programmable output slew rate and programmable open-collector options.
13	I/O	bidirectional	Bidirectional I/O on macrocell 20 (PLC B) with programmable pin-keeper, programmable output slew rate and programmable open-collector options.
14	I/O	bidirectional	Bidirectional I/O on macrocell 19 (PLC B) with programmable pin-keeper, programmable output slew rate and programmable open-collector options.
15	I/O	bidirectional	Bidirectional I/O on macrocell 17 (PLC B) with programmable pin-keeper, programmable output slew rate and programmable open-collector options.
16	GND	power_in	Ground pin for the device.
17	VCC	power_in	Supply voltage pin (VCC, VCCINT/VCCIO) for the device, operating range 3.0V to 3.6V.
18	I/O	bidirectional	Bidirectional I/O on macrocell 33 (PLC C) with programmable pin-keeper, programmable output slew rate and programmable open-collector options.
19	I/O/PD2	bidirectional	Bidirectional I/O on macrocell 35 (PLC C) that also serves as power-down pin PD2 for the pin-controlled standby mode (100 µA typical).
20	I/O	bidirectional	Bidirectional I/O on macrocell 36 (PLC C) with programmable pin-keeper, programmable output slew rate and programmable open-collector options.
21	I/O	bidirectional	Bidirectional I/O on macrocell 37 (PLC C) with programmable pin-keeper, programmable output slew rate and programmable open-collector options.
22	I/O	bidirectional	Bidirectional I/O on macrocell 40 (PLC C) with programmable pin-keeper, programmable output slew rate and programmable open-collector options.
23	I/O	bidirectional	Bidirectional I/O on macrocell 41 (PLC C) with programmable pin-keeper, programmable output slew rate and programmable open-collector options.
24	GND	power_in	Ground pin for the device.
25	I/O	bidirectional	Bidirectional I/O on macrocell 46 (PLC C) with programmable pin-keeper, programmable output slew rate and programmable open-collector options.
26	I/O/TCK	bidirectional	Bidirectional I/O on macrocell 48 (PLC C) that serves as the JTAG TCK pin used for boundary-scan testing and in-system programming.
27	I/O	bidirectional	Bidirectional I/O on macrocell 49 (PLC D) with programmable pin-keeper, programmable output slew rate and programmable open-collector options.
28	I/O	bidirectional	Bidirectional I/O on macrocell 51 (PLC D) with programmable pin-keeper, programmable output slew rate and programmable open-collector options.
29	VCC	power_in	Supply voltage pin (VCC, VCCINT/VCCIO) for the device, operating range 3.0V to 3.6V.
30	I/O	bidirectional	Bidirectional I/O on macrocell 52 (PLC D) with programmable pin-keeper, programmable output slew rate and programmable open-collector options.
31	I/O	bidirectional	Bidirectional I/O on macrocell 53 (PLC D) with programmable pin-keeper, programmable output slew rate and programmable open-collector options.
32	I/O/TDO	bidirectional	Bidirectional I/O on macrocell 56 (PLC D) that serves as the JTAG TDO pin used for boundary-scan testing and in-system programming.
33	I/O	bidirectional	Bidirectional I/O on macrocell 57 (PLC D) with programmable pin-keeper, programmable output slew rate and programmable open-collector options.
34	I/O	bidirectional	Bidirectional I/O on macrocell 62 (PLC D) with programmable pin-keeper, programmable output slew rate and programmable open-collector options.
35	I/O/GCLK3	bidirectional	Bidirectional I/O on macrocell 64 (PLC D) that can also serve as global clock pin GCLK3.
36	GND	power_in	Ground pin for the device.
37	INPUT/GCLK1	input	Dedicated input that can serve as global clock GCLK1, selectable individually within each macrocell as register clock, register reset or output enable.
38	INPUT/OE1	input	Dedicated input that serves as global output enable OE1, selectable individually within each macrocell.
39	INPUT/GCLR	input	Dedicated input that serves as the global clear GCLR for macrocell registers, selectable individually within each macrocell.
40	INPUT/OE2/GCLK2	input	Dedicated input that can serve as global output enable OE2 or global clock GCLK2, selectable individually within each macrocell.
41	VCC	power_in	Supply voltage pin (VCC, VCCINT/VCCIO) for the device, operating range 3.0V to 3.6V.
42	I/O	bidirectional	Bidirectional I/O on macrocell 16 (PLC A) with programmable pin-keeper, programmable output slew rate and programmable open-collector options.
43	I/O	bidirectional	Bidirectional I/O on macrocell 14 (PLC A) with programmable pin-keeper, programmable output slew rate and programmable open-collector options.
44	I/O	bidirectional	Bidirectional I/O on macrocell 11 (PLC A) with programmable pin-keeper, programmable output slew rate and programmable open-collector options.

Key specifications

Parameter	Value
Manufacturer	Microchip Tech
Package	TQFP-44(10x10)
Category	Embedded Processors & Controllers
Pins	44

Electrical characteristics

Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).

Parameter	Symbol	Min	Typ	Max	Unit	Conditions	Page
Temperature under bias		-40		85	°C		8
Storage temperature		-65		150	°C		8
Voltage on any pin with respect to ground		-2		7	V	See Note 1: DC minimum -0.6V, undershoot to -2.0V for pulses <20 ns	8
Operating Temperature (Ambient), Industrial		-40		85	°C		8
VCC (VCCIO/VCCINT) Power Supply	VCC	3		3.6	V		8
Input or I/O Low Leakage Current	IIL		-2	-10	µA	VIN = GND	8
Input or I/O High Leakage Current	IIH		2	10	µA	VIN = VCC	8
Tri-State Output Off-State Current	IOZ	-40		40	µA	VO = VCC or GND	8
Power-Down mode Supply Current (PD mode)	ICC2		0.1	5	mA	VCC = Max, VIN = 0, VCC; PD mode	8
Input Low Voltage	VIL	-0.3		0.8	V		8
Input High Voltage	VIH	1.7			V		8
Output Low Voltage (3.3V TTL)	VOL			0.45	V	VIN = VIH or VIL; VCCIO = Min, IOL = 8 mA	8
Output Low Voltage (3.3V CMOS)	VOL			0.2	V	VIN = VIH or VIL; VCCIO = Min, IOL = 0.1 mA	8
Output High Voltage (3.3V TTL)	VOH	2.4			V	VIN = VIH or VIL; VCCIO = Min, IOH = -1.5 mA	8
Input Capacitance	CIN			8	pF	VIN = 0V; f = 1.0 MHz	9
I/O Capacitance	CI/O			8	pF	VOUT = 0V; f = 1.0 MHz	9
Input or Feedback to Non-Registered Output	tPD1			20	ns		9
I/O Input or Feedback to Non-Registered Feedback	tPD2			16	ns		9
Global Clock Setup Time	tSU	13.5			ns		9
Global Clock Hold Time	tH	0			ns		9
Global Clock Setup Time of Fast Input	tFSU	3			ns		9
Global Clock Hold Time of Fast Input	tFH	2			ns		9
Global Clock to Output Delay	tCOP			12	ns		9
Array Clock Setup Time	tASU	7			ns		9
Array Clock Hold Time	tAH	4			ns		9
Array Clock Output Delay	tACOP			18.5	ns		9
Array Clock High Time	tACH	8			ns		9
Array Clock Low Time	tACL	8			ns		10
Minimum Clock Global Period	tCNT			17	ns		10
Maximum Internal Global Clock Frequency	fCNT	66			MHz		10
Minimum Array Clock Period	tACNT			17	ns		10
Maximum Internal Array Clock Frequency	fACNT	58.8			MHz		10
Maximum Clock Frequency	fMAX	83.3			MHz		10
Fast Input Delay	tFIN			2	ns		10
Foldback Term Delay	tSEXP			10	ns		10
Logic Array Delay	tLAD			8	ns		10
Logic Control Delay	tLAC			4.5	ns		10
Output Buffer and Pad Delay (Slow slew rate OFF)	tOD1			4	ns	Slow slew rate = OFF; VCCIO = 3.3V; CL = 35 pF	10
Output Buffer and Pad Delay (Slow slew rate ON)	tOD3			6	ns	Slow slew rate = ON; VCCIO = 3.3V; CL = 35 pF	10
Output Buffer Enable Delay (Slow slew rate OFF)	tZX1			9	ns	Slow slew rate = OFF; VCCIO = 3.3V; CL = 35 pF	10
Output Buffer Enable Delay (Slow slew rate ON)	tZX3			11	ns	Slow slew rate = ON; VCCIO = 3.3V; CL = 35 pF	10
Output Buffer Disable Delay	tXZ			7	ns	CL = 5 pF	10
Register Setup Time	tSU	6			ns		10
Register Hold Time	tH	5			ns		10
Register Setup Time of Fast Input	tFSU	2			ns		10
Register Hold Time of Fast Input	tFH	2			ns		10
Combinatorial Delay	tCOMB			3	ns		10
Array Clock Delay	tIC			7	ns		10
Register Enable Time	tEN			7	ns		10
Reduced-Power Adder	tRPA			13	ns		11
Valid I, I/O before PD High	tIVDH	20			ns		12
Valid OE before PD High	tGVDH	20			ns		12
Valid Clock before PD High	tCVDH	20			ns		12
I, I/O Don't Care after PD High	tDHIX			30	ns		12
OE Don't Care after PD High	tDHGX			30	ns		12
Clock Don't Care after PD High	tDHCX			30	ns		12
PD Low to Valid I, I/O	tDLIV			1	µs		12
PD Low to Valid OE (Pin or Term)	tDLGV			1	µs		12
PD Low to Valid Clock (Pin or Term)	tDLCV			1	µs		12
PD Low to Valid Output	tDLOV			1	µs		12

CAD (KiCad official)

Symbol: ATF1504ASVL-20AU44
Footprint: Package_QFP:TQFP-44_10x10mm_P0.8mm
3D model: TQFP-44(10x10) (KiCad packages3D, STEP)
3D model files: atf1504asvl-20au44-etched.step / atf1504asvl-20au44-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); atf1504asvl-20au44.step / atf1504asvl-20au44.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

Datasheet: Microchip Tech datasheet (30 pp, sha256 1dd868cd32f411ad, retrieved 2026-11-13, tier: manufacturer)
Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-haiku-5-5 (text), consensus claude-sonnet-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF

ATF1504ASVL-20AU44

Verified ATF1504ASVL-20AU44

Verification log 1 record

3D Model

Symbol & Footprint

Schematic Symbol

PCB Footprint

Datasheet

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