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ATECC608B-SSHDA-B

Microchip Tech · Security Verification / Encryption ICs · SOIC-8

ATECC608B-SSHDA-B from Microchip Tech, in a SOIC-8. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 NC unconnected Pin 1 is a no-connect on the 8-lead SOIC and should be left unconnected.
2 NC unconnected Pin 2 is a no-connect on the 8-lead SOIC and should be left unconnected.
3 NC unconnected Pin 3 is a no-connect on the 8-lead SOIC and should be left unconnected.
4 GND power_in Ground reference for the device supply and I/O levels.
5 SDA bidirectional Serial data line of the standard I2C interface, supporting clock rates up to 1 MHz.
6 SCL input Serial clock input of the standard I2C interface, supporting clock rates up to 1 MHz.
7 NC unconnected Pin 7 is a no-connect on the 8-lead SOIC and should be left unconnected.
8 VCC power_in Supply pin with a 2.0V to 5.5V supply voltage range and 1.8V to 5.5V I/O levels.

Key specifications

Parameter Value
Manufacturer Microchip Tech
Package SOIC-8
Category Communication Interface Chip/UART/485/232
Pins 8

Electrical characteristics

Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).

Parameter Symbol Min Typ Max Unit Conditions Page
Operating Temperature (abs max) -40 100 °C 6
Storage Temperature -65 150 °C 6
Maximum Operating Voltage 6 V 6
DC Output Current 5 mA 6
Voltage on any pin -0.5 V -0.5V to (VCC + 0.5V) 6
ESD HBM 4 kV Human Body Model, >4kV 6
ESD CDM 1 kV Charge Device Model, >1kV 6
Ambient Operating Temperature TA -40 85 °C Standard Industrial Temperature Range 10
Power Supply Voltage VCC 2 5.5 V 10
Active Power Supply Current ICC 2 3 mA Waiting for I/O during I/O transfers or execution of non-ECC commands. Independent of Clock Divider value. 10
Active Power Supply Current, ECC ICC 14 mA During ECC command execution. Clock divider = 0x0 10
Active Power Supply Current, ECC ICC 6 mA During ECC command execution. Clock divider = 0x5 10
Active Power Supply Current, ECC ICC 3 mA During ECC command execution. Clock divider = 0xD 10
Idle Power Supply Current IIDLE 800 µA Idle mode, VSDA and VSCL < 0.4V or > VCC, 0.4 10
Sleep Current ISLEEP 30 150 nA Sleep mode, VCC ≤ 3.6V, VSDA and VSCL < 0.4V or > VCC, 0.4, TA ≤ +55°C 10
Sleep Current, full range ISLEEP 2 µA Sleep mode. Over full VCC and temperature range. 10
Output Low Voltage VOL 0.4 V Active mode, VCC = 2.5 to 5.5V 10
Output Low Current IOL 4 mA Active mode, VCC = 2.5 to 5.5V, VOL = 0.4V 10
Input Low Voltage VIL -0.5 0.5 V Device active and TTLenable bit in Configuration memory is zero 10
Input High Voltage VIH 1.5 V Device active and TTLenable bit zero; max printed as VCC + 0.5 10
Theta JA ƟJA 166 °C/W SOIC (SSH) 10
Write Endurance 400000 Write Cycles at +85°C (Each Byte) 6
Data Retention 10 Years at +55°C 6
Data Retention 30 50 Years at +35°C 6
Power-Up Delay tPU 100 µs Minimum time between VCC > VCC min prior to start of tWLO. 7
Wake Low Duration tWLO 60 µs 7
Wake High Delay to Data Comm tWHI 1500 µs SDA stable high for this entire duration unless polling is implemented. SelfTest is not enabled at power-up. 7
Wake High Delay when SelfTest is Enabled tWHIST 20 ms SDA stable high for this entire duration unless polling is implemented. 7
High-Side Glitch Filter at Active tHIGNORE_A 45 ns Pulses shorter than this in width will be ignored, regardless of state when active. 7
Low-Side Glitch Filter at Active tLIGNORE_A 45 ns Pulses shorter than this in width will be ignored, regardless of state when active. 7
Low-Side Glitch Filter at Sleep tLIGNORE_S 15 µs Pulses shorter than this in width will be ignored when in Sleep mode. 7
Watchdog Time-out tWATCHDOG 0.7 1.3 1.7 s Time from wake until device forced into Sleep mode if Config.ChipMode[2] is 0. 7
SCL Clock Frequency fSCL 0 1 MHz TA = -40°C to +100°C, VCC = +2.0V to +5.5V, CL = 1 TTL Gate and 100 pF 9
SCL High Time tHIGH 400 ns 9
SCL Low Time tLOW 400 ns 9
Start Setup Time tSU.STA 250 ns 9
Start Hold Time tHD.STA 250 ns 9
Stop Setup Time tSU.STO 250 ns 9
Data In Setup Time tSU.DAT 100 ns 9
Data In Hold Time tHD.DAT 0 ns 9
Input Rise Time tR 300 ns Based on characterization, not tested 9
Input Fall Time tF 100 ns Based on characterization, not tested 9
Clock Low to Data Out Valid tAA 50 550 ns 9
Data Out Hold Time tDH 50 ns 9
SMBus Time-Out Delay tTIMEOUT 25 75 ms 9
Time bus must be free before a new transmission can start tBUF 500 ns Based on characterization, not tested 9

CAD (KiCad official)

  • Symbol: ATECC608B-SSHDA-B
  • Footprint: Package_SO:SOIC-8_3.9x4.9mm_P1.27mm
  • 3D model: SOIC-8 (KiCad packages3D, STEP)
  • 3D model files: atecc608b-sshda-b-etched.step / atecc608b-sshda-b-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); atecc608b-sshda-b.step / atecc608b-sshda-b.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: Microchip Tech datasheet (28 pp, sha256 3d4cadb49a93109b, retrieved 2026-10-31, tier: manufacturer)
  • Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-haiku-5-5 (text), consensus claude-sonnet-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF