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ATECC608A-SSHDA-B
Public Made by Adomby adom
Microchip Tech Interface - Specialized, SOIC-8. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.
3D Model
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Symbol & Footprint
Schematic Symbol
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PCB Footprint
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Datasheet
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README
markdownATECC608A-SSHDA-B
Microchip Tech · Interface - Specialized · SOIC-8
ATECC608A-SSHDA-B from Microchip Tech, in a SOIC-8. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.
Pinout
| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | NC | unconnected | No Connect pin; the datasheet lists no function for it. |
| 2 | NC | unconnected | No Connect pin; the datasheet lists no function for it. |
| 3 | NC | unconnected | No Connect pin; the datasheet lists no function for it. |
| 4 | GND | power_in | Ground reference for the device. |
| 5 | SDA | bidirectional | Serial data line of the 1 MHz standard I2C interface, which is used to access the device. |
| 6 | SCL | input | Serial clock input for the 1 MHz standard I2C interface. |
| 7 | NC | unconnected | No Connect pin; the datasheet lists no function for it. |
| 8 | VCC | power_in | Power supply pin; the device supports a 2.0 V to 5.5 V supply voltage with 1.8 V to 5.5 V IO levels. |
Key specifications
| Parameter | Value |
|---|---|
| Manufacturer | Microchip Tech |
| Package | SOIC-8 |
| Category | Communication Interface Chip/UART/485/232 |
| Pins | 8 |
Electrical characteristics
Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).
| Parameter | Symbol | Min | Typ | Max | Unit | Conditions | Page |
|---|---|---|---|---|---|---|---|
| Operating Temperature | -40 | 85 | °C | 6 | |||
| Storage Temperature | -65 | 150 | °C | 6 | |||
| Maximum Operating Voltage | 6 | V | 6 | ||||
| DC Output Current | 5 | mA | 6 | ||||
| Voltage on any pin | -0.5 | V | Printed as -0.5 V to (VCC + 0.5 V); upper limit is VCC-referenced, not a fixed number | 6 | |||
| ESD Human Body Model | 4 | kV | Printed as >4kV (HBM); lower bound only | 6 | |||
| ESD Charge Device Model | 1 | kV | Printed as >1kV (CDM); lower bound only | 6 | |||
| Write Endurance (each byte) | 400000 | Write Cycles | At +85°C | 6 | |||
| Data Retention | 10 | Years | At +55°C | 6 | |||
| Data Retention | 30 | 50 | Years | At +35°C | 6 | ||
| Power-Up Delay | tPU | 100 | µs | Minimum time between VCC > VCC min prior to start of tWLO. | 7 | ||
| Wake Low Duration | tWLO | 60 | µs | 7 | |||
| Wake High Delay to Data Comm | tWHI | 1500 | µs | SDA should be stable high for this entire duration unless polling is implemented. SelfTest is not enabled at power-up. | 7 | ||
| Wake High Delay when SelfTest is Enabled | tWHIST | 20 | ms | SDA should be stable high for this entire duration unless polling is implemented. | 7 | ||
| High Side Glitch Filter at Active | tHIGNORE_A | 45 | ns | Pulses shorter than this in width will be ignored regardless of state when active. Characterized, not production tested. | 7 | ||
| Low Side Glitch Filter at Active | tLIGNORE_A | 45 | ns | Pulses shorter than this in width will be ignored regardless of state when active. Characterized, not production tested. | 7 | ||
| Low Side Glitch Filter at Sleep | tLIGNORE_S | 15 | µs | Pulses shorter than this in width will be ignored when in Sleep mode. Characterized, not production tested. | 7 | ||
| Watchdog Timeout | tWATCHDOG | 0.7 | 1.3 | 1.7 | s | Time from wake until device is forced into Sleep mode if Config.ChipMode.<2> is 0. | 7 |
| Watchdog Timeout | tWATCHDOG | 7.6 | 13 | 17 | s | Watchdog time: Config.ChipMode.<2> is 0 (as printed; see review_required). | 7 |
| Start Pulse Duration (to Crypto Authentication) | tSTART | 4.1 | 4.34 | 4.56 | µs | SWI table: unless otherwise specified TA -40 to +85°C, VCC +2.0 to +5.5V, CL 100 pF | 8 |
| Start Pulse Duration (from Crypto Authentication) | tSTART | 4.6 | 6 | 8.6 | µs | SWI table: unless otherwise specified TA -40 to +85°C, VCC +2.0 to +5.5V, CL 100 pF | 8 |
| Zero Transmission High Pulse (to Crypto Authentication) | tZHI | 4.1 | 4.34 | 4.56 | µs | SWI table: unless otherwise specified TA -40 to +85°C, VCC +2.0 to +5.5V, CL 100 pF | 8 |
| Zero Transmission High Pulse (from Crypto Authentication) | tZHI | 4.6 | 6 | 8.6 | µs | SWI table: unless otherwise specified TA -40 to +85°C, VCC +2.0 to +5.5V, CL 100 pF | 8 |
| Zero Transmission Low Pulse (to Crypto Authentication) | tZLO | 4.1 | 4.34 | 4.56 | µs | SWI table: unless otherwise specified TA -40 to +85°C, VCC +2.0 to +5.5V, CL 100 pF | 8 |
| Zero Transmission Low Pulse (from Crypto Authentication) | tZLO | 4.6 | 6 | 8.6 | µs | SWI table: unless otherwise specified TA -40 to +85°C, VCC +2.0 to +5.5V, CL 100 pF | 8 |
| Bit Time (to Crypto Authentication) | tBIT | 37 | 39 | µs | If the bit time exceeds tTIMEOUT then ATECC608A may enter the Sleep mode. | 8 | |
| Bit Time (from Crypto Authentication) | tBIT | 41 | 54 | 78 | µs | SWI table: unless otherwise specified TA -40 to +85°C, VCC +2.0 to +5.5V, CL 100 pF | 8 |
| Turn Around Delay (from Crypto Authentication) | tTURNAROUND | 64 | 96 | 131 | µs | ATECC608A will initiate the first low going transition after this time interval following the initial falling edge of the start pulse of the last bit of the transmit flag. | 9 |
| Turn Around Delay (to Crypto Authentication) | tTURNAROUND | 93 | µs | After ATECC608A transmits the last bit of a group, system must wait this interval before sending the first bit of a flag. | 9 | ||
| IO Timeout (SWI) | tTIMEOUT | 45 | 65 | 85 | ms | ATECC608A may transition to Sleep mode if the bus is inactive longer than this duration. | 9 |
| SCK Clock Frequency | fSCK | 0 | 1 | MHz | I2C; TA -40 to +85°C, VCC +2.0 to +5.5V, CL 1 TTL gate and 100 pF | 9 | |
| SCK High Time | tHIGH | 400 | ns | 9 | |||
| SCK Low Time | tLOW | 400 | ns | 9 | |||
| Start Setup Time | tSU.STA | 250 | ns | 9 | |||
| Start Hold Time | tHD.STA | 250 | ns | 9 | |||
| Stop Setup Time | tSU.STO | 250 | ns | 10 | |||
| Data In Setup Time | tSU.DAT | 100 | ns | 10 | |||
| Data In Hold Time | tHD.DAT | 0 | ns | 10 | |||
| Input Rise Time | tR | 300 | ns | Printed note 1: values based on characterization and not tested. | 10 | ||
| Input Fall Time | tF | 100 | ns | Printed note 1: values based on characterization and not tested. | 10 | ||
| Clock Low to Data Out Valid | tAA | 50 | 550 | ns | 10 | ||
| Data Out Hold Time | tDH | 50 | ns | 10 | |||
| SMBus Timeout Delay | tTIMEOUT | 25 | 75 | ms | 10 | ||
| Time bus must be free before a new transmission can start | tBUF | 500 | ns | 10 | |||
| Active Power Supply Current | ICC | 2 | 3 | mA | Waiting for I/O during I/O transfers or execution of non-ECC commands. Independent of Clock Divider value. | 10 | |
| Active Power Supply Current during ECC command | ICC | 14 | mA | During ECC command execution. Clock divider = 0x0 | 10 | ||
| Active Power Supply Current during ECC command | ICC | 6 | mA | During ECC command execution. Clock divider = 0x5 | 10 | ||
| Active Power Supply Current during ECC command | ICC | 3 | mA | During ECC command execution. Clock divider = 0xD | 10 | ||
| Sleep Current | ISLEEP | 30 | 150 | nA | When device is in sleep mode, VCC ≤ 3.6V, VSDA and VSCL < 0.4V or > VCC, 0.4, TA ≤ 55°C | 10 | |
| Sleep Current (full VCC and temperature range) | ISLEEP | 2 | µA | When device is in sleep mode. Over full VCC and temperature range. | 10 | ||
| Output Low Voltage | VOL | 0.4 | V | When device is in active mode, VCC = 2.5 to 5.5V | 11 | ||
| Output Low Current | IOL | 4 | mA | When device is in active mode, VCC = 2.5 to 5.5V, VOL = 0.4V | 11 | ||
| Input Low Voltage | VIL | -0.5 | 0.5 | V | When device is active and TTLenable bit in configuration memory is zero; otherwise see Section 2.4.1. | 11 | |
| Input High Voltage | VIH | 1.5 | V | When device is active and TTLenable bit in configuration memory is zero; otherwise see Section 2.4.1. Printed max: VCC + 0.5 V. | 11 | ||
| Ambient Operating Temperature | TA | -40 | 85 | °C | 10 | ||
| Power Supply Voltage | VCC | 2 | 5.5 | V | 10 | ||
| Theta JA (SOIC, SSH package) | ƟJA | 166 | °C/W | SOIC (SSH) | 11 |
CAD (KiCad official)
- Symbol:
ATECC608A-SSHDA-B - Footprint:
Package_SO:SOIC-8_3.9x4.9mm_P1.27mm - 3D model: SOIC-8 (KiCad packages3D, STEP)
- 3D model files:
atecc608a-sshda-b-etched.step/atecc608a-sshda-b-etched.glbcarry the MPN laser-etched on the die in a toggleableAdom.LaserEtchgroup (Fusion-ready);atecc608a-sshda-b.step/atecc608a-sshda-b.glbare the bare package body.
Provenance
Data extracted from the manufacturer datasheet, not a distributor listing:
- Datasheet: Microchip Tech datasheet (28 pp, sha256
93f43a50efe31a35, retrieved 2026-10-19, tier: lcsc) - Extractor: parts-factory
2.0.0/extract_pins 0.3, primaryclaude-haiku-5-5(text), consensusclaude-sonnet-5-5(agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish. - CAD: KiCad official libraries (CC-BY-SA 4.0).