component

ATECC608A-SSHCZ-T

Public Made by Adom

by adom

Microchip Tech Security Verification / Encryption ICs, SOIC-8. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.

componentcommunication interface chip-uart-485-232atecc608a-sshcz-tfactory-2.0.0extractor-text

Verified ATECC608A-SSHCZ-T

by Ray · last 31 Oct 2026 · 1 record · files match
SymbolFootprint3D modelPins

Verification log 1 record

31 Oct 2026RayPublished by the parts factory: tier mfr, 8 pinsfiles match
SymbolFootprint3D modelPinsfor all variants
  • ✓component-page-verify: PASS
  • ✓cad_props: Datasheet, MPN and distributor properties match page.json
  • ✓component: ATECC608A-SSHCZ-T · SOIC-8 · 8 pins
  • ✓copper: 8 copper pads, none touching another net
  • ✓datasheet: all 8 pin names found in the 28-page datasheet
  • ✓distributor: lcsc C2650405, digikey ATECC608A-SSHCZ-TTR-ND, mouser 556-ATECC608ASSHCZT
  • ✓family: SOIC-8_3.9x4.9mm_P1.27mm
  • ✓files: 7 declared files present
  • ✓hero: docs/hero.png 4000x2500
  • ✓lbr: OK: /tmp/cpv-n2d346rs/x.lbr is a valid EAGLE .lbr with complete deviceset
  • ✓license: CC-BY-SA-4.0
  • ✓models_3d: 2 records
  • ✓package_fit: height and body within the datasheet's package drawing (datasheet p.18)
  • ✓pads: 8 pins = 8 pads
  • ✓pose: 2 STEP(s) Z-up, seated, centred
  • ✓symbol: 8 pins agree
  • ✓visibility: public, source open
Evidencedatasheet
Verified files✓ atecc608a-sshcz-t.kicad_sym✓ atecc608a-sshcz-t.kicad_mod✓ atecc608a-sshcz-t.step
Spot something wrong? Report it as an issue Propose a fix Records are signed by members of adom.
Overview Files Discover Packages Releases Dependencies Issues Breadcrumbs Pull Requests Activity
main
Download ZIP Propose a change
Generated by kicad-footprint-generator · KiCad file format 20260206
Name Last commit message Last updated
docs Publish 0.1.0 · Ray 15h ago
viewers atecc608a-sshcz-t: viewers · Ray 15h ago
atecc608a-sshcz-t-etched.glb Publish 0.1.0 · Ray 15h ago
atecc608a-sshcz-t-etched.step atecc608a-sshcz-t: factory component page (tier=mfr) · Ray 15h ago
atecc608a-sshcz-t-hero.glb atecc608a-sshcz-t: hero GLB from the etched model (keeps the MPN mark) · Ray 15h ago
atecc608a-sshcz-t-hero.overlay.json Publish 0.1.0 · Ray 15h ago
atecc608a-sshcz-t.glb Publish 0.1.0 · Ray 15h ago
atecc608a-sshcz-t.kicad_mod Publish 0.1.0 · Ray 15h ago
atecc608a-sshcz-t.kicad_sym Publish 0.1.0 · Ray 15h ago
atecc608a-sshcz-t.lbr Publish 0.1.0 · Ray 15h ago
atecc608a-sshcz-t.step Publish 0.1.0 · Ray 15h ago
package.json Publish 0.1.0 · Ray 15h ago
page.json Set visibility: public · Ray 15h ago
README.md Publish 0.1.0 · Ray 15h ago
verification.json Verified: Published by the parts factory: tier mfr, 8 pins · Ray 15h ago

ATECC608A-SSHCZ-T

Microchip Tech · Security Verification / Encryption ICs · SOIC-8

ATECC608A-SSHCZ-T from Microchip Tech, in a SOIC-8. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 NC unconnected No connect pin on the 8-lead SOIC.
2 NC unconnected No connect pin on the 8-lead SOIC.
3 NC unconnected No connect pin on the 8-lead SOIC.
4 GND power_in Ground.
5 SDA bidirectional Serial data pin; on the single-wire (CZ) variant it is the single-wire interface pin.
6 SCL input Serial clock input; with the single-wire interface enabled the remaining pin is available as a GPIO, authenticated output or tamper input.
7 NC unconnected No connect pin on the 8-lead SOIC.
8 VCC power_in Power supply, 2.0V to 5.5V supply voltage.

Key specifications

Parameter Value
Manufacturer Microchip Tech
Package SOIC-8
Category Communication Interface Chip/UART/485/232
Pins 8

Electrical characteristics

Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).

Parameter Symbol Min Typ Max Unit Conditions Page
Supply Voltage VCC 2 5.5 V 10
Ambient Operating Temperature TA -40 85 °C 10
Operating Temperature (abs max) -40 85 °C 6
Storage Temperature -65 150 °C 6
Maximum Operating Voltage 6 V 6
DC Output Current 5 mA 6
Voltage on any pin -0.5 V -0.5V to (VCC + 0.5V) 6
Active Power Supply Current ICC 2 3 mA Waiting for I/O during I/O transfers or execution of non-ECC commands. Independent of Clock Divider value. 10
Active Supply Current, ECC command ICC 14 mA During ECC command execution. Clock divider = 0x0 10
Active Supply Current, ECC command ICC 6 mA During ECC command execution. Clock divider = 0x5 10
Active Supply Current, ECC command ICC 3 mA During ECC command execution. Clock divider = 0xD 10
Idle Power Supply Current IIDLE 800 µA When device is in idle mode, VSDA and VSCL < 0.4V or > VCC, 0.4 10
Sleep Current ISLEEP 30 150 nA When device is in sleep mode, VCC ≤ 3.6V, VSDA and VSCL < 0.4V or > VCC, 0.4, TA ≤ 55°C 10
Sleep Current, full range ISLEEP 2 µA When device is in sleep mode. Over full VCC and temperature range. 10
Output Low Voltage VOL 0.4 V When device is in active mode, VCC = 2.5 to 5.5V 11
Output Low Current IOL 4 mA When device is in active mode, VCC = 2.5 to 5.5V, VOL = 0.4V 11
Input Low Voltage VIL -0.5 0.5 V When device is active and TTLenable bit in configuration memory is zero 11
Input High Voltage VIH 1.5 V When device is active and TTLenable bit in configuration memory is zero; max VCC + 0.5 11
Theta JA SOIC (SSH) ƟJA 166 °C/W SOIC (SSH) 11
Write Endurance 400000 Write Cycles at +85°C (Each Byte) 6
Data Retention 10 Years at +55°C 6
Data Retention 30 50 Years at +35°C 6
Power-Up Delay tPU 100 µs Minimum time between VCC > VCC min prior to start of tWLO. 7
Wake Low Duration tWLO 60 µs 7
Wake High Delay to Data Comm tWHI 1500 µs SDA should be stable high for this entire duration unless polling is implemented. SelfTest is not enabled at power-up. 7
Wake High Delay when SelfTest is Enabled tWHIST 20 ms SDA should be stable high for this entire duration unless polling is implemented. 7
High Side Glitch Filter at Active tHIGNORE_A 45 ns Pulses shorter than this in width will be ignored by the device, regardless of its state when active. 7
Low Side Glitch Filter at Active tLIGNORE_A 45 ns Pulses shorter than this in width will be ignored by the device, regardless of its state when active. 7
Low Side Glitch Filter at Sleep tLIGNORE_S 15 µs Pulses shorter than this in width will be ignored by the device when in Sleep mode. 7
Watchdog Timeout tWATCHDOG 0.7 1.3 1.7 s Time from wake until device is forced into Sleep mode if Config.ChipMode.<2> is 0. 7
Watchdog Timeout tWATCHDOG 7.6 13 17 s Watchdog time : Config.ChipMode.<2> is 0. 7
SWI Start Pulse Duration, to device tSTART 4.1 4.34 4.56 µs TA = -40°C to +85°C, VCC = +2.0V to +5.5V, CL = 100 pF 8
SWI Start Pulse Duration, from device tSTART 4.6 6 8.6 µs TA = -40°C to +85°C, VCC = +2.0V to +5.5V, CL = 100 pF 8
SWI Zero Transmission High Pulse, to device tZHI 4.1 4.34 4.56 µs TA = -40°C to +85°C, VCC = +2.0V to +5.5V, CL = 100 pF 8
SWI Zero Transmission High Pulse, from device tZHI 4.6 6 8.6 µs TA = -40°C to +85°C, VCC = +2.0V to +5.5V, CL = 100 pF 8
SWI Zero Transmission Low Pulse, to device tZLO 4.1 4.34 4.56 µs TA = -40°C to +85°C, VCC = +2.0V to +5.5V, CL = 100 pF 8
SWI Zero Transmission Low Pulse, from device tZLO 4.6 6 8.6 µs TA = -40°C to +85°C, VCC = +2.0V to +5.5V, CL = 100 pF 8
SWI Bit Time, to device tBIT 37 39 µs If the bit time exceeds tTIMEOUT then ATECC608A may enter the Sleep mode. 8
SWI Bit Time, from device tBIT 41 54 78 µs 8
Turn Around Delay, from device tTURNAROUND 64 96 131 µs ATECC608A will initiate the first low going transition after this time interval following the initial falling edge of the start pulse of the last bit of the transmit flag. 9
Turn Around Delay, to device tTURNAROUND 93 µs After ATECC608A transmits the last bit of a group, system must wait this interval before sending the first bit of a flag. 9
IO Timeout tTIMEOUT 45 65 85 ms ATECC608A may transition to the Sleep mode if the bus is inactive longer than this duration. 9
SCK Clock Frequency fSCK 0 1 MHz TA = -40°C to + 85°C, VCC = +2.0V to +5.5V, CL = 1 TTL Gate and 100 pF 9
SCK High Time tHIGH 400 ns 9
SCK Low Time tLOW 400 ns 9
Start Setup Time tSU.STA 250 ns 9
Start Hold Time tHD.STA 250 ns 9
Stop Setup Time tSU.STO 250 ns 10
Data In Setup Time tSU.DAT 100 ns 10
Data In Hold Time tHD.DAT 0 ns 10
Input Rise Time tR 300 ns 10
Input Fall Time tF 100 ns 10
Clock Low to Data Out Valid tAA 50 550 ns 10
Data Out Hold Time tDH 50 ns 10
SMBus Timeout Delay tTIMEOUT 25 75 ms 10
Bus Free Time tBUF 500 ns Time bus must be free before a new transmission can start 10

CAD (KiCad official)

  • Symbol: ATECC608A-SSHCZ-T
  • Footprint: Package_SO:SOIC-8_3.9x4.9mm_P1.27mm
  • 3D model: SOIC-8 (KiCad packages3D, STEP)
  • 3D model files: atecc608a-sshcz-t-etched.step / atecc608a-sshcz-t-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); atecc608a-sshcz-t.step / atecc608a-sshcz-t.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: Microchip Tech datasheet (28 pp, sha256 5b9164c658d321e3, retrieved 2026-10-31, tier: manufacturer)
  • Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-sonnet-5-5 (text), consensus claude-sonnet-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF