component
ATECC608A-SSHCZ-B
Public Made by Adomby adom
Microchip Tech Pre-ordered MCUs, SOIC-8. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.
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ATECC608A-SSHCZ-B
Microchip Tech · Pre-ordered MCUs · SOIC-8
ATECC608A-SSHCZ-B from Microchip Tech, in a SOIC-8. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.
Pinout
| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | NC | unconnected | No connect pin. |
| 2 | NC | unconnected | No connect pin. |
| 3 | NC | unconnected | No connect pin. |
| 4 | GND | power_in | Ground. |
| 5 | SDA | bidirectional | Serial data pin, used as the high-speed single-wire interface on the CZ (Single Wire Interface) variant, with IO levels of 1.8V to 5.5V. |
| 6 | SCL | input | Serial clock input per the pin table; when the Single-Wire Interface is enabled the remaining pin is available as a GPIO, authenticated output or tamper input. |
| 7 | NC | unconnected | No connect pin. |
| 8 | VCC | power_in | Power supply, 2.0V to 5.5V supply voltage range. |
Key specifications
| Parameter | Value |
|---|---|
| Manufacturer | Microchip Tech |
| Package | SOIC-8 |
| Category | Single Chip Microcomputer/Microcontroller |
| Pins | 8 |
Electrical characteristics
Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).
| Parameter | Symbol | Min | Typ | Max | Unit | Conditions | Page |
|---|---|---|---|---|---|---|---|
| Operating Temperature (absolute maximum) | -40 | 85 | °C | 6 | |||
| Storage Temperature | -65 | 150 | °C | 6 | |||
| Maximum Operating Voltage | 6 | V | 6 | ||||
| DC Output Current | 5 | mA | 6 | ||||
| Voltage on any pin | -0.5 | 6 | V | -0.5V to (VCC + 0.5V); max printed as VCC + 0.5V | 6 | ||
| ESD HBM | 4 | kV | Human Body Model, >4kV | 6 | |||
| ESD CDM | 1 | kV | Charge Device Model, >1kV | 6 | |||
| Ambient Operating Temperature | TA | -40 | 85 | °C | 10 | ||
| Power Supply Voltage | VCC | 2 | 5.5 | V | 10 | ||
| Active Power Supply Current | ICC | 2 | 3 | mA | Waiting for I/O during I/O transfers or execution of non-ECC commands. Independent of Clock Divider value. | 10 | |
| Active Power Supply Current (ECC, divider 0x0) | ICC | 14 | mA | During ECC command execution. Clock divider = 0x0 | 10 | ||
| Active Power Supply Current (ECC, divider 0x5) | ICC | 6 | mA | During ECC command execution. Clock divider = 0x5 | 10 | ||
| Active Power Supply Current (ECC, divider 0xD) | ICC | 3 | mA | During ECC command execution. Clock divider = 0xD | 10 | ||
| Sleep Current | ISLEEP | 30 | 150 | nA | Sleep mode, VCC ≤ 3.6V, VSDA and VSCL < 0.4V or > VCC, 0.4, TA ≤ 55°C | 10 | |
| Sleep Current (full range) | ISLEEP | 2 | µA | When device is in sleep mode. Over full VCC and temperature range. | 10 | ||
| Output Low Voltage | VOL | 0.4 | V | When device is in active mode, VCC = 2.5 to 5.5V | 11 | ||
| Output Low Current | IOL | 4 | mA | When device is in active mode, VCC = 2.5 to 5.5V, VOL = 0.4V | 11 | ||
| Input Low Voltage | VIL | -0.5 | 0.5 | V | When device is active and TTLenable bit in configuration memory is zero | 11 | |
| Input High Voltage | VIH | 1.5 | 5.5 | V | When device is active and TTLenable bit in configuration memory is zero; max printed as VCC + 0.5 | 11 | |
| Idle Power Supply Current | IIDLE | 800 | µA | Idle mode, VSDA and VSCL < 0.4V or > VCC, 0.4 | 10 | ||
| Theta JA SOIC (SSH) | ƟJA | 166 | °C/W | SOIC (SSH) | 11 | ||
| Power-Up Delay | tPU | 100 | µs | Minimum time between VCC > VCC min prior to start of tWLO. | 7 | ||
| Wake Low Duration | tWLO | 60 | µs | 7 | |||
| Wake High Delay to Data Comm | tWHI | 1500 | µs | SDA should be stable high for this entire duration unless polling is implemented. SelfTest is not enabled at power-up. | 7 | ||
| Wake High Delay when SelfTest is Enabled | tWHIST | 20 | ms | SDA should be stable high for this entire duration unless polling is implemented. | 7 | ||
| High Side Glitch Filter at Active | tHIGNORE_A | 45 | ns | Pulses shorter than this in width will be ignored, regardless of state when active. | 7 | ||
| Low Side Glitch Filter at Active | tLIGNORE_A | 45 | ns | Pulses shorter than this in width will be ignored, regardless of state when active. | 7 | ||
| Low Side Glitch Filter at Sleep | tLIGNORE_S | 15 | µs | Pulses shorter than this in width will be ignored when in Sleep mode. | 7 | ||
| Watchdog Timeout | tWATCHDOG | 0.7 | 1.3 | 1.7 | s | Time from wake until device is forced into Sleep mode if Config.ChipMode.<2> is 0. | 7 |
| Watchdog Timeout (second row) | tWATCHDOG | 7.6 | 13 | 17 | s | Watchdog time : Config.ChipMode.<2> is 0. | 7 |
| SWI Start Pulse Duration (to device) | tSTART | 4.1 | 4.34 | 4.56 | µs | TA = -40°C to +85°C, VCC = +2.0V to +5.5V, CL = 100 pF; To Crypto Authentication | 8 |
| SWI Start Pulse Duration (from device) | tSTART | 4.6 | 6 | 8.6 | µs | From Crypto Authentication | 8 |
| SWI Zero Transmission High Pulse (to device) | tZHI | 4.1 | 4.34 | 4.56 | µs | To Crypto Authentication | 8 |
| SWI Zero Transmission High Pulse (from device) | tZHI | 4.6 | 6 | 8.6 | µs | From Crypto Authentication | 8 |
| SWI Zero Transmission Low Pulse (to device) | tZLO | 4.1 | 4.34 | 4.56 | µs | To Crypto Authentication | 8 |
| SWI Zero Transmission Low Pulse (from device) | tZLO | 4.6 | 6 | 8.6 | µs | From Crypto Authentication | 8 |
| SWI Bit Time (to device) | tBIT | 37 | 39 | µs | If the bit time exceeds tTIMEOUT then device may enter Sleep mode. | 8 | |
| SWI Bit Time (from device) | tBIT | 41 | 54 | 78 | µs | From Crypto Authentication | 8 |
| SWI Turn Around Delay (from device) | tTURNAROUND | 64 | 96 | 131 | µs | Device initiates first low going transition after this interval following initial falling edge of start pulse of last bit of transmit flag. | 9 |
| SWI Turn Around Delay (to device) | tTURNAROUND | 93 | µs | After device transmits last bit of a group, system must wait this interval before sending first bit of a flag. | 9 | ||
| SWI IO Timeout | tTIMEOUT | 45 | 65 | 85 | ms | Device may transition to Sleep mode if the bus is inactive longer than this duration. | 9 |
| I2C SCK Clock Frequency | fSCK | 0 | 1 | MHz | TA = -40°C to +85°C, VCC = +2.0V to +5.5V, CL = 1 TTL Gate and 100 pF | 9 | |
| I2C SCK High Time | tHIGH | 400 | ns | 9 | |||
| I2C SCK Low Time | tLOW | 400 | ns | 9 | |||
| I2C Start Setup Time | tSU.STA | 250 | ns | 9 | |||
| I2C Start Hold Time | tHD.STA | 250 | ns | 9 | |||
| I2C Stop Setup Time | tSU.STO | 250 | ns | 10 | |||
| I2C Data In Setup Time | tSU.DAT | 100 | ns | 10 | |||
| I2C Data In Hold Time | tHD.DAT | 0 | ns | 10 | |||
| I2C Input Rise Time | tR | 300 | ns | Values based on characterization, not tested | 10 | ||
| I2C Input Fall Time | tF | 100 | ns | Values based on characterization, not tested | 10 | ||
| I2C Clock Low to Data Out Valid | tAA | 50 | 550 | ns | 10 | ||
| I2C Data Out Hold Time | tDH | 50 | ns | 10 | |||
| I2C SMBus Timeout Delay | tTIMEOUT | 25 | 75 | ms | 10 | ||
| I2C Bus Free Time | tBUF | 500 | ns | Time bus must be free before a new transmission can start; based on characterization | 10 | ||
| Write Endurance at +85°C (Each Byte) | 400000 | Write Cycles | 6 | ||||
| Data Retention at +55°C | 10 | Years | 6 | ||||
| Data Retention at +35°C | 30 | 50 | Years | 6 |
CAD (KiCad official)
- Symbol:
ATECC608A-SSHCZ-B - Footprint:
Package_SO:SOIC-8_3.9x4.9mm_P1.27mm - 3D model: SOIC-8 (KiCad packages3D, STEP)
- 3D model files:
atecc608a-sshcz-b-etched.step/atecc608a-sshcz-b-etched.glbcarry the MPN laser-etched on the die in a toggleableAdom.LaserEtchgroup (Fusion-ready);atecc608a-sshcz-b.step/atecc608a-sshcz-b.glbare the bare package body.
Provenance
Data extracted from the manufacturer datasheet, not a distributor listing:
- Datasheet: Microchip Tech datasheet (28 pp, sha256
5b9164c658d321e3, retrieved 2026-10-30, tier: manufacturer) - Extractor: parts-factory
2.0.0/extract_pins 0.3, primaryclaude-sonnet-5-5(text), consensusclaude-sonnet-5-5(agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish. - CAD: KiCad official libraries (CC-BY-SA 4.0).
# ATECC608A-SSHCZ-B
**Microchip Tech** · Pre-ordered MCUs · SOIC-8
ATECC608A-SSHCZ-B from Microchip Tech, in a SOIC-8. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.
## Pinout
| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | NC | unconnected | No connect pin. |
| 2 | NC | unconnected | No connect pin. |
| 3 | NC | unconnected | No connect pin. |
| 4 | GND | power_in | Ground. |
| 5 | SDA | bidirectional | Serial data pin, used as the high-speed single-wire interface on the CZ (Single Wire Interface) variant, with IO levels of 1.8V to 5.5V. |
| 6 | SCL | input | Serial clock input per the pin table; when the Single-Wire Interface is enabled the remaining pin is available as a GPIO, authenticated output or tamper input. |
| 7 | NC | unconnected | No connect pin. |
| 8 | VCC | power_in | Power supply, 2.0V to 5.5V supply voltage range. |
## Key specifications
| Parameter | Value |
|---|---|
| Manufacturer | Microchip Tech |
| Package | SOIC-8 |
| Category | Single Chip Microcomputer/Microcontroller |
| Pins | 8 |
## Electrical characteristics
Limits as printed in the datasheet (page.json `metadata.characteristics` carries them as data).
| Parameter | Symbol | Min | Typ | Max | Unit | Conditions | Page |
|---|---|---|---|---|---|---|---|
| Operating Temperature (absolute maximum) | | -40 | | 85 | °C | | 6 |
| Storage Temperature | | -65 | | 150 | °C | | 6 |
| Maximum Operating Voltage | | | | 6 | V | | 6 |
| DC Output Current | | | | 5 | mA | | 6 |
| Voltage on any pin | | -0.5 | | 6 | V | -0.5V to (VCC + 0.5V); max printed as VCC + 0.5V | 6 |
| ESD HBM | | 4 | | | kV | Human Body Model, >4kV | 6 |
| ESD CDM | | 1 | | | kV | Charge Device Model, >1kV | 6 |
| Ambient Operating Temperature | TA | -40 | | 85 | °C | | 10 |
| Power Supply Voltage | VCC | 2 | | 5.5 | V | | 10 |
| Active Power Supply Current | ICC | | 2 | 3 | mA | Waiting for I/O during I/O transfers or execution of non-ECC commands. Independent of Clock Divider value. | 10 |
| Active Power Supply Current (ECC, divider 0x0) | ICC | | | 14 | mA | During ECC command execution. Clock divider = 0x0 | 10 |
| Active Power Supply Current (ECC, divider 0x5) | ICC | | | 6 | mA | During ECC command execution. Clock divider = 0x5 | 10 |
| Active Power Supply Current (ECC, divider 0xD) | ICC | | | 3 | mA | During ECC command execution. Clock divider = 0xD | 10 |
| Sleep Current | ISLEEP | | 30 | 150 | nA | Sleep mode, VCC ≤ 3.6V, VSDA and VSCL < 0.4V or > VCC, 0.4, TA ≤ 55°C | 10 |
| Sleep Current (full range) | ISLEEP | | | 2 | µA | When device is in sleep mode. Over full VCC and temperature range. | 10 |
| Output Low Voltage | VOL | | | 0.4 | V | When device is in active mode, VCC = 2.5 to 5.5V | 11 |
| Output Low Current | IOL | | | 4 | mA | When device is in active mode, VCC = 2.5 to 5.5V, VOL = 0.4V | 11 |
| Input Low Voltage | VIL | -0.5 | | 0.5 | V | When device is active and TTLenable bit in configuration memory is zero | 11 |
| Input High Voltage | VIH | 1.5 | | 5.5 | V | When device is active and TTLenable bit in configuration memory is zero; max printed as VCC + 0.5 | 11 |
| Idle Power Supply Current | IIDLE | | 800 | | µA | Idle mode, VSDA and VSCL < 0.4V or > VCC, 0.4 | 10 |
| Theta JA SOIC (SSH) | ƟJA | | 166 | | °C/W | SOIC (SSH) | 11 |
| Power-Up Delay | tPU | 100 | | | µs | Minimum time between VCC > VCC min prior to start of tWLO. | 7 |
| Wake Low Duration | tWLO | 60 | | | µs | | 7 |
| Wake High Delay to Data Comm | tWHI | 1500 | | | µs | SDA should be stable high for this entire duration unless polling is implemented. SelfTest is not enabled at power-up. | 7 |
| Wake High Delay when SelfTest is Enabled | tWHIST | 20 | | | ms | SDA should be stable high for this entire duration unless polling is implemented. | 7 |
| High Side Glitch Filter at Active | tHIGNORE_A | 45 | | | ns | Pulses shorter than this in width will be ignored, regardless of state when active. | 7 |
| Low Side Glitch Filter at Active | tLIGNORE_A | 45 | | | ns | Pulses shorter than this in width will be ignored, regardless of state when active. | 7 |
| Low Side Glitch Filter at Sleep | tLIGNORE_S | 15 | | | µs | Pulses shorter than this in width will be ignored when in Sleep mode. | 7 |
| Watchdog Timeout | tWATCHDOG | 0.7 | 1.3 | 1.7 | s | Time from wake until device is forced into Sleep mode if Config.ChipMode.<2> is 0. | 7 |
| Watchdog Timeout (second row) | tWATCHDOG | 7.6 | 13 | 17 | s | Watchdog time : Config.ChipMode.<2> is 0. | 7 |
| SWI Start Pulse Duration (to device) | tSTART | 4.1 | 4.34 | 4.56 | µs | TA = -40°C to +85°C, VCC = +2.0V to +5.5V, CL = 100 pF; To Crypto Authentication | 8 |
| SWI Start Pulse Duration (from device) | tSTART | 4.6 | 6 | 8.6 | µs | From Crypto Authentication | 8 |
| SWI Zero Transmission High Pulse (to device) | tZHI | 4.1 | 4.34 | 4.56 | µs | To Crypto Authentication | 8 |
| SWI Zero Transmission High Pulse (from device) | tZHI | 4.6 | 6 | 8.6 | µs | From Crypto Authentication | 8 |
| SWI Zero Transmission Low Pulse (to device) | tZLO | 4.1 | 4.34 | 4.56 | µs | To Crypto Authentication | 8 |
| SWI Zero Transmission Low Pulse (from device) | tZLO | 4.6 | 6 | 8.6 | µs | From Crypto Authentication | 8 |
| SWI Bit Time (to device) | tBIT | 37 | 39 | | µs | If the bit time exceeds tTIMEOUT then device may enter Sleep mode. | 8 |
| SWI Bit Time (from device) | tBIT | 41 | 54 | 78 | µs | From Crypto Authentication | 8 |
| SWI Turn Around Delay (from device) | tTURNAROUND | 64 | 96 | 131 | µs | Device initiates first low going transition after this interval following initial falling edge of start pulse of last bit of transmit flag. | 9 |
| SWI Turn Around Delay (to device) | tTURNAROUND | 93 | | | µs | After device transmits last bit of a group, system must wait this interval before sending first bit of a flag. | 9 |
| SWI IO Timeout | tTIMEOUT | 45 | 65 | 85 | ms | Device may transition to Sleep mode if the bus is inactive longer than this duration. | 9 |
| I2C SCK Clock Frequency | fSCK | 0 | | 1 | MHz | TA = -40°C to +85°C, VCC = +2.0V to +5.5V, CL = 1 TTL Gate and 100 pF | 9 |
| I2C SCK High Time | tHIGH | 400 | | | ns | | 9 |
| I2C SCK Low Time | tLOW | 400 | | | ns | | 9 |
| I2C Start Setup Time | tSU.STA | 250 | | | ns | | 9 |
| I2C Start Hold Time | tHD.STA | 250 | | | ns | | 9 |
| I2C Stop Setup Time | tSU.STO | 250 | | | ns | | 10 |
| I2C Data In Setup Time | tSU.DAT | 100 | | | ns | | 10 |
| I2C Data In Hold Time | tHD.DAT | 0 | | | ns | | 10 |
| I2C Input Rise Time | tR | | | 300 | ns | Values based on characterization, not tested | 10 |
| I2C Input Fall Time | tF | | | 100 | ns | Values based on characterization, not tested | 10 |
| I2C Clock Low to Data Out Valid | tAA | 50 | | 550 | ns | | 10 |
| I2C Data Out Hold Time | tDH | 50 | | | ns | | 10 |
| I2C SMBus Timeout Delay | tTIMEOUT | 25 | | 75 | ms | | 10 |
| I2C Bus Free Time | tBUF | 500 | | | ns | Time bus must be free before a new transmission can start; based on characterization | 10 |
| Write Endurance at +85°C (Each Byte) | | 400000 | | | Write Cycles | | 6 |
| Data Retention at +55°C | | 10 | | | Years | | 6 |
| Data Retention at +35°C | | 30 | 50 | | Years | | 6 |
## CAD (KiCad official)
- Symbol: `ATECC608A-SSHCZ-B`
- Footprint: `Package_SO:SOIC-8_3.9x4.9mm_P1.27mm`
- 3D model: SOIC-8 (KiCad packages3D, STEP)
- 3D model files: `atecc608a-sshcz-b-etched.step` / `atecc608a-sshcz-b-etched.glb` carry the MPN laser-etched on the die in a toggleable `Adom.LaserEtch` group (Fusion-ready); `atecc608a-sshcz-b.step` / `atecc608a-sshcz-b.glb` are the bare package body.
## Provenance
Data extracted from the manufacturer datasheet, not a distributor listing:
- **Datasheet:** [Microchip Tech datasheet](docs/atecc608a-sshcz-b-datasheet.pdf) (28 pp, sha256 `5b9164c658d321e3`, retrieved 2026-10-30, tier: manufacturer)
- **Extractor:** parts-factory `2.0.0` / `extract_pins 0.3`, primary `claude-sonnet-5-5` (text), consensus `claude-sonnet-5-5` (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
- **CAD:** KiCad official libraries (CC-BY-SA 4.0).
[Datasheet PDF](docs/atecc608a-sshcz-b-datasheet.pdf)