component
ATECC108A-SSHDA-T
Public Made by Adomby adom
Microchip Tech Security Verification / Encryption ICs, SOIC-8. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.
Generated by kicad-footprint-generator · KiCad file format 20260206
| Name | Last updated |
|---|---|
| docs | 20h ago |
| viewers | 20h ago |
| atecc108a-sshda-t-etched.glb | 20h ago |
| atecc108a-sshda-t-etched.step | 20h ago |
| atecc108a-sshda-t-hero.glb | 20h ago |
| atecc108a-sshda-t-hero.overlay.json | 20h ago |
| atecc108a-sshda-t.glb | 20h ago |
| atecc108a-sshda-t.kicad_mod | 20h ago |
| atecc108a-sshda-t.kicad_sym | 20h ago |
| atecc108a-sshda-t.lbr | 20h ago |
| atecc108a-sshda-t.step | 20h ago |
| package.json | 20h ago |
| page.json | 20h ago |
| README.md | 20h ago |
| verification.json | 20h ago |
ATECC108A-SSHDA-T
Microchip Tech · Security Verification / Encryption ICs · SOIC-8
ATECC108A-SSHDA-T from Microchip Tech, in a SOIC-8. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.
Pinout
| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | NC | unconnected | No connect pin with no internal function stated in the datasheet. |
| 2 | NC | unconnected | No connect pin with no internal function stated in the datasheet. |
| 3 | NC | unconnected | No connect pin with no internal function stated in the datasheet. |
| 4 | GND | power_in | Ground reference for the device. |
| 5 | SDA | bidirectional | Serial data pin for the I2C interface (up to 1MHz), with a pull-up resistor to VCC (RL 1.2k in the AC measurement conditions). |
| 6 | SCL | input | Serial clock input for the I2C interface, with a clock frequency of up to 1MHz. |
| 7 | NC | unconnected | No connect pin with no internal function stated in the datasheet. |
| 8 | VCC | power_in | Power supply input, 2.0V to 5.5V operating range. |
Key specifications
| Parameter | Value |
|---|---|
| Manufacturer | Microchip Tech |
| Package | SOIC-8 |
| Category | Communication Interface Chip/UART/485/232 |
| Pins | 8 |
Electrical characteristics
Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).
| Parameter | Symbol | Min | Typ | Max | Unit | Conditions | Page |
|---|---|---|---|---|---|---|---|
| Operating Temperature | -40 | 85 | °C | 5 | |||
| Storage Temperature | -65 | 150 | °C | 5 | |||
| Maximum Operating Voltage | 6 | V | 5 | ||||
| DC Output Current | 5 | mA | 5 | ||||
| Voltage on any pin | -0.5 | V | Maximum printed as VCC + 0.5V | 5 | |||
| Ambient Operating Temperature | TA | -40 | 85 | C | 8 | ||
| Power Supply Voltage | VCC | 2 | 5.5 | V | 8 | ||
| Active Power Supply Current | ICC | 3 | 6 | mA | Waiting for I/O during I/O transfers or execution of non-ECC commands when ChipMode:3 is zero. | 8 | |
| Active Power Supply Current during ECC command execution | ICC | 16 | mA | During ECC command execution. | 8 | ||
| Idle Power Supply Current | IIDLE | 800 | µA | When device is in idle mode, VSDA and VSCL < 0.4V or > VCC, 0.4 | 8 | ||
| Sleep Current | ISLEEP | 30 | 150 | nA | When device is in sleep mode, VCC 3.6V, VSDA and VSCL < 0.4V or > VCC, 0.4, TA 55°C | 8 | |
| Sleep Current | ISLEEP | 2 | µA | When device is in sleep mode. | 8 | ||
| Output Low Voltage | VOL | 0.4 | V | When device is in active mode, VCC = 2.5, 5.5V | 8 | ||
| Output Low Current | IOL | 4 | mA | When device is in active mode, VCC = 2.5, 5.5V, VOL = 0.4V | 8 | ||
| Input Low Voltage | VIL | -0.5 | 0.5 | V | When device is active and TTLenable bit in configuration memory is zero. | 8 | |
| Input High Voltage | VIH | 1.5 | V | When device is active and TTLenable bit in configuration memory is zero. Maximum printed as VCC + 0.5 V | 8 | ||
| Power-Up Delay | tPU | 100 | µs | Minimum time between VCC > VCC min prior to measurement of tWLO. | 5 | ||
| Wake Low Duration | tWLO | 60 | µs | To Crypto Authentication | 5 | ||
| Wake High Delay to Data Comm. | tWHI | 500 | µs | SDA should be stable high for this entire duration. | 5 | ||
| High Side Glitch Filter at Active | tHIGNORE_A | 45 | ns | Pulses shorter than this in width will be ignored by the device, regardless of its state when active. Guaranteed through characterization, not tested. | 5 | ||
| Low Side Glitch Filter at Active | tLIGNORE_A | 45 | ns | Pulses shorter than this in width will be ignored by the device, regardless of its state when active. Guaranteed through characterization, not tested. | 5 | ||
| Low Side Glitch Filter at Sleep | tLIGNORE_S | 15 | µs | Pulses shorter than this in width will be ignored by the device when in sleep mode. Guaranteed through characterization, not tested. | 5 | ||
| Watchdog Timeout | tWATCHDOG | 0.7 | 1.3 | 1.7 | s | Maximum time from wake until device is forced into sleep mode. | 5 |
| SCK Clock Frequency | fSCK | 1 | MHz | TA -40 to +85°C, VCC +2.0 to +5.5V, CL 1 TTL Gate and 100pF | 7 | ||
| SCK High Time | tHIGH | 400 | ns | TA -40 to +85°C, VCC +2.0 to +5.5V, CL 1 TTL Gate and 100pF | 7 | ||
| SCK Low Time | tLOW | 400 | ns | TA -40 to +85°C, VCC +2.0 to +5.5V, CL 1 TTL Gate and 100pF | 7 | ||
| Start Setup Time | tSU.STA | 250 | ns | TA -40 to +85°C, VCC +2.0 to +5.5V, CL 1 TTL Gate and 100pF | 7 | ||
| Start Hold Time | tHD.STA | 250 | ns | TA -40 to +85°C, VCC +2.0 to +5.5V, CL 1 TTL Gate and 100pF | 7 | ||
| Stop Setup Time | tSU.STO | 250 | ns | TA -40 to +85°C, VCC +2.0 to +5.5V, CL 1 TTL Gate and 100pF | 7 | ||
| Data In Setup Time | tSU.DAT | 100 | ns | TA -40 to +85°C, VCC +2.0 to +5.5V, CL 1 TTL Gate and 100pF | 7 | ||
| Data In Hold Time | tHD.DAT | 0 | ns | TA -40 to +85°C, VCC +2.0 to +5.5V, CL 1 TTL Gate and 100pF | 7 | ||
| Input Rise Time | tR | 300 | ns | TA -40 to +85°C, VCC +2.0 to +5.5V, CL 1 TTL Gate and 100pF | 7 | ||
| Input Fall Time | tF | 100 | ns | TA -40 to +85°C, VCC +2.0 to +5.5V, CL 1 TTL Gate and 100pF | 7 | ||
| Clock Low to Data Out Valid | tAA | 50 | 550 | ns | TA -40 to +85°C, VCC +2.0 to +5.5V, CL 1 TTL Gate and 100pF | 7 | |
| Data Out Hold Time | tDH | 50 | ns | TA -40 to +85°C, VCC +2.0 to +5.5V, CL 1 TTL Gate and 100pF | 7 | ||
| SMBus Timeout Delay | tTIMEOUT | 25 | 75 | ms | TA -40 to +85°C, VCC +2.0 to +5.5V, CL 1 TTL Gate and 100pF | 7 | |
| Bus free time before a new transmission | tBUF | 500 | ns | TA -40 to +85°C, VCC +2.0 to +5.5V, CL 1 TTL Gate and 100pF | 7 | ||
| Write Endurance (Each Byte) | 400000 | Write Cycles | 5 | ||||
| Data Retention (At 55C) | 10 | Years | 5 | ||||
| Data Retention (At 35C) | 30 | 50 | Years | 5 | |||
| Thermal resistance junction-to-ambient, SOIC (SSH) | ƟJA | 166 | C/W | SOIC (SSH) | 8 |
CAD (KiCad official)
- Symbol:
ATECC108A-SSHDA-T - Footprint:
Package_SO:SOIC-8_3.9x4.9mm_P1.27mm - 3D model: SOIC-8 (KiCad packages3D, STEP)
- 3D model files:
atecc108a-sshda-t-etched.step/atecc108a-sshda-t-etched.glbcarry the MPN laser-etched on the die in a toggleableAdom.LaserEtchgroup (Fusion-ready);atecc108a-sshda-t.step/atecc108a-sshda-t.glbare the bare package body.
Provenance
Data extracted from the manufacturer datasheet, not a distributor listing:
- Datasheet: Microchip Tech datasheet (14 pp, sha256
b6c9ad37653156e2, retrieved 2026-10-30, tier: manufacturer) - Extractor: parts-factory
2.0.0/extract_pins 0.3, primaryclaude-sonnet-5-5(text+vision), consensusclaude-opus-5-5(agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish. - CAD: KiCad official libraries (CC-BY-SA 4.0).