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ATA6836C-TIQW
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Microchip Tech Gate Drivers, SOP-28. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.
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ATA6836C-TIQW
Microchip Tech · Gate Drivers · SOP-28
ATA6836C-TIQW from Microchip Tech, in a SOP-28. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.
Pinout
| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | OUT5 | output | Half-bridge output 5, formed by high-side switch 5 and low-side switch 5 with internal reverse diodes, with short circuit and overtemperature protection and open/short load diagnosis. |
| 2 | OUT5 | output | Half-bridge output 5 (parallel to pin 1), formed by high-side switch 5 and low-side switch 5 with internal reverse diodes, with short circuit and overtemperature protection and open/short load diagnosis. |
| 3 | OUT4 | output | Half-bridge output 4, formed by high-side switch 4 and low-side switch 4 with internal reverse diodes, with short circuit and overtemperature protection and open/short load diagnosis. |
| 4 | OUT4 | output | Half-bridge output 4 (parallel to pin 3), formed by high-side switch 4 and low-side switch 4 with internal reverse diodes, with short circuit and overtemperature protection and open/short load diagnosis. |
| 5 | VS | power_in | Power supply for output stages HS4, HS5 and HS6 and internal supply; external connection to pin 10 is necessary. |
| 6 | GND | power_in | Ground and reference potential, internally connected to pins 20 to 23 and serving as cooling tab. |
| 7 | GND | power_in | Ground and reference potential, internally connected to pins 20 to 23 and serving as cooling tab. |
| 8 | GND | power_in | Ground and reference potential, internally connected to pins 20 to 23 and serving as cooling tab. |
| 9 | GND | power_in | Ground and reference potential, internally connected to pins 20 to 23 and serving as cooling tab. |
| 10 | VS | power_in | Power supply for output stages HS1, HS2 and HS3; external connection to pin 5 is necessary. |
| 11 | OUT3 | output | Half-bridge output 3, formed by high-side switch 3 and low-side switch 3 with internal reverse diodes, with short circuit and overtemperature protection and open/short load diagnosis. |
| 12 | OUT3 | output | Half-bridge output 3 (parallel to pin 11), formed by high-side switch 3 and low-side switch 3 with internal reverse diodes, with short circuit and overtemperature protection and open/short load diagnosis. |
| 13 | OUT2 | output | Half-bridge output 2, formed by high-side switch 2 and low-side switch 2 with internal reverse diodes, with short circuit and overtemperature protection and open/short load diagnosis. |
| 14 | OUT2 | output | Half-bridge output 2 (parallel to pin 13), formed by high-side switch 2 and low-side switch 2 with internal reverse diodes, with short circuit and overtemperature protection and open/short load diagnosis. |
| 15 | OUT1 | output | Half-bridge output 1, formed by high-side switch 1 and low-side switch 1 with internal reverse diodes, with short circuit and overtemperature protection and open/short load diagnosis. |
| 16 | OUT1 | output | Half-bridge output 1 (parallel to pin 15), formed by high-side switch 1 and low-side switch 1 with internal reverse diodes, with short circuit and overtemperature protection and open/short load diagnosis. |
| 17 | INH | input | Inhibit input, 5V logic input with internal pull down; low = standby, high = normal operation. |
| 18 | DO | tri_state | Serial data output, 5V CMOS logic level tri-state output sending 16-bit status information LSB first; it remains tri-stated unless CS is low. |
| 19 | VCC | power_in | Logic supply voltage of 5V (4.75V to 5.25V operating range). |
| 20 | GND | power_in | Ground and reference potential, see pins 6 to 9. |
| 21 | GND | power_in | Ground and reference potential, see pins 6 to 9. |
| 22 | GND | power_in | Ground and reference potential, see pins 6 to 9. |
| 23 | GND | power_in | Ground and reference potential, see pins 6 to 9. |
| 24 | CS | input | Chip select input, 5V CMOS logic level with internal pull up; low = serial communication enabled, high = disabled. |
| 25 | CLK | input | Serial clock input, 5V CMOS logic level with internal pull down, controlling the serial data input interface and shift register with fmax = 2MHz. |
| 26 | DI | input | Serial data input, 5V CMOS logic level with internal pull down, receiving a 16-bit control word with LSB transferred first. |
| 27 | OUT6 | output | Half-bridge output 6, formed by high-side switch 6 and low-side switch 6 with internal reverse diodes, with short circuit and overtemperature protection and open/short load diagnosis. |
| 28 | OUT6 | output | Half-bridge output 6 (parallel to pin 27), formed by high-side switch 6 and low-side switch 6 with internal reverse diodes, with short circuit and overtemperature protection and open/short load diagnosis. |
Key specifications
| Parameter | Value |
|---|---|
| Manufacturer | Microchip Tech |
| Package | SOP-28 |
| Category | Motor Driver ICs |
| Pins | 28 |
Electrical characteristics
Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).
| Parameter | Symbol | Min | Typ | Max | Unit | Conditions | Page |
|---|---|---|---|---|---|---|---|
| Supply voltage | VVS | -0.3 | 40 | V | 10 | ||
| Supply voltage t < 0.5s | VVS | -1 | V | t < 0.5s; IS > -2A | 10 | ||
| Supply voltage difference | VS_pin5(3) - VS_pin10(4) | 150 | mV | 10 | |||
| Logic supply voltage | VVCC | -0.3 | 7 | V | 10 | ||
| Logic input voltage | VDI, VCLK, VCS | -0.3 | V | upper limit VVCC +0.3 V | 10 | ||
| Logic output voltage | VDO | -0.3 | V | upper limit VVCC +0.3 V | 10 | ||
| Input current | IINH, IDI, ICLK, ICS | -10 | 10 | mA | 10 | ||
| Output current | IDO | -10 | 10 | mA | 10 | ||
| Output voltage | OUT1 to OUT6 | -0.3 | 40 | V | 10 | ||
| Junction temperature range | Tj | -40 | 150 | °C | 10 | ||
| Storage temperature range | TSTG | -55 | 150 | °C | 10 | ||
| Supply voltage | VVS | 40 | V | 11 | |||
| Logic supply voltage | VVCC | 4.75 | 5.25 | V | 11 | ||
| Logic input voltage | VINH, VDI, VCLK, VCS | -0.3 | V | upper limit VVCC | 11 | ||
| Serial interface clock frequency | fCLK | 2 | MHz | 11 | |||
| Junction temperature range | Tj | -40 | 150 | °C | 11 | ||
| Total quiescent current (VS and all outputs to VS) | IVS | 2 | µA | VS = 33V; VCC = 0V or VCC = 5V, bit SI = low or VCC = 5V, pin INH = low; output pins to VS and GND | 11 | ||
| Quiescent current (VCC) | IVCC | 20 | µA | 4.75V < VVCC < 5.25V, INH or bit SI = low | 11 | ||
| Supply current (VS) | IVS | 0.8 | 1.2 | mA | VVS < 28V normal operation, all output stages off | 11 | |
| Supply current (VS) | IVS | 10 | mA | VVS < 28V normal operation, all output low stages on, no load | 11 | ||
| Supply current (VS) | IVS | 16 | mA | VVS < 28V normal operation, all output high stages on, no load | 11 | ||
| Supply current (VCC) | IVCC | 150 | µA | 4.75V < VVCC < 5.25V, normal operation | 11 | ||
| Discharge current (VS) | IVS | 5 | mA | VVS = 40V, INH = low | 11 | ||
| Power-on reset threshold | VVCC | 2.3 | 2.7 | 3 | V | 11 | |
| Power-on reset delay time | tdPor | 30 | 95 | 160 | µs | After switching on VVCC | 12 |
| Undervoltage detection threshold | VUV | 5.5 | 7 | V | 12 | ||
| Undervoltage detection delay | tdUV | 7 | 21 | ms | 12 | ||
| Thermal prewarning | TjPWset | 120 | 145 | 170 | °C | 12 | |
| Thermal prewarning reset | TjPWreset | 105 | 130 | 155 | °C | 12 | |
| Thermal shutdown | Tj switch off | 150 | 175 | 200 | °C | 12 | |
| Thermal shutdown | Tj switch on | 135 | 160 | 185 | °C | 12 | |
| On resistance | RDS OnL | 1.8 | Ω | IOut = 600mA | 12 | ||
| High-side output leakage current | IOut1-6 | -15 | µA | VOut1-6 = 0V, all output stages off | 12 | ||
| Low-side output leakage current | IOut1-6 | 120 | µA | VOut1-6 = VS, all output stages off | 12 | ||
| Inductive shutdown energy | Woutx | 15 | mJ | 12 | |||
| Overcurrent limitation and shutdown threshold | ILS1-6 | 650 | 950 | 1400 | mA | VVS = 13V | 12 |
| Overcurrent limitation and shutdown threshold | IHS1-6 | -1400 | -950 | -650 | mA | VVS = 13V | 12 |
| Overcurrent limitation and shutdown threshold | ILS1-6 | 650 | 950 | 1600 | mA | 20V < VVS < 40V | 13 |
| Overcurrent limitation and shutdown threshold | IHS1-6 | -1600 | -950 | -650 | mA | 20V < VVS < 40V | 13 |
| Overcurrent shutdown delay time | tdSd | 0.9 | 1.5 | 2.1 | ms | Input register bit 14 (SCT) = low, VVS = 13V | 13 |
| Overcurrent shutdown delay time | tdSd | 7 | 12 | 17 | ms | Input register bit 14 (SCT) = High, VVS = 13V | 13 |
| High-side open load detection current | IOut1-6H | -1.5 | -0.4 | mA | Input register bit 13 (OLD) = low, output off | 13 | |
| Low-side open load detection current | IOut1-6L | 0.4 | 1.5 | mA | Input register bit 13 (OLD) = low, output off | 13 | |
| Open load detection current ratio | IOLoutLX/IOLoutHX | 1.05 | 1.2 | 2 | 13 | ||
| High-side open load detection voltage | VOut1-6H | -2.5 | -0.6 | V | Input register bit 13 (OLD) = low, output off, reference: VS | 13 | |
| Low-side open load detection voltage | VOut1-6L | 0.6 | 2 | V | Input register bit 13 (OLD) = low, output off | 13 | |
| Input voltage low-level threshold | VIL | 0.3 | VVCC | 13 | |||
| Input voltage high-level threshold | VIH | 0.7 | VVCC | 13 | |||
| Hysteresis of input voltage | VI | 100 | 700 | mV | 13 | ||
| Pull-down current | IPD | 10 | 80 | µA | VINH = VVCC | 13 | |
| Input voltage low-level threshold | VIL | 0.3 | VVCC | 14 | |||
| Input voltage high-level threshold | VIH | 0.7 | VVCC | 14 | |||
| Hysteresis of input voltage | VI | 50 | 500 | mV | 14 | ||
| Pull-down current pin DI, CLK | IPDSI | 2 | 50 | µA | VDI, VCLK = VVCC | 14 | |
| Pull-up current pin CS | IPUSI | -50 | -2 | µA | VCS = 0V | 14 | |
| Output voltage low level | VDOL | 0.5 | V | IOL = 3mA | 14 | ||
| Leakage current (tri-state) | IDO | -10 | 10 | µA | VCS = VVCC, 0V < VDO < VVCC | 14 | |
| Junction pin thermal resistance | RthJP | 25 | K/W | Measured to GND | 10 | ||
| Junction ambient thermal resistance | RthJA | 65 | K/W | 10 |
CAD (KiCad official)
- Symbol:
ATA6836C-TIQW - Footprint:
Package_SO:SOP-28_8.4x18.16mm_P1.27mm - 3D model: SOP-28 (KiCad packages3D, STEP)
- 3D model files:
ata6836c-tiqw-etched.step/ata6836c-tiqw-etched.glbcarry the MPN laser-etched on the die in a toggleableAdom.LaserEtchgroup (Fusion-ready);ata6836c-tiqw.step/ata6836c-tiqw.glbare the bare package body.
Provenance
Data extracted from the manufacturer datasheet, not a distributor listing:
- Datasheet: Microchip Tech datasheet (22 pp, sha256
7666d97608f51a74, retrieved 2026-10-27, tier: manufacturer) - Extractor: parts-factory
2.0.0/extract_pins 0.3, primaryclaude-haiku-5-5(text), consensusoff(skipped (clean text read)), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish. - CAD: KiCad official libraries (CC-BY-SA 4.0).
# ATA6836C-TIQW
**Microchip Tech** · Gate Drivers · SOP-28
ATA6836C-TIQW from Microchip Tech, in a SOP-28. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.
## Pinout
| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | OUT5 | output | Half-bridge output 5, formed by high-side switch 5 and low-side switch 5 with internal reverse diodes, with short circuit and overtemperature protection and open/short load diagnosis. |
| 2 | OUT5 | output | Half-bridge output 5 (parallel to pin 1), formed by high-side switch 5 and low-side switch 5 with internal reverse diodes, with short circuit and overtemperature protection and open/short load diagnosis. |
| 3 | OUT4 | output | Half-bridge output 4, formed by high-side switch 4 and low-side switch 4 with internal reverse diodes, with short circuit and overtemperature protection and open/short load diagnosis. |
| 4 | OUT4 | output | Half-bridge output 4 (parallel to pin 3), formed by high-side switch 4 and low-side switch 4 with internal reverse diodes, with short circuit and overtemperature protection and open/short load diagnosis. |
| 5 | VS | power_in | Power supply for output stages HS4, HS5 and HS6 and internal supply; external connection to pin 10 is necessary. |
| 6 | GND | power_in | Ground and reference potential, internally connected to pins 20 to 23 and serving as cooling tab. |
| 7 | GND | power_in | Ground and reference potential, internally connected to pins 20 to 23 and serving as cooling tab. |
| 8 | GND | power_in | Ground and reference potential, internally connected to pins 20 to 23 and serving as cooling tab. |
| 9 | GND | power_in | Ground and reference potential, internally connected to pins 20 to 23 and serving as cooling tab. |
| 10 | VS | power_in | Power supply for output stages HS1, HS2 and HS3; external connection to pin 5 is necessary. |
| 11 | OUT3 | output | Half-bridge output 3, formed by high-side switch 3 and low-side switch 3 with internal reverse diodes, with short circuit and overtemperature protection and open/short load diagnosis. |
| 12 | OUT3 | output | Half-bridge output 3 (parallel to pin 11), formed by high-side switch 3 and low-side switch 3 with internal reverse diodes, with short circuit and overtemperature protection and open/short load diagnosis. |
| 13 | OUT2 | output | Half-bridge output 2, formed by high-side switch 2 and low-side switch 2 with internal reverse diodes, with short circuit and overtemperature protection and open/short load diagnosis. |
| 14 | OUT2 | output | Half-bridge output 2 (parallel to pin 13), formed by high-side switch 2 and low-side switch 2 with internal reverse diodes, with short circuit and overtemperature protection and open/short load diagnosis. |
| 15 | OUT1 | output | Half-bridge output 1, formed by high-side switch 1 and low-side switch 1 with internal reverse diodes, with short circuit and overtemperature protection and open/short load diagnosis. |
| 16 | OUT1 | output | Half-bridge output 1 (parallel to pin 15), formed by high-side switch 1 and low-side switch 1 with internal reverse diodes, with short circuit and overtemperature protection and open/short load diagnosis. |
| 17 | INH | input | Inhibit input, 5V logic input with internal pull down; low = standby, high = normal operation. |
| 18 | DO | tri_state | Serial data output, 5V CMOS logic level tri-state output sending 16-bit status information LSB first; it remains tri-stated unless CS is low. |
| 19 | VCC | power_in | Logic supply voltage of 5V (4.75V to 5.25V operating range). |
| 20 | GND | power_in | Ground and reference potential, see pins 6 to 9. |
| 21 | GND | power_in | Ground and reference potential, see pins 6 to 9. |
| 22 | GND | power_in | Ground and reference potential, see pins 6 to 9. |
| 23 | GND | power_in | Ground and reference potential, see pins 6 to 9. |
| 24 | CS | input | Chip select input, 5V CMOS logic level with internal pull up; low = serial communication enabled, high = disabled. |
| 25 | CLK | input | Serial clock input, 5V CMOS logic level with internal pull down, controlling the serial data input interface and shift register with fmax = 2MHz. |
| 26 | DI | input | Serial data input, 5V CMOS logic level with internal pull down, receiving a 16-bit control word with LSB transferred first. |
| 27 | OUT6 | output | Half-bridge output 6, formed by high-side switch 6 and low-side switch 6 with internal reverse diodes, with short circuit and overtemperature protection and open/short load diagnosis. |
| 28 | OUT6 | output | Half-bridge output 6 (parallel to pin 27), formed by high-side switch 6 and low-side switch 6 with internal reverse diodes, with short circuit and overtemperature protection and open/short load diagnosis. |
## Key specifications
| Parameter | Value |
|---|---|
| Manufacturer | Microchip Tech |
| Package | SOP-28 |
| Category | Motor Driver ICs |
| Pins | 28 |
## Electrical characteristics
Limits as printed in the datasheet (page.json `metadata.characteristics` carries them as data).
| Parameter | Symbol | Min | Typ | Max | Unit | Conditions | Page |
|---|---|---|---|---|---|---|---|
| Supply voltage | VVS | -0.3 | | 40 | V | | 10 |
| Supply voltage t < 0.5s | VVS | -1 | | | V | t < 0.5s; IS > -2A | 10 |
| Supply voltage difference | VS_pin5(3) - VS_pin10(4) | | | 150 | mV | | 10 |
| Logic supply voltage | VVCC | -0.3 | | 7 | V | | 10 |
| Logic input voltage | VDI, VCLK, VCS | -0.3 | | | V | upper limit VVCC +0.3 V | 10 |
| Logic output voltage | VDO | -0.3 | | | V | upper limit VVCC +0.3 V | 10 |
| Input current | IINH, IDI, ICLK, ICS | -10 | | 10 | mA | | 10 |
| Output current | IDO | -10 | | 10 | mA | | 10 |
| Output voltage | OUT1 to OUT6 | -0.3 | | 40 | V | | 10 |
| Junction temperature range | Tj | -40 | | 150 | °C | | 10 |
| Storage temperature range | TSTG | -55 | | 150 | °C | | 10 |
| Supply voltage | VVS | | | 40 | V | | 11 |
| Logic supply voltage | VVCC | 4.75 | | 5.25 | V | | 11 |
| Logic input voltage | VINH, VDI, VCLK, VCS | -0.3 | | | V | upper limit VVCC | 11 |
| Serial interface clock frequency | fCLK | | | 2 | MHz | | 11 |
| Junction temperature range | Tj | -40 | | 150 | °C | | 11 |
| Total quiescent current (VS and all outputs to VS) | IVS | | | 2 | µA | VS = 33V; VCC = 0V or VCC = 5V, bit SI = low or VCC = 5V, pin INH = low; output pins to VS and GND | 11 |
| Quiescent current (VCC) | IVCC | | | 20 | µA | 4.75V < VVCC < 5.25V, INH or bit SI = low | 11 |
| Supply current (VS) | IVS | | 0.8 | 1.2 | mA | VVS < 28V normal operation, all output stages off | 11 |
| Supply current (VS) | IVS | | | 10 | mA | VVS < 28V normal operation, all output low stages on, no load | 11 |
| Supply current (VS) | IVS | | | 16 | mA | VVS < 28V normal operation, all output high stages on, no load | 11 |
| Supply current (VCC) | IVCC | | | 150 | µA | 4.75V < VVCC < 5.25V, normal operation | 11 |
| Discharge current (VS) | IVS | | | 5 | mA | VVS = 40V, INH = low | 11 |
| Power-on reset threshold | VVCC | 2.3 | 2.7 | 3 | V | | 11 |
| Power-on reset delay time | tdPor | 30 | 95 | 160 | µs | After switching on VVCC | 12 |
| Undervoltage detection threshold | VUV | 5.5 | | 7 | V | | 12 |
| Undervoltage detection delay | tdUV | 7 | | 21 | ms | | 12 |
| Thermal prewarning | TjPWset | 120 | 145 | 170 | °C | | 12 |
| Thermal prewarning reset | TjPWreset | 105 | 130 | 155 | °C | | 12 |
| Thermal shutdown | Tj switch off | 150 | 175 | 200 | °C | | 12 |
| Thermal shutdown | Tj switch on | 135 | 160 | 185 | °C | | 12 |
| On resistance | RDS OnL | | | 1.8 | Ω | IOut = 600mA | 12 |
| High-side output leakage current | IOut1-6 | -15 | | | µA | VOut1-6 = 0V, all output stages off | 12 |
| Low-side output leakage current | IOut1-6 | | | 120 | µA | VOut1-6 = VS, all output stages off | 12 |
| Inductive shutdown energy | Woutx | | | 15 | mJ | | 12 |
| Overcurrent limitation and shutdown threshold | ILS1-6 | 650 | 950 | 1400 | mA | VVS = 13V | 12 |
| Overcurrent limitation and shutdown threshold | IHS1-6 | -1400 | -950 | -650 | mA | VVS = 13V | 12 |
| Overcurrent limitation and shutdown threshold | ILS1-6 | 650 | 950 | 1600 | mA | 20V < VVS < 40V | 13 |
| Overcurrent limitation and shutdown threshold | IHS1-6 | -1600 | -950 | -650 | mA | 20V < VVS < 40V | 13 |
| Overcurrent shutdown delay time | tdSd | 0.9 | 1.5 | 2.1 | ms | Input register bit 14 (SCT) = low, VVS = 13V | 13 |
| Overcurrent shutdown delay time | tdSd | 7 | 12 | 17 | ms | Input register bit 14 (SCT) = High, VVS = 13V | 13 |
| High-side open load detection current | IOut1-6H | -1.5 | | -0.4 | mA | Input register bit 13 (OLD) = low, output off | 13 |
| Low-side open load detection current | IOut1-6L | 0.4 | | 1.5 | mA | Input register bit 13 (OLD) = low, output off | 13 |
| Open load detection current ratio | IOLoutLX/IOLoutHX | 1.05 | 1.2 | 2 | | | 13 |
| High-side open load detection voltage | VOut1-6H | -2.5 | | -0.6 | V | Input register bit 13 (OLD) = low, output off, reference: VS | 13 |
| Low-side open load detection voltage | VOut1-6L | 0.6 | | 2 | V | Input register bit 13 (OLD) = low, output off | 13 |
| Input voltage low-level threshold | VIL | | | 0.3 | VVCC | | 13 |
| Input voltage high-level threshold | VIH | 0.7 | | | VVCC | | 13 |
| Hysteresis of input voltage | VI | 100 | | 700 | mV | | 13 |
| Pull-down current | IPD | 10 | | 80 | µA | VINH = VVCC | 13 |
| Input voltage low-level threshold | VIL | | | 0.3 | VVCC | | 14 |
| Input voltage high-level threshold | VIH | 0.7 | | | VVCC | | 14 |
| Hysteresis of input voltage | VI | 50 | | 500 | mV | | 14 |
| Pull-down current pin DI, CLK | IPDSI | 2 | | 50 | µA | VDI, VCLK = VVCC | 14 |
| Pull-up current pin CS | IPUSI | -50 | | -2 | µA | VCS = 0V | 14 |
| Output voltage low level | VDOL | | | 0.5 | V | IOL = 3mA | 14 |
| Leakage current (tri-state) | IDO | -10 | | 10 | µA | VCS = VVCC, 0V < VDO < VVCC | 14 |
| Junction pin thermal resistance | RthJP | | 25 | | K/W | Measured to GND | 10 |
| Junction ambient thermal resistance | RthJA | | 65 | | K/W | | 10 |
## CAD (KiCad official)
- Symbol: `ATA6836C-TIQW`
- Footprint: `Package_SO:SOP-28_8.4x18.16mm_P1.27mm`
- 3D model: SOP-28 (KiCad packages3D, STEP)
- 3D model files: `ata6836c-tiqw-etched.step` / `ata6836c-tiqw-etched.glb` carry the MPN laser-etched on the die in a toggleable `Adom.LaserEtch` group (Fusion-ready); `ata6836c-tiqw.step` / `ata6836c-tiqw.glb` are the bare package body.
## Provenance
Data extracted from the manufacturer datasheet, not a distributor listing:
- **Datasheet:** [Microchip Tech datasheet](docs/ata6836c-tiqw-datasheet.pdf) (22 pp, sha256 `7666d97608f51a74`, retrieved 2026-10-27, tier: manufacturer)
- **Extractor:** parts-factory `2.0.0` / `extract_pins 0.3`, primary `claude-haiku-5-5` (text), consensus `off` (skipped (clean text read)), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
- **CAD:** KiCad official libraries (CC-BY-SA 4.0).
[Datasheet PDF](docs/ata6836c-tiqw-datasheet.pdf)