component

ATA6625C-GAQW

Public Made by Adom

by adom

Microchip Tech LIN Transceivers, SO-8. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.

componentcommunication interface chip-uart-485-232ata6625c-gaqwfactory-2.0.0extractor-text

Verified ATA6625C-GAQW

by Ray · last 2 Nov 2026 · 1 record · files match
SymbolFootprint3D modelPins

Verification log 1 record

2 Nov 2026RayPublished by the parts factory: tier mfr, 8 pinsfiles match
SymbolFootprint3D modelPinsfor all variants
  • ✓component-page-verify: PASS
  • ✓cad_props: Datasheet, MPN and distributor properties match page.json
  • ✓component: ATA6625C-GAQW · SO-8 · 8 pins
  • ✓copper: 8 copper pads, none touching another net
  • ✓datasheet: all 8 pin names found in the 22-page datasheet
  • •distributor (warn): no ['digikey'] number
  • ✓family: SOIC-8_3.9x4.9mm_P1.27mm
  • ✓files: 7 declared files present
  • ✓hero: docs/hero.png 4000x2500
  • ✓lbr: OK: /tmp/cpv-la1x2n1t/x.lbr is a valid EAGLE .lbr with complete deviceset
  • ✓license: CC-BY-SA-4.0
  • ✓models_3d: 2 records
  • •package_fit (skip): no component.package_dims on the page: the model is unchecked against the datasheet drawing
  • ✓pads: 8 pins = 8 pads
  • ✓pose: 2 STEP(s) Z-up, seated, centred
  • ✓symbol: 8 pins agree
  • ✓visibility: public, source open
Evidencedatasheet
Verified files✓ ata6625c-gaqw.kicad_sym✓ ata6625c-gaqw.kicad_mod✓ ata6625c-gaqw.step
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Generated by kicad-footprint-generator · KiCad file format 20260206
Name Last commit message Last updated
docs Publish 0.1.0 · Ray 2d ago
viewers ata6625c-gaqw: viewers · Ray 2d ago
ata6625c-gaqw-etched.glb Publish 0.1.0 · Ray 2d ago
ata6625c-gaqw-etched.step ata6625c-gaqw: factory component page (tier=mfr) · Ray 2d ago
ata6625c-gaqw-hero.glb ata6625c-gaqw: hero GLB from the etched model (keeps the MPN mark) · Ray 2d ago
ata6625c-gaqw-hero.overlay.json Publish 0.1.0 · Ray 2d ago
ata6625c-gaqw.glb Publish 0.1.0 · Ray 2d ago
ata6625c-gaqw.kicad_mod Publish 0.1.0 · Ray 2d ago
ata6625c-gaqw.kicad_sym Publish 0.1.0 · Ray 2d ago
ata6625c-gaqw.lbr Publish 0.1.0 · Ray 2d ago
ata6625c-gaqw.step Publish 0.1.0 · Ray 2d ago
package.json Publish 0.1.0 · Ray 2d ago
page.json Set visibility: public · Ray 2d ago
README.md Publish 0.1.0 · Ray 2d ago
verification.json Verified: Published by the parts factory: tier mfr, 8 pins · Ray 2d ago

ATA6625C-GAQW

Microchip Tech · LIN Transceivers · SO-8

ATA6625C-GAQW from Microchip Tech, in a SO-8. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 VS power_in Battery supply; LIN operating voltage is VS = 5V to 27V, with transmission disabled if VS falls below 5V.
2 EN input Enables normal mode if the input is high.
3 GND power_in Ground and heat sink; connect to a wide GND plate on the PCB to achieve Rthja of 80K/W.
4 LIN bidirectional LIN bus line input/output; voltage range is -27V to +40V.
5 RXD output Receive data output reporting the LIN bus state; internal pull-up typically 5kΩ to VCC.
6 TXD input Transmit data input; must be pulled to ground to drive the LIN bus low.
7 NRES output Output undervoltage reset, low at reset; reset time tReset is 4ms after VCC reaches its nominal value.
8 VCC power_out Output of voltage regulator 3.3V/5V/85mA.

Key specifications

Parameter Value
Manufacturer Microchip Tech
Package SO-8
Category Communication Interface Chip/UART/485/232
Pins 8

Electrical characteristics

Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).

Parameter Symbol Min Typ Max Unit Conditions Page
Supply voltage VS -0.3 40 V 12
Logic pins (RxD, TxD, EN, NRES) -0.3 5.5 V 12
Output current NRES INRES 2 mA 12
LIN DC voltage -27 40 V 12
VCC DC voltage -0.3 5.5 V 12
ESD pin VS, LIN to GND (IEC 61000-4-2) -6 6 KV ESD according to IBEE LIN EMC test specification 1.0 following IEC 61000-4-2 12
ESD HBM pin VS, LIN to GND -6 6 KV ESD HBM following STM5.1 with 1.5kΩ/100pF 12
HBM ESD -3 3 KV ANSI/ESD-STM5.1, JESD22-A114, AEC-Q100 (002) 12
CDM ESD -750 750 V STM 5.3.1 12
Machine Model ESD -200 200 V AEC-Q100-RevF(003) 12
Junction temperature Tj -40 150 °C 12
Storage temperature Ts -55 150 °C 12
Thermal resistance junction to ambient (free air) Rthja 145 K/W free air 12
Thermal resistance junction to ambient with special heat sink at GND (pin 3) Rthja 80 K/W special heat sink at GND (pin 3) on PCB 12
Thermal shutdown of VCC regulator TVCCoff 150 160 170 °C 12
Thermal shutdown of LIN output TLINoff 150 160 170 °C 12
Nominal DC voltage range VS 5 13.5 27 V 5V < VS < 27V, -40°C < Tj < 150°C 13
Supply current in sleep mode IVSsleep 3 10 14 µA Sleep mode, VLIN > VS, 0.5V, VS < 14V (Tj = 25°C) 13
Supply current in sleep mode IVSsleep 5 11 16 µA Sleep mode, VLIN > VS, 0.5V, VS < 14V (Tj = 125°C) 13
Supply current in silent mode IVSsi 47 57 67 µA Bus recessive, VS < 14V (Tj = 25°C), without load at VCC 13
Supply current in silent mode IVSsi 56 66 76 µA Bus recessive, VS < 14V (Tj = 125°C), without load at VCC 13
Supply current in normal mode, bus recessive IVSrec 0.3 0.8 mA Bus recessive, VS < 14V, without load at VCC 13
Supply current in normal mode, bus dominant IVSdom 50 53 mA Bus dominant, VS < 14V, VCC load current 50mA 13
Supply current in fail-safe mode IVSspeed 200 500 µA Bus recessive, VS < 14V, without load at VCC 13
VS undervoltage threshold VSth 3.7 4.4 5 V 13
Low level output sink current RXD IRXD 1.3 2.5 8 mA Normal mode, VLIN = 0V, VRXD = 0.4V 13
Low level output voltage RXD VRXDL 0.4 V IRXD = 1mA 13
Internal resistor to VCC RXD RRXD 3 5 7 kΩ 13
Low level voltage input TXD VTXDL -0.3 0.8 V 13
High level voltage input TXD VTXDH 2 V upper limit VCC + 0.3V 13
Pull-up resistor TXD RTXD 125 250 400 kΩ VTXD = 0V 13
High level leakage current TXD ITXD -3 3 µA VTXD = VCC 13
Low level voltage input EN VENL -0.3 0.8 V 14
High level voltage input EN VENH 2 V upper limit VCC + 0.3V 14
Pull-down resistor EN REN 50 125 200 kΩ VEN = VCC 14
Low level input current EN IEN -3 3 µA VEN = 0V 14
Low level output voltage NRES VNRESL 0.14 V VS ≥ 5.5V, INRES = 1mA 14
Low level output low NRES VNRESLL 0.14 V 10kΩ to 5V, VCC = 0V 14
Undervoltage reset time tReset 2 4 6 ms VS ≥ 5.5V, CNRES = 20pF 14
Reset debounce time for falling edge tres_f 1.5 10 µs VS ≥ 5.5V, CNRES = 20pF 14
Output voltage VCC (ATA6625C) VCCnor 4.9 5.1 V 5.5V < VS < 18V (0mA to 50mA) 15
Output voltage VCC (ATA6625C, 85mA) VCCnor 4.9 5.1 V 6V < VS < 18V (0mA to 85mA) 15
Output voltage VCC at low VS VCClow 5.1 V 4V < VS < 5.5V 15
Regulator drop voltage VD1 250 mV VS > 4V, IVCC = -20mA 15
Regulator drop voltage VD2 400 600 mV VS > 4V, IVCC = -50mA 15
Regulator drop voltage VD3 200 mV VS > 3.3V, IVCC = -15mA 15
Line regulation VCCline 0.1 0.2 % 5.5V < VS < 18V 15
Load regulation VCCload 0.1 0.5 % 5mA < IVCC < 50mA 15
Output current limitation IVCClim -240 -160 -85 mA VS > 5.5V 15
External load capacity Cload 1.8 10 µF 0.2Ω < ESR < 5Ω at 100kHz for phase margin ≥ 60° 15
VCC undervoltage threshold VthunN 4.2 4.8 V Referred to VCC, VS > 5.5V 15
Hysteresis of undervoltage threshold Vhysthun 250 mV Referred to VCC, VS > 5.5V 15
Ramp up time VS > 5.5V to VCC = 5V tVCC 130 300 µs CVCC = 2.2µF, Iload = -5mA at VCC 15
Driver dominant voltage VS = 7V, Rload = 500Ω V_LoSUP 1.2 V VS = 7V, Rload = 500Ω 15
Driver dominant voltage VS = 18V, Rload = 500Ω V_HiSUP 2 V VS = 18V, Rload = 500Ω 15
LIN current limitation IBUS_lim 40 120 200 mA VBUS = VBatt_max 15
Pull-up resistor to VS RLIN 20 30 60 kΩ The serial diode is mandatory 15
Input leakage current at the receiver, driver off IBUS_PAS_dom -1 -0.35 mA Driver off, VBUS = 0V, VBatt = 12V 16
Leakage current LIN recessive IBUS_PAS_rec 10 20 µA Driver off, 8V < VBatt < 18V, 8V < VBUS < 18V, VBUS ≥ VBatt 16
Leakage current when control unit disconnected from ground IBUS_NO_gnd -10 0.5 10 µA GNDDevice = VS, VBatt = 12V, 0V < VBUS < 18V 16
Leakage current at disconnected battery IBUS_NO_bat 0.1 2 µA VBatt disconnected, VSUP_Device = GND, 0V < VBUS < 18V 16
Pre-wake detection LIN low level input voltage VLINL -27 V Activates the LIN receiver; upper limit VS, 3.3V 16
Dominant time for wake-up via LIN bus tbus 30 90 150 µs VLIN = 0V 16
Duty cycle 1 D1 0.396 THRec(max) = 0.744 × VS, THDom(max) = 0.581 × VS, VS = 7.0V to 18V, tBit = 50µs 17
Duty cycle 2 D2 0.581 THRec(min) = 0.422 × VS, THDom(min) = 0.284 × VS, VS = 7.6V to 18V, tBit = 50µs 17
TXD dominant time out time tdom 6 13 20 ms VTXD = 0V 17
Slope time falling and rising edge at LIN tSLOPE_fall / tSLOPE_rise 3.5 22.5 µs VS = 7.0V to 18V 17
Propagation delay of receiver trx_pd 6 µs VS = 7.0V to 18V, trx_pd = max(trx_pdr, trx_pdf), CRXD = 20pF 17
Symmetry of receiver propagation delay rising minus falling edge trx_sym -2 2 µs VS = 7.0V to 18V, CRXD = 20pF 17

CAD (KiCad official)

  • Symbol: ATA6625C-GAQW
  • Footprint: Package_SO:SOIC-8_3.9x4.9mm_P1.27mm
  • 3D model: SO-8 (KiCad packages3D, STEP)
  • 3D model files: ata6625c-gaqw-etched.step / ata6625c-gaqw-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); ata6625c-gaqw.step / ata6625c-gaqw.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: Microchip Tech datasheet (22 pp, sha256 f8b3756fa2776b8a, retrieved 2026-11-02, tier: manufacturer)
  • Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-haiku-5-5 (text), consensus claude-sonnet-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF