component
ATA6562-GAQW1
Public Made by Adomby adom
Microchip Tech CAN ICs, SOIC-8. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.
main
ATA6562-GAQW1
Microchip Tech · CAN ICs · SOIC-8
ATA6562-GAQW1 from Microchip Tech, in a SOIC-8. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.
Pinout
| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | TXD | input | Transmit data input. |
| 2 | GND | power_in | Ground. |
| 3 | VCC | power_in | Supply voltage. |
| 4 | RXD | output | Receive data output; reads out data from the bus lines. |
| 5 | NSIL | input | Silent mode control input (low active). |
| 6 | CANL | bidirectional | Low-level CAN bus line. |
| 7 | CANH | bidirectional | High-level CAN bus line. |
| 8 | STBY | input | Standby mode control input. |
Key specifications
| Parameter | Value |
|---|---|
| Manufacturer | Microchip Tech |
| Package | SOIC-8 |
| Category | Communication Interface Chip/UART/485/232 |
| Pins | 8 |
Electrical characteristics
Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).
| Parameter | Symbol | Min | Typ | Max | Unit | Conditions | Page |
|---|---|---|---|---|---|---|---|
| Supply Voltage | VVCC | 4.5 | 5.5 | V | 11 | ||
| Supply Current in Silent Mode | IVCC_sil | 1.9 | 2.5 | 3.2 | mA | Silent mode, VTXD = VVIO | 11 |
| Supply Current Normal Mode Recessive | IVCC_rec | 2 | 5 | mA | Recessive, VTXD = VVIO | 11 | |
| Supply Current Normal Mode Dominant | IVCC_dom | 30 | 50 | 70 | mA | Dominant, VTXD = 0V | 11 |
| Supply Current Normal Mode Short | IVCC_short | 85 | mA | Short between CANH and CANL (Note 1) | 11 | ||
| Supply Current in Standby Mode | IVCC_STBY | 12 | µA | VCC = VIO, VTXD = VNSIL = VVIO | 11 | ||
| Supply Current in Standby Mode | IVCC_STBY | 7 | µA | Ta = 25°C (Note 3) | 11 | ||
| Undervoltage Detection Threshold on Pin VCC | Vuvd(VCC) | 2.75 | 4.5 | V | 11 | ||
| High-Level Input Voltage (NSIL, STBY) | VIH | 0.7 | V | min 0.7 VVIO; max VVIO +0.3 | 12 | ||
| Low-Level Input Voltage (NSIL, STBY) | VIL | -0.3 | 0.3 | V | max 0.3 VVIO | 12 | |
| Pull-Up Resistor (NSIL, STBY) | Rpu | 75 | 125 | 175 | kΩ | VSTBY = 0V, VNSIL = 0V | 12 |
| High-Level Leakage Current | IL | -2 | 2 | µA | VSTBY = VVIO, VNSIL = VVIO | 12 | |
| TXD High-Level Input Voltage | VIH | 0.7 | V | min 0.7 VVIO; max VVIO +0.3 | 12 | ||
| TXD Low-Level Input Voltage | VIL | -0.3 | 0.3 | V | max 0.3 VVIO | 12 | |
| TXD Pull-Up Resistor | RTXD | 20 | 35 | 50 | kΩ | VTXD = 0V | 12 |
| TXD High-Level Leakage Current | ITXD | -2 | 2 | µA | Normal mode, VTXD = VVIO | 12 | |
| TXD Input Capacitance | CTXD | 5 | 10 | pF | Note 3 | 12 | |
| RXD High-Level Output Current | IOH | -8 | -1 | mA | Normal mode, VRXD = VVIO, 0.4V, VVIO = VVCC | 12 | |
| RXD Low-Level Output Current, Bus Dominant | IOL | 2 | 12 | mA | Normal mode, VRXD = 0.4V, Bus Dominant | 12 | |
| Single Ended Dominant Output Voltage CANH | VO(dom) | 2.75 | 3.5 | 4.5 | V | VTXD = 0V, t < tto(dom)TXD, RL = 50Ω to 65Ω, pin CANH (Note 1) | 12 |
| Single Ended Dominant Output Voltage CANL | VO(dom) | 0.5 | 1.5 | 2.25 | V | VTXD = 0V, t < tto(dom)TXD, RL = 50Ω to 65Ω, pin CANL (Note 1) | 12 |
| Transmitter Voltage Symmetry | VSym | 0.9 | 1 | 1.1 | VSym = (VCANH + VCANL) / VVCC, Split Termination, RL = 2 x 30, CSplit = 4.7 nF (Note 3) | 12 | |
| Bus Differential Output Voltage | VDiff | 1.5 | 3 | V | VTXD = 0V, t < tto(dom)TXD, RL = 45Ω to 65Ω | 12 | |
| Bus Differential Output Voltage | VDiff | 1.5 | 3.3 | V | RL = 70Ω (Note 3) | 12 | |
| Bus Differential Output Voltage | VDiff | 1.5 | 5 | V | RL = 2240Ω (Note 3) | 12 | |
| Bus Differential Output Voltage, recessive | VDiff | -50 | 50 | mV | Normal and Silent mode: VVCC = 4.75V to 5.25V, VTXD = VVIO, recessive, no load | 12 | |
| Bus Differential Output Voltage, recessive | VDiff | -200 | 200 | mV | Standby mode: VVCC = 4.75V to 5.25V, VTXD = VVIO, recessive, no load | 12 | |
| Single Ended Recessive Output Voltage | VO(rec) | 2 | 0.5 | 3 | V | Normal and Silent mode, VTXD = VVIO, no load; typ 0.5 VVCC | 13 |
| Single Ended Recessive Output Voltage | VO(rec) | -0.1 | 0.1 | V | Standby mode, VTXD = VVIO, no load | 13 | |
| Differential Receiver Threshold Voltage | Vth(RX)dif | 0.5 | 0.7 | 0.9 | V | Normal and Silent mode (HSC), Vcm(CAN) = -27V to +27V | 13 |
| Differential Receiver Threshold Voltage | Vth(RX)dif | 0.4 | 0.7 | 1.1 | V | Standby mode (WUC), Vcm(CAN) = -27V to +27V (Note 1) | 13 |
| Differential Receiver Hysteresis Voltage | Vhys(RX)dif | 50 | 120 | 200 | mV | Normal and Silent mode (HSC), Vcm(CAN) = -27V to +27V (Note 1) | 13 |
| Dominant Output Current CANH | IIO(dom) | -75 | -35 | mA | VTXD = 0V, t < tto(dom)TXD, VVCC = 5V, pin CANH, VCANH = -5V | 13 | |
| Dominant Output Current CANL | IIO(dom) | 35 | 75 | mA | VTXD = 0V, t < tto(dom)TXD, VVCC = 5V, pin CANL, VCANL = +40V | 13 | |
| Recessive Output Current | IIO(rec) | -5 | 5 | mA | Normal and Silent mode, VTXD = VVIO, no load, VCANH = VCANL = -27V to +32V | 13 | |
| Leakage Current | IIO(leak) | -5 | 0 | 5 | µA | VVCC = VVIO = 0V, VCANH = VCANL = 5V | 13 |
| Input Resistance | Ri | 9 | 15 | 28 | kΩ | VCANH = VCANL = 4V | 13 |
| Input Resistance Deviation | ΔRi | -1 | 0 | 1 | % | Between CANH and CANL, VCANH = VCANL = 4V (Note 1) | 13 |
| Differential Input Resistance | Ri(dif) | 18 | 30 | 56 | kΩ | VCANH = VCANL = 4V (Note 1) | 13 |
| Common-mode Input Capacitance | Ci(cm) | 20 | pF | f = 500 kHz, CANH and CANL referred to GND (Note 3) | 13 | ||
| Differential Input Capacitance | Ci(dif) | 10 | pF | f = 500kHz, between CANH and CANL (Note 3) | 13 | ||
| Differential Bus Voltage Range for RECESSIVE State Detection | VDiff_rec | -3 | 0.5 | V | Normal and Silent mode (HSC) -27V ≤ VCANH ≤ +27V, -27V ≤ VCANL ≤ +27V (Note 3) | 14 | |
| Differential Bus Voltage Range for RECESSIVE State Detection | VDiff_rec | -3 | 0.4 | V | Standby mode (WUC) -27V ≤ VCANH ≤ +27V, -27V ≤ VCANL ≤ +27V (Note 3) | 14 | |
| Differential Bus Voltage Range for DOMINANT State Detection | VDiff_dom | 0.9 | 8 | V | Normal and Silent mode (HSC) -27V ≤ VCANH ≤ +27V, -27V ≤ VCANL ≤ +27V (Note 3) | 14 | |
| Differential Bus Voltage Range for DOMINANT State Detection | VDiff_dom | 1.15 | 8 | V | Standby mode (WUC) -27V ≤ VCANH ≤ +27V, -27V ≤ VCANL ≤ +27V (Note 3) | 14 | |
| Delay Time from TXD to Bus Dominant | td(TXD-busdom) | 40 | 130 | ns | Normal mode (Note 2) | 14 | |
| Delay Time from TXD to Bus Recessive | td(TXD-busrec) | 40 | 130 | ns | Normal mode (Note 2) | 14 | |
| Delay Time from Bus Dominant to RXD | td(busdom-RXD) | 20 | 100 | ns | Normal mode (Note 2) | 14 | |
| Delay Time from Bus Recessive to RXD | td(busrec-RXD) | 20 | 100 | ns | Normal mode (Note 2) | 14 | |
| Propagation Delay from TXD to RXD | tPD(TXD-RXD) | 40 | 210 | ns | Normal mode, Rising edge at pin TXD, RL = 60Ω, CL = 100 pF | 14 | |
| Propagation Delay from TXD to RXD | tPD(TXD-RXD) | 40 | 200 | ns | Normal mode, Falling edge at pin TXD, RL = 60Ω, CL = 100 pF | 14 | |
| TXD Dominant Time-Out Time | tto(dom)TXD | 0.8 | 3 | ms | VTXD = 0V, Normal mode | 14 | |
| Bus Wake-up Time-Out Time | tWake | 0.8 | 3 | ms | Standby mode | 14 | |
| Min. Dominant/Recessive Bus Wake-up Time | tFilter | 0.5 | 3 | 3.8 | µs | Standby mode | 14 |
| Thermal Shutdown of the Bus Drivers (Grade 1) | TVJsd | 150 | 195 | °C | ATA6562-GAQW1 (Grade 1) | 15 | |
| Thermal Resistance Virtual Junction to Ambient | RthvJA | 145 | K/W | SOIC8 Package | 15 | ||
| Thermal Shutdown Hysteresis | TvJsd_hys | 15 | °C | SOIC8 Package | 15 |
CAD (KiCad official)
- Symbol:
ATA6562-GAQW1 - Footprint:
Package_SO:SOIC-8_3.9x4.9mm_P1.27mm - 3D model: SOIC-8 (KiCad packages3D, STEP)
- 3D model files:
ata6562-gaqw1-etched.step/ata6562-gaqw1-etched.glbcarry the MPN laser-etched on the die in a toggleableAdom.LaserEtchgroup (Fusion-ready);ata6562-gaqw1.step/ata6562-gaqw1.glbare the bare package body.
Provenance
Data extracted from the manufacturer datasheet, not a distributor listing:
- Datasheet: Microchip Tech datasheet (32 pp, sha256
478d9e36fb86996f, retrieved 2026-11-02, tier: manufacturer) - Extractor: parts-factory
2.0.0/extract_pins 0.3, primaryclaude-sonnet-5-5(text), consensusclaude-opus-5-5(agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish. - CAD: KiCad official libraries (CC-BY-SA 4.0).
# ATA6562-GAQW1
**Microchip Tech** · CAN ICs · SOIC-8
ATA6562-GAQW1 from Microchip Tech, in a SOIC-8. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.
## Pinout
| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | TXD | input | Transmit data input. |
| 2 | GND | power_in | Ground. |
| 3 | VCC | power_in | Supply voltage. |
| 4 | RXD | output | Receive data output; reads out data from the bus lines. |
| 5 | NSIL | input | Silent mode control input (low active). |
| 6 | CANL | bidirectional | Low-level CAN bus line. |
| 7 | CANH | bidirectional | High-level CAN bus line. |
| 8 | STBY | input | Standby mode control input. |
## Key specifications
| Parameter | Value |
|---|---|
| Manufacturer | Microchip Tech |
| Package | SOIC-8 |
| Category | Communication Interface Chip/UART/485/232 |
| Pins | 8 |
## Electrical characteristics
Limits as printed in the datasheet (page.json `metadata.characteristics` carries them as data).
| Parameter | Symbol | Min | Typ | Max | Unit | Conditions | Page |
|---|---|---|---|---|---|---|---|
| Supply Voltage | VVCC | 4.5 | | 5.5 | V | | 11 |
| Supply Current in Silent Mode | IVCC_sil | 1.9 | 2.5 | 3.2 | mA | Silent mode, VTXD = VVIO | 11 |
| Supply Current Normal Mode Recessive | IVCC_rec | 2 | | 5 | mA | Recessive, VTXD = VVIO | 11 |
| Supply Current Normal Mode Dominant | IVCC_dom | 30 | 50 | 70 | mA | Dominant, VTXD = 0V | 11 |
| Supply Current Normal Mode Short | IVCC_short | | | 85 | mA | Short between CANH and CANL (Note 1) | 11 |
| Supply Current in Standby Mode | IVCC_STBY | | | 12 | µA | VCC = VIO, VTXD = VNSIL = VVIO | 11 |
| Supply Current in Standby Mode | IVCC_STBY | | 7 | | µA | Ta = 25°C (Note 3) | 11 |
| Undervoltage Detection Threshold on Pin VCC | Vuvd(VCC) | 2.75 | | 4.5 | V | | 11 |
| High-Level Input Voltage (NSIL, STBY) | VIH | 0.7 | | | V | min 0.7 VVIO; max VVIO +0.3 | 12 |
| Low-Level Input Voltage (NSIL, STBY) | VIL | -0.3 | | 0.3 | V | max 0.3 VVIO | 12 |
| Pull-Up Resistor (NSIL, STBY) | Rpu | 75 | 125 | 175 | kΩ | VSTBY = 0V, VNSIL = 0V | 12 |
| High-Level Leakage Current | IL | -2 | | 2 | µA | VSTBY = VVIO, VNSIL = VVIO | 12 |
| TXD High-Level Input Voltage | VIH | 0.7 | | | V | min 0.7 VVIO; max VVIO +0.3 | 12 |
| TXD Low-Level Input Voltage | VIL | -0.3 | | 0.3 | V | max 0.3 VVIO | 12 |
| TXD Pull-Up Resistor | RTXD | 20 | 35 | 50 | kΩ | VTXD = 0V | 12 |
| TXD High-Level Leakage Current | ITXD | -2 | | 2 | µA | Normal mode, VTXD = VVIO | 12 |
| TXD Input Capacitance | CTXD | | 5 | 10 | pF | Note 3 | 12 |
| RXD High-Level Output Current | IOH | -8 | | -1 | mA | Normal mode, VRXD = VVIO, 0.4V, VVIO = VVCC | 12 |
| RXD Low-Level Output Current, Bus Dominant | IOL | 2 | | 12 | mA | Normal mode, VRXD = 0.4V, Bus Dominant | 12 |
| Single Ended Dominant Output Voltage CANH | VO(dom) | 2.75 | 3.5 | 4.5 | V | VTXD = 0V, t < tto(dom)TXD, RL = 50Ω to 65Ω, pin CANH (Note 1) | 12 |
| Single Ended Dominant Output Voltage CANL | VO(dom) | 0.5 | 1.5 | 2.25 | V | VTXD = 0V, t < tto(dom)TXD, RL = 50Ω to 65Ω, pin CANL (Note 1) | 12 |
| Transmitter Voltage Symmetry | VSym | 0.9 | 1 | 1.1 | | VSym = (VCANH + VCANL) / VVCC, Split Termination, RL = 2 x 30, CSplit = 4.7 nF (Note 3) | 12 |
| Bus Differential Output Voltage | VDiff | 1.5 | | 3 | V | VTXD = 0V, t < tto(dom)TXD, RL = 45Ω to 65Ω | 12 |
| Bus Differential Output Voltage | VDiff | 1.5 | | 3.3 | V | RL = 70Ω (Note 3) | 12 |
| Bus Differential Output Voltage | VDiff | 1.5 | | 5 | V | RL = 2240Ω (Note 3) | 12 |
| Bus Differential Output Voltage, recessive | VDiff | -50 | | 50 | mV | Normal and Silent mode: VVCC = 4.75V to 5.25V, VTXD = VVIO, recessive, no load | 12 |
| Bus Differential Output Voltage, recessive | VDiff | -200 | | 200 | mV | Standby mode: VVCC = 4.75V to 5.25V, VTXD = VVIO, recessive, no load | 12 |
| Single Ended Recessive Output Voltage | VO(rec) | 2 | 0.5 | 3 | V | Normal and Silent mode, VTXD = VVIO, no load; typ 0.5 VVCC | 13 |
| Single Ended Recessive Output Voltage | VO(rec) | -0.1 | | 0.1 | V | Standby mode, VTXD = VVIO, no load | 13 |
| Differential Receiver Threshold Voltage | Vth(RX)dif | 0.5 | 0.7 | 0.9 | V | Normal and Silent mode (HSC), Vcm(CAN) = -27V to +27V | 13 |
| Differential Receiver Threshold Voltage | Vth(RX)dif | 0.4 | 0.7 | 1.1 | V | Standby mode (WUC), Vcm(CAN) = -27V to +27V (Note 1) | 13 |
| Differential Receiver Hysteresis Voltage | Vhys(RX)dif | 50 | 120 | 200 | mV | Normal and Silent mode (HSC), Vcm(CAN) = -27V to +27V (Note 1) | 13 |
| Dominant Output Current CANH | IIO(dom) | -75 | | -35 | mA | VTXD = 0V, t < tto(dom)TXD, VVCC = 5V, pin CANH, VCANH = -5V | 13 |
| Dominant Output Current CANL | IIO(dom) | 35 | | 75 | mA | VTXD = 0V, t < tto(dom)TXD, VVCC = 5V, pin CANL, VCANL = +40V | 13 |
| Recessive Output Current | IIO(rec) | -5 | | 5 | mA | Normal and Silent mode, VTXD = VVIO, no load, VCANH = VCANL = -27V to +32V | 13 |
| Leakage Current | IIO(leak) | -5 | 0 | 5 | µA | VVCC = VVIO = 0V, VCANH = VCANL = 5V | 13 |
| Input Resistance | Ri | 9 | 15 | 28 | kΩ | VCANH = VCANL = 4V | 13 |
| Input Resistance Deviation | ΔRi | -1 | 0 | 1 | % | Between CANH and CANL, VCANH = VCANL = 4V (Note 1) | 13 |
| Differential Input Resistance | Ri(dif) | 18 | 30 | 56 | kΩ | VCANH = VCANL = 4V (Note 1) | 13 |
| Common-mode Input Capacitance | Ci(cm) | | | 20 | pF | f = 500 kHz, CANH and CANL referred to GND (Note 3) | 13 |
| Differential Input Capacitance | Ci(dif) | | | 10 | pF | f = 500kHz, between CANH and CANL (Note 3) | 13 |
| Differential Bus Voltage Range for RECESSIVE State Detection | VDiff_rec | -3 | | 0.5 | V | Normal and Silent mode (HSC) -27V ≤ VCANH ≤ +27V, -27V ≤ VCANL ≤ +27V (Note 3) | 14 |
| Differential Bus Voltage Range for RECESSIVE State Detection | VDiff_rec | -3 | | 0.4 | V | Standby mode (WUC) -27V ≤ VCANH ≤ +27V, -27V ≤ VCANL ≤ +27V (Note 3) | 14 |
| Differential Bus Voltage Range for DOMINANT State Detection | VDiff_dom | 0.9 | | 8 | V | Normal and Silent mode (HSC) -27V ≤ VCANH ≤ +27V, -27V ≤ VCANL ≤ +27V (Note 3) | 14 |
| Differential Bus Voltage Range for DOMINANT State Detection | VDiff_dom | 1.15 | | 8 | V | Standby mode (WUC) -27V ≤ VCANH ≤ +27V, -27V ≤ VCANL ≤ +27V (Note 3) | 14 |
| Delay Time from TXD to Bus Dominant | td(TXD-busdom) | 40 | | 130 | ns | Normal mode (Note 2) | 14 |
| Delay Time from TXD to Bus Recessive | td(TXD-busrec) | 40 | | 130 | ns | Normal mode (Note 2) | 14 |
| Delay Time from Bus Dominant to RXD | td(busdom-RXD) | 20 | | 100 | ns | Normal mode (Note 2) | 14 |
| Delay Time from Bus Recessive to RXD | td(busrec-RXD) | 20 | | 100 | ns | Normal mode (Note 2) | 14 |
| Propagation Delay from TXD to RXD | tPD(TXD-RXD) | 40 | | 210 | ns | Normal mode, Rising edge at pin TXD, RL = 60Ω, CL = 100 pF | 14 |
| Propagation Delay from TXD to RXD | tPD(TXD-RXD) | 40 | | 200 | ns | Normal mode, Falling edge at pin TXD, RL = 60Ω, CL = 100 pF | 14 |
| TXD Dominant Time-Out Time | tto(dom)TXD | 0.8 | | 3 | ms | VTXD = 0V, Normal mode | 14 |
| Bus Wake-up Time-Out Time | tWake | 0.8 | | 3 | ms | Standby mode | 14 |
| Min. Dominant/Recessive Bus Wake-up Time | tFilter | 0.5 | 3 | 3.8 | µs | Standby mode | 14 |
| Thermal Shutdown of the Bus Drivers (Grade 1) | TVJsd | 150 | | 195 | °C | ATA6562-GAQW1 (Grade 1) | 15 |
| Thermal Resistance Virtual Junction to Ambient | RthvJA | | 145 | | K/W | SOIC8 Package | 15 |
| Thermal Shutdown Hysteresis | TvJsd_hys | | 15 | | °C | SOIC8 Package | 15 |
## CAD (KiCad official)
- Symbol: `ATA6562-GAQW1`
- Footprint: `Package_SO:SOIC-8_3.9x4.9mm_P1.27mm`
- 3D model: SOIC-8 (KiCad packages3D, STEP)
- 3D model files: `ata6562-gaqw1-etched.step` / `ata6562-gaqw1-etched.glb` carry the MPN laser-etched on the die in a toggleable `Adom.LaserEtch` group (Fusion-ready); `ata6562-gaqw1.step` / `ata6562-gaqw1.glb` are the bare package body.
## Provenance
Data extracted from the manufacturer datasheet, not a distributor listing:
- **Datasheet:** [Microchip Tech datasheet](docs/ata6562-gaqw1-datasheet.pdf) (32 pp, sha256 `478d9e36fb86996f`, retrieved 2026-11-02, tier: manufacturer)
- **Extractor:** parts-factory `2.0.0` / `extract_pins 0.3`, primary `claude-sonnet-5-5` (text), consensus `claude-opus-5-5` (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
- **CAD:** KiCad official libraries (CC-BY-SA 4.0).
[Datasheet PDF](docs/ata6562-gaqw1-datasheet.pdf)