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AT9880

Public Made by Adom

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ZHONGKEWEI GNSS Modules, QFN-40L-EP(5x5). Datasheet-verified pinout, KiCad symbol/footprint/3D.

componentiot-communication modulesat9880
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Contents

README

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AT9880

ZHONGKEWEI · GNSS Modules · QFN-40L-EP(5x5)

AT9880 from ZHONGKEWEI, in a QFN-40L-EP(5x5). Pinout and pin descriptions extracted from the manufacturer datasheet by ds2sf; symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 RF1 input L1-band RF signal input (1561.098 MHz min / 1575.42 MHz typ / 1602 MHz max). DC voltage must not exceed 0.8V; AC-couple with a series capacitor if the external LNA output carries DC.
2 GND power_in Ground.
3 VDD_ANA power_out Analog LDO output. Bypass with 1uF decoupling capacitor close to the pin.
4 VX_OUT power_out TCXO supply output (1.8V typ). Bypass with 1uF decoupling capacitor; feeds the external TCXO EN/VCC.
5 XREF input Reference clock input from external 26 MHz TCXO. Accepts clipped-sine drive 0.5-1.5 Vpp.
6 TST_RF unconnected Factory RF test port. Leave floating in normal application.
7 VDD_BK power_out Backup-domain LDO output. Bypass with 1uF decoupling capacitor close to the pin.
8 VBAT power_in Backup power input for the RTC/backup-RAM domain (1.4-3.6V, 3.3V typ). Keeps RTC time and backup RAM alive when the main supply is removed to enable warm/hot start.
9 VDD_IO power_in Digital I/O supply input (2.7-3.6V, 3.3V typ). Also feeds the POR and antenna-detect circuits.
10 ANT_BIAS power_out Active-antenna bias/feed with integrated current sensing for antenna open/short detection and short-circuit protection (short-protection trip 45-65 mA, typ 50 mA).
11 RTC_O output 32.768 kHz RTC oscillator output. Connect the 32.768 kHz crystal (12.5 pF CL, ≤80 kΩ ESR) between RTC_O and RTC_I.
12 RTC_I input 32.768 kHz RTC oscillator input. Other terminal of the RTC crystal.
13 GPIO2/TXD1 bidirectional UART1 TXD (default) / general-purpose digital I/O.
14 GPIO3/RXD1 bidirectional UART1 RXD (default) / general-purpose digital I/O.
15 Reserved unconnected Reserved. Leave floating when unused.
16 Reserved unconnected Reserved. Leave floating when unused.
17 nRST input Active-low external reset input, internal pull-up. Reset threshold VDD_IO ≈1.65V; internal nRESET released ~160 ms after nRST rises. Leave floating if unused.
18 GPIO1/RXD0 bidirectional UART0 RXD (default communication port) / general-purpose digital I/O.
19 GPIO0/TXD0 bidirectional UART0 TXD (default positioning output) / general-purpose digital I/O.
20 GPIO27 bidirectional General-purpose digital I/O (Vih ≥ 0.8·VDD_IO, Vil ≤ 0.2·VDD_IO, Voh ≥ VDD_IO−0.4V, Vol ≤ 0.4V; internal 80 kΩ pull-up/pull-down programmable).
21 DX_IN power_in Internal DCDC converter input (typically tied to 3.3V main supply). Decouple with a 2.2uF cap; the DCDC steps 3.3V down for the internal core LDO.
22 DX_OUT power_out Internal DCDC switching-node/output. Connect the DCDC inductor (4.7uH) and 10uF output cap; the resulting rail feeds VCORE.
23 VCORE power_in Core LDO input (1.2V min, 3.6V max). Normally sourced from DX_OUT via the DCDC, but may be driven from an external supply.
24 VDD_BB power_out Digital core LDO output (1.0V typ). Bypass with 2.2uF decoupling capacitor close to the pin.
25 GPIO22 bidirectional General-purpose digital I/O; default function is 1PPS timing output.
26 Reserved unconnected Reserved. Leave floating when unused.
27 Reserved unconnected Reserved. Leave floating when unused.
28 Reserved unconnected Factory test port. Leave floating when unused.
29 ON_OFF input Shutdown/wake control input; internal pull-up. Drive low to enter sleep mode (~50 uA); leave floating if unused.
30 GPIO4 bidirectional General-purpose digital I/O. Leave floating when unused.
31 GPIO5 bidirectional General-purpose digital I/O. Leave floating when unused.
32 GPIO8 bidirectional General-purpose digital I/O. Leave floating when unused.
33 GPIO7 bidirectional General-purpose digital I/O. Leave floating when unused.
34 GPIO6 bidirectional General-purpose digital I/O. Leave floating when unused.
35 GPIO10 bidirectional General-purpose digital I/O. Leave floating when unused.
36 GPIO9 bidirectional General-purpose digital I/O. Leave floating when unused.
37 DVDD power_out PLL LDO output. Bypass with 1uF decoupling capacitor close to the pin.
38 GND power_in Ground; also acts as RF isolation pin between RF1 and RF2 - tie directly to PCB ground plane with multiple vias.
39 RF2 input L5-band RF signal input (1176.45 MHz). DC voltage must not exceed 0.8V; AC-couple with a series capacitor if the external LNA output carries DC.
40 GND power_in Ground.
EP GND power_in Exposed thermal pad on package underside. Must be soldered directly to the PCB ground plane with a full via array for thermal and electrical grounding.

Key specifications

Parameter Value
Manufacturer ZHONGKEWEI
Package QFN-40L-EP(5x5)
Category IoT/Communication Modules
Pins 41

CAD (KiCad official)

  • Symbol: AT9880
  • Footprint: Package_DFN_QFN:QFN-40-1EP_5x5mm_P0.4mm_EP3.6x3.6mm
  • 3D model: QFN-40L-EP(5x5) (KiCad packages3D, STEP)
  • 3D model files: at9880-etched.step / at9880-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); at9880.step / at9880.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: ZHONGKEWEI datasheet (16 pp, sha256 97d93eb7c809245b, retrieved 2026-08-17, tier: lcsc)
  • Datasheet language: Chinese. Pin names, descriptions, and specs on this page were extracted and translated to English by ds2sf; the linked PDF is the manufacturer original.
  • Extractor: ds2sf (Claude). Every pin and dimension is cited to a datasheet page; it refuses to fabricate.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF