# AT91SAM9G45C-CU-999

**Microchip Tech** · Microcontroller Units (MCUs/MPUs/SOCs) · TFBGA-324

AT91SAM9G45C-CU-999 from Microchip Tech, in a TFBGA-324. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

## Pinout

| Pin | Name | Type | Function |
|---|---|---|---|
| A1 | PC27 | bidirectional | PIO line PC27 of PIO Controller C; resets as input with pull-up enabled unless it is an External Bus Interface signal (Table 3-1 note 3). |
| A2 | PC28 | bidirectional | PIO line PC28 of PIO Controller C; resets as input with pull-up enabled unless it is an External Bus Interface signal (Table 3-1 note 3). |
| A3 | PC25 | bidirectional | PIO line PC25 of PIO Controller C; resets as input with pull-up enabled unless it is an External Bus Interface signal (Table 3-1 note 3). |
| A4 | PC20 | bidirectional | PIO line PC20 of PIO Controller C; resets as input with pull-up enabled unless it is an External Bus Interface signal (Table 3-1 note 3). |
| A5 | PC12 | bidirectional | PIO line PC12 of PIO Controller C; resets as input with pull-up enabled unless it is an External Bus Interface signal (Table 3-1 note 3). |
| A6 | PC7 | bidirectional | PIO line PC7 of PIO Controller C; resets as input with pull-up enabled unless it is an External Bus Interface signal (Table 3-1 note 3). |
| A7 | PC5 | bidirectional | PIO line PC5 of PIO Controller C; resets as input with pull-up enabled unless it is an External Bus Interface signal (Table 3-1 note 3). |
| A8 | PC0 | bidirectional | PIO line PC0 of PIO Controller C; resets as input with pull-up enabled unless it is an External Bus Interface signal (Table 3-1 note 3). |
| A9 | NWR3/NBS3 | output | External bus write/byte-select strobe as listed in Table 4-1; function per Section 7.3 (not in provided pages). |
| A10 | NCS0 | output | External bus chip-select as listed in Table 4-1; function per Section 7.3 (not in provided pages). |
| A11 | DQS0 | bidirectional | Memory data strobe as listed in Table 4-1; function per Section 7.3 (not in provided pages). |
| A12 | RAS | output | SDRAM row-address strobe as listed in Table 4-1; function per Section 7.3 (not in provided pages). |
| A13 | SDCK | output | SDRAM clock as listed in Table 4-1; function per Section 7.3 (not in provided pages). |
| A14 | NSDCK | output | SDRAM complementary clock as listed in Table 4-1; function per Section 7.3 (not in provided pages). |
| A15 | D7 | bidirectional | External bus data bit as listed in Table 4-1; function per Section 7.3 (not in provided pages). |
| A16 | DDR_VREF | passive | DDR reference voltage pin; no value is stated in the provided pages. |
| A17 | D0 | bidirectional | External bus data bit as listed in Table 4-1; function per Section 7.3 (not in provided pages). |
| A18 | A14 | output | External bus address bit as listed in Table 4-1; function per Section 7.3 (not in provided pages). |
| B1 | PC31 | bidirectional | PIO line PC31 of PIO Controller C; resets as input with pull-up enabled unless it is an External Bus Interface signal (Table 3-1 note 3). |
| B2 | PC29 | bidirectional | PIO line PC29 of PIO Controller C; resets as input with pull-up enabled unless it is an External Bus Interface signal (Table 3-1 note 3). |
| B3 | PC30 | bidirectional | PIO line PC30 of PIO Controller C; resets as input with pull-up enabled unless it is an External Bus Interface signal (Table 3-1 note 3). |
| B4 | PC22 | bidirectional | PIO line PC22 of PIO Controller C; resets as input with pull-up enabled unless it is an External Bus Interface signal (Table 3-1 note 3). |
| B5 | PC17 | bidirectional | PIO line PC17 of PIO Controller C; resets as input with pull-up enabled unless it is an External Bus Interface signal (Table 3-1 note 3). |
| B6 | PC10 | bidirectional | PIO line PC10 of PIO Controller C; resets as input with pull-up enabled unless it is an External Bus Interface signal (Table 3-1 note 3). |
| B7 | PC11 | bidirectional | PIO line PC11 of PIO Controller C; resets as input with pull-up enabled unless it is an External Bus Interface signal (Table 3-1 note 3). |
| B8 | PC2 | bidirectional | PIO line PC2 of PIO Controller C; resets as input with pull-up enabled unless it is an External Bus Interface signal (Table 3-1 note 3). |
| B9 | SDA10 | output | SDRAM address line A10 as listed in Table 4-1; function per Section 7.3 (not in provided pages). |
| B10 | A17/BA1 | output | External bus address A17 or SDRAM bank address BA1 as listed in Table 4-1; function per Section 7.3 (not in provided pages). |
| B11 | DQM0 | output | Memory data mask for byte lane 0 as listed in Table 4-1; function per Section 7.3 (not in provided pages). |
| B12 | SDCKE | output | SDRAM clock enable as listed in Table 4-1; function per Section 7.3 (not in provided pages). |
| B13 | D12 | bidirectional | External bus data bit as listed in Table 4-1; function per Section 7.3 (not in provided pages). |
| B14 | D8 | bidirectional | External bus data bit as listed in Table 4-1; function per Section 7.3 (not in provided pages). |
| B15 | D4 | bidirectional | External bus data bit as listed in Table 4-1; function per Section 7.3 (not in provided pages). |
| B16 | D3 | bidirectional | External bus data bit as listed in Table 4-1; function per Section 7.3 (not in provided pages). |
| B17 | A15 | output | External bus address bit as listed in Table 4-1; function per Section 7.3 (not in provided pages). |
| B18 | A13 | output | External bus address bit as listed in Table 4-1; function per Section 7.3 (not in provided pages). |
| C1 | XIN32 | input | 32768 Hz crystal input of the slow clock oscillator; it accepts an external slow clock when OSC32BYP is set (Section 8.6.2). |
| C2 | GNDANA | power_in | Ground for the VDDANA ADC supply (Section 5.1). |
| C3 | WKUP | input | Wake-up input to the Shut Down Controller; an input change releases SHDN and wakes the system power supply (Section 8.4). |
| C4 | PC26 | bidirectional | PIO line PC26 of PIO Controller C; resets as input with pull-up enabled unless it is an External Bus Interface signal (Table 3-1 note 3). |
| C5 | PC21 | bidirectional | PIO line PC21 of PIO Controller C; resets as input with pull-up enabled unless it is an External Bus Interface signal (Table 3-1 note 3). |
| C6 | PC15 | bidirectional | PIO line PC15 of PIO Controller C; resets as input with pull-up enabled unless it is an External Bus Interface signal (Table 3-1 note 3). |
| C7 | PC9 | bidirectional | PIO line PC9 of PIO Controller C; resets as input with pull-up enabled unless it is an External Bus Interface signal (Table 3-1 note 3). |
| C8 | PC3 | bidirectional | PIO line PC3 of PIO Controller C; resets as input with pull-up enabled unless it is an External Bus Interface signal (Table 3-1 note 3). |
| C9 | NWR0/NWE | output | External bus write strobe or write enable as listed in Table 4-1; function per Section 7.3 (not in provided pages). |
| C10 | A16/BA0 | output | External bus address A16 or SDRAM bank address BA0 as listed in Table 4-1; function per Section 7.3 (not in provided pages). |
| C11 | CAS | output | SDRAM column-address strobe as listed in Table 4-1; function per Section 7.3 (not in provided pages). |
| C12 | D15 | bidirectional | External bus data bit as listed in Table 4-1; function per Section 7.3 (not in provided pages). |
| C13 | D10 | bidirectional | External bus data bit as listed in Table 4-1; function per Section 7.3 (not in provided pages). |
| C14 | D6 | bidirectional | External bus data bit as listed in Table 4-1; function per Section 7.3 (not in provided pages). |
| C15 | D2 | bidirectional | External bus data bit as listed in Table 4-1; function per Section 7.3 (not in provided pages). |
| C16 | GNDIOM | power_in | Ground shared by VDDIOM0 and VDDIOM1 (Section 5.1). |
| C17 | A18 | output | External bus address bit as listed in Table 4-1; function per Section 7.3 (not in provided pages). |
| C18 | A12 | output | External bus address bit as listed in Table 4-1; function per Section 7.3 (not in provided pages). |
| D1 | XOUT32 | output | 32768 Hz crystal output of the slow clock oscillator (Section 8.6). |
| D2 | PD20 | bidirectional | PIO line PD20 of PIO Controller D; resets as input with pull-up enabled unless it is an External Bus Interface signal (Table 3-1 note 3). |
| D3 | GNDBU | power_in | Ground for the VDDBU backup supply (Section 5.1). |
| D4 | VDDBU | power_in | Backup supply for the slow clock oscillator, RC oscillator and part of the System Controller; 1.8 V to 3.6 V (Section 5.1). |
| D5 | PC24 | bidirectional | PIO line PC24 of PIO Controller C; resets as input with pull-up enabled unless it is an External Bus Interface signal (Table 3-1 note 3). |
| D6 | PC18 | bidirectional | PIO line PC18 of PIO Controller C; resets as input with pull-up enabled unless it is an External Bus Interface signal (Table 3-1 note 3). |
| D7 | PC13 | bidirectional | PIO line PC13 of PIO Controller C; resets as input with pull-up enabled unless it is an External Bus Interface signal (Table 3-1 note 3). |
| D8 | PC6 | bidirectional | PIO line PC6 of PIO Controller C; resets as input with pull-up enabled unless it is an External Bus Interface signal (Table 3-1 note 3). |
| D9 | NWR1/NBS1 | output | External bus write or byte-select strobe as listed in Table 4-1; function per Section 7.3 (not in provided pages). |
| D10 | NANDOE | output | NAND Flash output enable as listed in Table 4-1; function per Section 7.3 (not in provided pages). |
| D11 | DQM1 | output | Memory data mask for byte lane 1 as listed in Table 4-1; function per Section 7.3 (not in provided pages). |
| D12 | D14 | bidirectional | External bus data bit as listed in Table 4-1; function per Section 7.3 (not in provided pages). |
| D13 | D9 | bidirectional | External bus data bit as listed in Table 4-1; function per Section 7.3 (not in provided pages). |
| D14 | D5 | bidirectional | External bus data bit as listed in Table 4-1; function per Section 7.3 (not in provided pages). |
| D15 | D1 | bidirectional | External bus data bit as listed in Table 4-1; function per Section 7.3 (not in provided pages). |
| D16 | VDDIOM1 | power_in | External Bus Interface 1 I/O supply; 1.65 V to 1.95 V (1.8 V typical) or 3.0 V to 3.6 V (3.3 V typical) (Section 5.1). |
| D17 | A11 | output | External bus address bit as listed in Table 4-1; function per Section 7.3 (not in provided pages). |
| D18 | A10 | output | External bus address bit as listed in Table 4-1; function per Section 7.3 (not in provided pages). |
| E1 | PD21 | bidirectional | PIO line PD21 of PIO Controller D; resets as input with pull-up enabled unless it is an External Bus Interface signal (Table 3-1 note 3). |
| E2 | TSADVREF | input | ADC reference input of the touch-screen converter, analog, referenced to VDDANA (Table 3-1). |
| E3 | VDDANA | power_in | Supply for the Analog to Digital Converter; 3.0 V to 3.6 V, 3.3 V typical (Section 5.1). |
| E4 | JTAGSEL | input | JTAG select pin; its function is not stated in the provided pages. |
| E5 | TST | input | Test pin; its function is not stated in the provided pages. |
| E6 | PC23 | bidirectional | PIO line PC23 of PIO Controller C; resets as input with pull-up enabled unless it is an External Bus Interface signal (Table 3-1 note 3). |
| E7 | PC16 | bidirectional | PIO line PC16 of PIO Controller C; resets as input with pull-up enabled unless it is an External Bus Interface signal (Table 3-1 note 3). |
| E8 | PC8 | bidirectional | PIO line PC8 of PIO Controller C; resets as input with pull-up enabled unless it is an External Bus Interface signal (Table 3-1 note 3). |
| E9 | PC1 | bidirectional | PIO line PC1 of PIO Controller C; resets as input with pull-up enabled unless it is an External Bus Interface signal (Table 3-1 note 3). |
| E10 | NANDWE | output | NAND Flash write enable as listed in Table 4-1; function per Section 7.3 (not in provided pages). |
| E11 | DQS1 | bidirectional | Memory data strobe for byte lane 1 as listed in Table 4-1; function per Section 7.3 (not in provided pages). |
| E12 | D13 | bidirectional | External bus data bit as listed in Table 4-1; function per Section 7.3 (not in provided pages). |
| E13 | D11 | bidirectional | External bus data bit as listed in Table 4-1; function per Section 7.3 (not in provided pages). |
| E14 | A4 | output | External bus address bit as listed in Table 4-1; function per Section 7.3 (not in provided pages). |
| E15 | A8 | output | External bus address bit as listed in Table 4-1; function per Section 7.3 (not in provided pages). |
| E16 | A9 | output | External bus address bit as listed in Table 4-1; function per Section 7.3 (not in provided pages). |
| E17 | A7 | output | External bus address bit as listed in Table 4-1; function per Section 7.3 (not in provided pages). |
| E18 | VDDCORE | power_in | Core supply for the processor, embedded memories and peripherals; 0.9 V to 1.1 V, 1.0 V typical (Section 5.1). |
| F1 | PD22 | bidirectional | PIO line PD22 of PIO Controller D; resets as input with pull-up enabled unless it is an External Bus Interface signal (Table 3-1 note 3). |
| F2 | PD24 | bidirectional | PIO line PD24 of PIO Controller D; resets as input with pull-up enabled unless it is an External Bus Interface signal (Table 3-1 note 3). |
| F3 | SHDN | output | Shut-down control output, software-controllable to shut the system down; released by a WKUP input change or an alarm (Section 8.4). |
| F4 | PE1 | bidirectional | PIO line PE1 of PIO Controller E; resets as input with pull-up enabled unless it is an External Bus Interface signal (Table 3-1 note 3). |
| F5 | PE3 | bidirectional | PIO line PE3 of PIO Controller E; resets as input with pull-up enabled unless it is an External Bus Interface signal (Table 3-1 note 3). |
| F6 | VDDIOM1 | power_in | External Bus Interface 1 I/O supply; 1.65 V to 1.95 V (1.8 V typical) or 3.0 V to 3.6 V (3.3 V typical) (Section 5.1). |
| F7 | PC19 | bidirectional | PIO line PC19 of PIO Controller C; resets as input with pull-up enabled unless it is an External Bus Interface signal (Table 3-1 note 3). |
| F8 | PC14 | bidirectional | PIO line PC14 of PIO Controller C; resets as input with pull-up enabled unless it is an External Bus Interface signal (Table 3-1 note 3). |
| F9 | PC4 | bidirectional | PIO line PC4 of PIO Controller C; resets as input with pull-up enabled unless it is an External Bus Interface signal (Table 3-1 note 3). |
| F10 | NCS1/SDCS | output | External bus chip-select 1 or SDRAM chip-select as listed in Table 4-1; function per Section 7.3 (not in provided pages). |
| F11 | NRD | output | External bus read strobe as listed in Table 4-1; function per Section 7.3 (not in provided pages). |
| F12 | SDWE | output | SDRAM write enable as listed in Table 4-1; function per Section 7.3 (not in provided pages). |
| F13 | A0/NBS0 | output | External bus address A0 or byte-select 0 as listed in Table 4-1; function per Section 7.3 (not in provided pages). |
| F14 | A1/NBS2/NWR2 | output | External bus address A1 or byte-select/write strobe 2 as listed in Table 4-1; function per Section 7.3 (not in provided pages). |
| F15 | A3 | output | External bus address bit as listed in Table 4-1; function per Section 7.3 (not in provided pages). |
| F16 | A6 | output | External bus address bit as listed in Table 4-1; function per Section 7.3 (not in provided pages). |
| F17 | A5 | output | External bus address bit as listed in Table 4-1; function per Section 7.3 (not in provided pages). |
| F18 | A2 | output | External bus address bit as listed in Table 4-1; function per Section 7.3 (not in provided pages). |
| G1 | PD25 | bidirectional | PIO line PD25 of PIO Controller D; resets as input with pull-up enabled unless it is an External Bus Interface signal (Table 3-1 note 3). |
| G2 | PD23 | bidirectional | PIO line PD23 of PIO Controller D; resets as input with pull-up enabled unless it is an External Bus Interface signal (Table 3-1 note 3). |
| G3 | PE6 | bidirectional | PIO line PE6 of PIO Controller E; resets as input with pull-up enabled unless it is an External Bus Interface signal (Table 3-1 note 3). |
| G4 | PE0 | bidirectional | PIO line PE0 of PIO Controller E; resets as input with pull-up enabled unless it is an External Bus Interface signal (Table 3-1 note 3). |
| G5 | PE2 | bidirectional | PIO line PE2 of PIO Controller E; resets as input with pull-up enabled unless it is an External Bus Interface signal (Table 3-1 note 3). |
| G6 | PE8 | bidirectional | PIO line PE8 of PIO Controller E; resets as input with pull-up enabled unless it is an External Bus Interface signal (Table 3-1 note 3). |
| G7 | PE4 | bidirectional | PIO line PE4 of PIO Controller E; resets as input with pull-up enabled unless it is an External Bus Interface signal (Table 3-1 note 3). |
| G8 | PE11 | bidirectional | PIO line PE11 of PIO Controller E; resets as input with pull-up enabled unless it is an External Bus Interface signal (Table 3-1 note 3). |
| G9 | GNDCORE | power_in | Ground for the VDDCORE supply (Section 5.1). |
| G10 | VDDIOM1 | power_in | External Bus Interface 1 I/O supply; 1.65 V to 1.95 V (1.8 V typical) or 3.0 V to 3.6 V (3.3 V typical) (Section 5.1). |
| G11 | VDDIOM1 | power_in | External Bus Interface 1 I/O supply; 1.65 V to 1.95 V (1.8 V typical) or 3.0 V to 3.6 V (3.3 V typical) (Section 5.1). |
| G12 | VDDCORE | power_in | Core supply for the processor, embedded memories and peripherals; 0.9 V to 1.1 V, 1.0 V typical (Section 5.1). |
| G13 | VDDCORE | power_in | Core supply for the processor, embedded memories and peripherals; 0.9 V to 1.1 V, 1.0 V typical (Section 5.1). |
| G14 | DDR_DQM0 | output | DDR2/LPDDR data mask for byte lane 0; I/O on VDDIOM0, 1.65 V to 1.95 V (Section 5.1). |
| G15 | DDR_DQS1 | bidirectional | DDR2/LPDDR data strobe for byte lane 1; I/O on VDDIOM0, 1.65 V to 1.95 V (Section 5.1). |
| G16 | DDR_BA1 | output | DDR2/LPDDR bank address bit 1; I/O on VDDIOM0, 1.65 V to 1.95 V (Section 5.1). |
| G17 | DDR_BA0 | output | DDR2/LPDDR bank address bit 0; I/O on VDDIOM0, 1.65 V to 1.95 V (Section 5.1). |
| G18 | DDR_DQS0 | bidirectional | DDR2/LPDDR data strobe for byte lane 0; I/O on VDDIOM0, 1.65 V to 1.95 V (Section 5.1). |
| H1 | PD26 | bidirectional | PIO line PD26 of PIO Controller D; resets as input with pull-up enabled unless it is an External Bus Interface signal (Table 3-1 note 3). |
| H2 | PD27 | bidirectional | PIO line PD27 of PIO Controller D; resets as input with pull-up enabled unless it is an External Bus Interface signal (Table 3-1 note 3). |
| H3 | VDDIOP1 | power_in | Peripheral I/O supply; 1.65 V to 3.6 V (Section 5.1). |
| H4 | PE13 | bidirectional | PIO line PE13 of PIO Controller E; resets as input with pull-up enabled unless it is an External Bus Interface signal (Table 3-1 note 3). |
| H5 | PE5 | bidirectional | PIO line PE5 of PIO Controller E; resets as input with pull-up enabled unless it is an External Bus Interface signal (Table 3-1 note 3). |
| H6 | PE7 | bidirectional | PIO line PE7 of PIO Controller E; resets as input with pull-up enabled unless it is an External Bus Interface signal (Table 3-1 note 3). |
| H7 | PE9 | bidirectional | PIO line PE9 of PIO Controller E; resets as input with pull-up enabled unless it is an External Bus Interface signal (Table 3-1 note 3). |
| H8 | PE10 | bidirectional | PIO line PE10 of PIO Controller E; resets as input with pull-up enabled unless it is an External Bus Interface signal (Table 3-1 note 3). |
| H9 | GNDCORE | power_in | Ground for the VDDCORE supply (Section 5.1). |
| H10 | GNDIOP | power_in | Ground for the VDDIOP0, VDDIOP1 and VDDIOP2 peripheral I/O supplies (Section 5.1). |
| H11 | VDDCORE | power_in | Core supply for the processor, embedded memories and peripherals; 0.9 V to 1.1 V, 1.0 V typical (Section 5.1). |
| H12 | GNDIOM | power_in | Ground shared by VDDIOM0 and VDDIOM1 (Section 5.1). |
| H13 | GNDIOM | power_in | Ground shared by VDDIOM0 and VDDIOM1 (Section 5.1). |
| H14 | DDR_CS | output | DDR2/LPDDR chip select; I/O on VDDIOM0, 1.65 V to 1.95 V (Section 5.1). |
| H15 | DDR_WE | output | DDR2/LPDDR write enable; I/O on VDDIOM0, 1.65 V to 1.95 V (Section 5.1). |
| H16 | DDR_DQM1 | output | DDR2/LPDDR data mask for byte lane 1; I/O on VDDIOM0, 1.65 V to 1.95 V (Section 5.1). |
| H17 | DDR_CAS | output | DDR2/LPDDR column-address strobe; I/O on VDDIOM0, 1.65 V to 1.95 V (Section 5.1). |
| H18 | DDR_NCLK | output | DDR2/LPDDR complementary clock; I/O on VDDIOM0, 1.65 V to 1.95 V (Section 5.1). |
| J1 | PE19 | bidirectional | PIO line PE19 of PIO Controller E; resets as input with pull-up enabled unless it is an External Bus Interface signal (Table 3-1 note 3). |
| J2 | PE16 | bidirectional | PIO line PE16 of PIO Controller E; resets as input with pull-up enabled unless it is an External Bus Interface signal (Table 3-1 note 3). |
| J3 | PE14 | bidirectional | PIO line PE14 of PIO Controller E; resets as input with pull-up enabled unless it is an External Bus Interface signal (Table 3-1 note 3). |
| J4 | PE15 | bidirectional | PIO line PE15 of PIO Controller E; resets as input with pull-up enabled unless it is an External Bus Interface signal (Table 3-1 note 3). |
| J5 | PE12 | bidirectional | PIO line PE12 of PIO Controller E; resets as input with pull-up enabled unless it is an External Bus Interface signal (Table 3-1 note 3). |
| J6 | PE17 | bidirectional | PIO line PE17 of PIO Controller E; resets as input with pull-up enabled unless it is an External Bus Interface signal (Table 3-1 note 3). |
| J7 | PE18 | bidirectional | PIO line PE18 of PIO Controller E; resets as input with pull-up enabled unless it is an External Bus Interface signal (Table 3-1 note 3). |
| J8 | PE20 | bidirectional | PIO line PE20 of PIO Controller E; resets as input with pull-up enabled unless it is an External Bus Interface signal (Table 3-1 note 3). |
| J9 | GNDCORE | power_in | Ground for the VDDCORE supply (Section 5.1). |
| J10 | GNDCORE | power_in | Ground for the VDDCORE supply (Section 5.1). |
| J11 | GNDIOP | power_in | Ground for the VDDIOP0, VDDIOP1 and VDDIOP2 peripheral I/O supplies (Section 5.1). |
| J12 | GNDIOM | power_in | Ground shared by VDDIOM0 and VDDIOM1 (Section 5.1). |
| J13 | GNDIOM | power_in | Ground shared by VDDIOM0 and VDDIOM1 (Section 5.1). |
| J14 | DDR_A12 | output | DDR2/LPDDR address bit 12; I/O on VDDIOM0, 1.65 V to 1.95 V (Section 5.1). |
| J15 | DDR_A13 | output | DDR2/LPDDR address bit 13; I/O on VDDIOM0, 1.65 V to 1.95 V (Section 5.1). |
| J16 | DDR_CKE | output | DDR2/LPDDR clock enable; I/O on VDDIOM0, 1.65 V to 1.95 V (Section 5.1). |
| J17 | DDR_RAS | output | DDR2/LPDDR row-address strobe; I/O on VDDIOM0, 1.65 V to 1.95 V (Section 5.1). |
| J18 | DDR_CLK | output | DDR2/LPDDR clock; I/O on VDDIOM0, 1.65 V to 1.95 V (Section 5.1). |
| K1 | PE21 | bidirectional | PIO line PE21 of PIO Controller E; resets as input with pull-up enabled unless it is an External Bus Interface signal (Table 3-1 note 3). |
| K2 | PE23 | bidirectional | PIO line PE23 of PIO Controller E; resets as input with pull-up enabled unless it is an External Bus Interface signal (Table 3-1 note 3). |
| K3 | PE26 | bidirectional | PIO line PE26 of PIO Controller E; resets as input with pull-up enabled unless it is an External Bus Interface signal (Table 3-1 note 3). |
| K4 | PE22 | bidirectional | PIO line PE22 of PIO Controller E; resets as input with pull-up enabled unless it is an External Bus Interface signal (Table 3-1 note 3). |
| K5 | PE24 | bidirectional | PIO line PE24 of PIO Controller E; resets as input with pull-up enabled unless it is an External Bus Interface signal (Table 3-1 note 3). |
| K6 | PE25 | bidirectional | PIO line PE25 of PIO Controller E; resets as input with pull-up enabled unless it is an External Bus Interface signal (Table 3-1 note 3). |
| K7 | PE27 | bidirectional | PIO line PE27 of PIO Controller E; resets as input with pull-up enabled unless it is an External Bus Interface signal (Table 3-1 note 3). |
| K8 | PE28 | bidirectional | PIO line PE28 of PIO Controller E; resets as input with pull-up enabled unless it is an External Bus Interface signal (Table 3-1 note 3). |
| K9 | VDDIOP0 | power_in | Peripheral I/O supply; 1.65 V to 3.6 V (Section 5.1). |
| K10 | VDDIOP0 | power_in | Peripheral I/O supply; 1.65 V to 3.6 V (Section 5.1). |
| K11 | GNDIOM | power_in | Ground shared by VDDIOM0 and VDDIOM1 (Section 5.1). |
| K12 | GNDIOM | power_in | Ground shared by VDDIOM0 and VDDIOM1 (Section 5.1). |
| K13 | VDDIOM0 | power_in | DDR2/LPDDR I/O supply; 1.65 V to 1.95 V, 1.8 V typical (Section 5.1). |
| K14 | DDR_A7 | output | DDR2/LPDDR address bit 7; I/O on VDDIOM0, 1.65 V to 1.95 V (Section 5.1). |
| K15 | DDR_A8 | output | DDR2/LPDDR address bit 8; I/O on VDDIOM0, 1.65 V to 1.95 V (Section 5.1). |
| K16 | DDR_A9 | output | DDR2/LPDDR address bit 9; I/O on VDDIOM0, 1.65 V to 1.95 V (Section 5.1). |
| K17 | DDR_A11 | output | DDR2/LPDDR address bit 11; I/O on VDDIOM0, 1.65 V to 1.95 V (Section 5.1). |
| K18 | DDR_A10 | output | DDR2/LPDDR address bit 10; I/O on VDDIOM0, 1.65 V to 1.95 V (Section 5.1). |
| L1 | PA0 | bidirectional | PIO line PA0 of PIO Controller A; resets as input with pull-up enabled unless it is an External Bus Interface signal (Table 3-1 note 3). |
| L2 | PE30 | bidirectional | PIO line PE30 of PIO Controller E; resets as input with pull-up enabled unless it is an External Bus Interface signal (Table 3-1 note 3). |
| L3 | PE29 | bidirectional | PIO line PE29 of PIO Controller E; resets as input with pull-up enabled unless it is an External Bus Interface signal (Table 3-1 note 3). |
| L4 | PE31 | bidirectional | PIO line PE31 of PIO Controller E; resets as input with pull-up enabled unless it is an External Bus Interface signal (Table 3-1 note 3). |
| L5 | PA2 | bidirectional | PIO line PA2 of PIO Controller A; resets as input with pull-up enabled unless it is an External Bus Interface signal (Table 3-1 note 3). |
| L6 | PA4 | bidirectional | PIO line PA4 of PIO Controller A; resets as input with pull-up enabled unless it is an External Bus Interface signal (Table 3-1 note 3). |
| L7 | PA8 | bidirectional | PIO line PA8 of PIO Controller A; resets as input with pull-up enabled unless it is an External Bus Interface signal (Table 3-1 note 3). |
| L8 | PD2 | bidirectional | PIO line PD2 of PIO Controller D; resets as input with pull-up enabled unless it is an External Bus Interface signal (Table 3-1 note 3). |
| L9 | PD13 | bidirectional | PIO line PD13 of PIO Controller D; resets as input with pull-up enabled unless it is an External Bus Interface signal (Table 3-1 note 3). |
| L10 | PD29 | bidirectional | PIO line PD29 of PIO Controller D; resets as input with pull-up enabled unless it is an External Bus Interface signal (Table 3-1 note 3). |
| L11 | PD31 | bidirectional | PIO line PD31 of PIO Controller D; resets as input with pull-up enabled unless it is an External Bus Interface signal (Table 3-1 note 3). |
| L12 | VDDIOM0 | power_in | DDR2/LPDDR I/O supply; 1.65 V to 1.95 V, 1.8 V typical (Section 5.1). |
| L13 | VDDIOM0 | power_in | DDR2/LPDDR I/O supply; 1.65 V to 1.95 V, 1.8 V typical (Section 5.1). |
| L14 | DDR_A1 | output | DDR2/LPDDR address bit 1; I/O on VDDIOM0, 1.65 V to 1.95 V (Section 5.1). |
| L15 | DDR_A3 | output | DDR2/LPDDR address bit 3; I/O on VDDIOM0, 1.65 V to 1.95 V (Section 5.1). |
| L16 | DDR_A4 | output | DDR2/LPDDR address bit 4; I/O on VDDIOM0, 1.65 V to 1.95 V (Section 5.1). |
| L17 | DDR_A6 | output | DDR2/LPDDR address bit 6; I/O on VDDIOM0, 1.65 V to 1.95 V (Section 5.1). |
| L18 | DDR_A5 | output | DDR2/LPDDR address bit 5; I/O on VDDIOM0, 1.65 V to 1.95 V (Section 5.1). |
| M1 | PA1 | bidirectional | PIO line PA1 of PIO Controller A; resets as input with pull-up enabled unless it is an External Bus Interface signal (Table 3-1 note 3). |
| M2 | PA5 | bidirectional | PIO line PA5 of PIO Controller A; resets as input with pull-up enabled unless it is an External Bus Interface signal (Table 3-1 note 3). |
| M3 | PA6 | bidirectional | PIO line PA6 of PIO Controller A; resets as input with pull-up enabled unless it is an External Bus Interface signal (Table 3-1 note 3). |
| M4 | PA7 | bidirectional | PIO line PA7 of PIO Controller A; resets as input with pull-up enabled unless it is an External Bus Interface signal (Table 3-1 note 3). |
| M5 | PA10 | bidirectional | PIO line PA10 of PIO Controller A; resets as input with pull-up enabled unless it is an External Bus Interface signal (Table 3-1 note 3). |
| M6 | PA14 | bidirectional | PIO line PA14 of PIO Controller A; resets as input with pull-up enabled unless it is an External Bus Interface signal (Table 3-1 note 3). |
| M7 | PB14 | bidirectional | PIO line PB14 of PIO Controller B; resets as input with pull-up enabled unless it is an External Bus Interface signal (Table 3-1 note 3). |
| M8 | PD4 | bidirectional | PIO line PD4 of PIO Controller D; resets as input with pull-up enabled unless it is an External Bus Interface signal (Table 3-1 note 3). |
| M9 | PD15 | bidirectional | PIO line PD15 of PIO Controller D; resets as input with pull-up enabled unless it is an External Bus Interface signal (Table 3-1 note 3). |
| M10 | NRST | bidirectional | Active-low reset: as input it asynchronously resets the device when pulled low; the Reset Controller also drives it as an output (Note 2, Section 8.3). |
| M11 | PB11 | bidirectional | PIO line PB11 of PIO Controller B; resets as input with pull-up enabled unless it is an External Bus Interface signal (Table 3-1 note 3). |
| M12 | PB25 | bidirectional | PIO line PB25 of PIO Controller B; resets as input with pull-up enabled unless it is an External Bus Interface signal (Table 3-1 note 3). |
| M13 | PB27 | bidirectional | PIO line PB27 of PIO Controller B; resets as input with pull-up enabled unless it is an External Bus Interface signal (Table 3-1 note 3). |
| M14 | VDDIOM0 | power_in | DDR2/LPDDR I/O supply; 1.65 V to 1.95 V, 1.8 V typical (Section 5.1). |
| M15 | DDR_D14 | bidirectional | DDR2/LPDDR data bit 14; I/O on VDDIOM0, 1.65 V to 1.95 V (Section 5.1). |
| M16 | DDR_D15 | bidirectional | DDR2/LPDDR data bit 15; I/O on VDDIOM0, 1.65 V to 1.95 V (Section 5.1). |
| M17 | DDR_A0 | output | DDR2/LPDDR address bit 0; I/O on VDDIOM0, 1.65 V to 1.95 V (Section 5.1). |
| M18 | DDR_A2 | output | DDR2/LPDDR address bit 2; I/O on VDDIOM0, 1.65 V to 1.95 V (Section 5.1). |
| N1 | PA3 | bidirectional | PIO line PA3 of PIO Controller A; resets as input with pull-up enabled unless it is an External Bus Interface signal (Table 3-1 note 3). |
| N2 | PA9 | bidirectional | PIO line PA9 of PIO Controller A; resets as input with pull-up enabled unless it is an External Bus Interface signal (Table 3-1 note 3). |
| N3 | PA12 | bidirectional | PIO line PA12 of PIO Controller A; resets as input with pull-up enabled unless it is an External Bus Interface signal (Table 3-1 note 3). |
| N4 | PA15 | bidirectional | PIO line PA15 of PIO Controller A; resets as input with pull-up enabled unless it is an External Bus Interface signal (Table 3-1 note 3). |
| N5 | PA16 | bidirectional | PIO line PA16 of PIO Controller A; resets as input with pull-up enabled unless it is an External Bus Interface signal (Table 3-1 note 3). |
| N6 | PA17 | bidirectional | PIO line PA17 of PIO Controller A; resets as input with pull-up enabled unless it is an External Bus Interface signal (Table 3-1 note 3). |
| N7 | PB18 | bidirectional | PIO line PB18 of PIO Controller B; resets as input with pull-up enabled unless it is an External Bus Interface signal (Table 3-1 note 3). |
| N8 | PD6 | bidirectional | PIO line PD6 of PIO Controller D; resets as input with pull-up enabled unless it is an External Bus Interface signal (Table 3-1 note 3). |
| N9 | PD16 | bidirectional | PIO line PD16 of PIO Controller D; resets as input with pull-up enabled unless it is an External Bus Interface signal (Table 3-1 note 3). |
| N10 | NTRST | input | JTAG/boundary-scan TAP reset input (Section 8.2 block diagram); its electrical limits are not stated in the provided pages. |
| N11 | PB9 | bidirectional | PIO line PB9 of PIO Controller B; resets as input with pull-up enabled unless it is an External Bus Interface signal (Table 3-1 note 3). |
| N12 | PB24 | bidirectional | PIO line PB24 of PIO Controller B; resets as input with pull-up enabled unless it is an External Bus Interface signal (Table 3-1 note 3). |
| N13 | PB28 | bidirectional | PIO line PB28 of PIO Controller B; resets as input with pull-up enabled unless it is an External Bus Interface signal (Table 3-1 note 3). |
| N14 | DDR_D13 | bidirectional | DDR2/LPDDR data bit 13; I/O on VDDIOM0, 1.65 V to 1.95 V (Section 5.1). |
| N15 | DDR_D8 | bidirectional | DDR2/LPDDR data bit 8; I/O on VDDIOM0, 1.65 V to 1.95 V (Section 5.1). |
| N16 | DDR_D9 | bidirectional | DDR2/LPDDR data bit 9; I/O on VDDIOM0, 1.65 V to 1.95 V (Section 5.1). |
| N17 | DDR_D11 | bidirectional | DDR2/LPDDR data bit 11; I/O on VDDIOM0, 1.65 V to 1.95 V (Section 5.1). |
| N18 | DDR_D12 | bidirectional | DDR2/LPDDR data bit 12; I/O on VDDIOM0, 1.65 V to 1.95 V (Section 5.1). |
| P1 | PA11 | bidirectional | PIO line PA11 of PIO Controller A; resets as input with pull-up enabled unless it is an External Bus Interface signal (Table 3-1 note 3). |
| P2 | PA13 | bidirectional | PIO line PA13 of PIO Controller A; resets as input with pull-up enabled unless it is an External Bus Interface signal (Table 3-1 note 3). |
| P3 | PA19 | bidirectional | PIO line PA19 of PIO Controller A; resets as input with pull-up enabled unless it is an External Bus Interface signal (Table 3-1 note 3). |
| P4 | PA21 | bidirectional | PIO line PA21 of PIO Controller A; resets as input with pull-up enabled unless it is an External Bus Interface signal (Table 3-1 note 3). |
| P5 | PA23 | bidirectional | PIO line PA23 of PIO Controller A; resets as input with pull-up enabled unless it is an External Bus Interface signal (Table 3-1 note 3). |
| P6 | PB12 | bidirectional | PIO line PB12 of PIO Controller B; resets as input with pull-up enabled unless it is an External Bus Interface signal (Table 3-1 note 3). |
| P7 | PB19 | bidirectional | PIO line PB19 of PIO Controller B; resets as input with pull-up enabled unless it is an External Bus Interface signal (Table 3-1 note 3). |
| P8 | PD8 | bidirectional | PIO line PD8 of PIO Controller D; resets as input with pull-up enabled unless it is an External Bus Interface signal (Table 3-1 note 3). |
| P9 | PD28 | bidirectional | PIO line PD28 of PIO Controller D; resets as input with pull-up enabled unless it is an External Bus Interface signal (Table 3-1 note 3). |
| P10 | TMS | input | JTAG test mode select input of the boundary-scan TAP controller (Section 8.2); electrical limits are not stated in the provided pages. |
| P11 | VDDPLLA | power_in | Supply for the PLLA cell; 0.9 V to 1.1 V (Section 5.1). |
| P12 | PB20 | bidirectional | PIO line PB20 of PIO Controller B; resets as input with pull-up enabled unless it is an External Bus Interface signal (Table 3-1 note 3). |
| P13 | PB31 | bidirectional | PIO line PB31 of PIO Controller B; resets as input with pull-up enabled unless it is an External Bus Interface signal (Table 3-1 note 3). |
| P14 | DDR_D7 | bidirectional | DDR2/LPDDR data bit 7; I/O on VDDIOM0, 1.65 V to 1.95 V (Section 5.1). |
| P15 | DDR_D3 | bidirectional | DDR2/LPDDR data bit 3; I/O on VDDIOM0, 1.65 V to 1.95 V (Section 5.1). |
| P16 | DDR_D4 | bidirectional | DDR2/LPDDR data bit 4; I/O on VDDIOM0, 1.65 V to 1.95 V (Section 5.1). |
| P17 | DDR_D5 | bidirectional | DDR2/LPDDR data bit 5; I/O on VDDIOM0, 1.65 V to 1.95 V (Section 5.1). |
| P18 | DDR_D10 | bidirectional | DDR2/LPDDR data bit 10; I/O on VDDIOM0, 1.65 V to 1.95 V (Section 5.1). |
| R1 | PA18 | bidirectional | PIO line PA18 of PIO Controller A; resets as input with pull-up enabled unless it is an External Bus Interface signal (Table 3-1 note 3). |
| R2 | PA20 | bidirectional | PIO line PA20 of PIO Controller A; resets as input with pull-up enabled unless it is an External Bus Interface signal (Table 3-1 note 3). |
| R3 | PA24 | bidirectional | PIO line PA24 of PIO Controller A; resets as input with pull-up enabled unless it is an External Bus Interface signal (Table 3-1 note 3). |
| R4 | PA30 | bidirectional | PIO line PA30 of PIO Controller A; resets as input with pull-up enabled unless it is an External Bus Interface signal (Table 3-1 note 3). |
| R5 | PB4 | bidirectional | PIO line PB4 of PIO Controller B; resets as input with pull-up enabled unless it is an External Bus Interface signal (Table 3-1 note 3). |
| R6 | PB13 | bidirectional | PIO line PB13 of PIO Controller B; resets as input with pull-up enabled unless it is an External Bus Interface signal (Table 3-1 note 3). |
| R7 | PD0 | bidirectional | PIO line PD0 of PIO Controller D; resets as input with pull-up enabled unless it is an External Bus Interface signal (Table 3-1 note 3). |
| R8 | PD9 | bidirectional | PIO line PD9 of PIO Controller D; resets as input with pull-up enabled unless it is an External Bus Interface signal (Table 3-1 note 3). |
| R9 | PD18 | bidirectional | PIO line PD18 of PIO Controller D; resets as input with pull-up enabled unless it is an External Bus Interface signal (Table 3-1 note 3). |
| R10 | TDI | input | JTAG test data input of the boundary-scan TAP controller (Section 8.2); electrical limits are not stated in the provided pages. |
| R11 | RTCK | output | JTAG return test clock output of the debug interface; electrical limits are not stated in the provided pages. |
| R12 | PB22 | bidirectional | PIO line PB22 of PIO Controller B; resets as input with pull-up enabled unless it is an External Bus Interface signal (Table 3-1 note 3). |
| R13 | PB29 | bidirectional | PIO line PB29 of PIO Controller B; resets as input with pull-up enabled unless it is an External Bus Interface signal (Table 3-1 note 3). |
| R14 | DDR_D6 | bidirectional | DDR2/LPDDR data bit 6; I/O on VDDIOM0, 1.65 V to 1.95 V (Section 5.1). |
| R15 | DDR_D1 | bidirectional | DDR2/LPDDR data bit 1; I/O on VDDIOM0, 1.65 V to 1.95 V (Section 5.1). |
| R16 | DDR_D0 | bidirectional | DDR2/LPDDR data bit 0; I/O on VDDIOM0, 1.65 V to 1.95 V (Section 5.1). |
| R17 | HHSDMA | bidirectional | USB high-speed port A data-minus line (name only); function per Section 9.4 (not in provided pages). |
| R18 | HFSDMA | bidirectional | USB full-speed port A data-minus line (name only); function per Section 9.4 (not in provided pages). |
| T1 | PA22 | bidirectional | PIO line PA22 of PIO Controller A; resets as input with pull-up enabled unless it is an External Bus Interface signal (Table 3-1 note 3). |
| T2 | PA25 | bidirectional | PIO line PA25 of PIO Controller A; resets as input with pull-up enabled unless it is an External Bus Interface signal (Table 3-1 note 3). |
| T3 | PA26 | bidirectional | PIO line PA26 of PIO Controller A; resets as input with pull-up enabled unless it is an External Bus Interface signal (Table 3-1 note 3). |
| T4 | PB0 | bidirectional | PIO line PB0 of PIO Controller B; resets as input with pull-up enabled unless it is an External Bus Interface signal (Table 3-1 note 3). |
| T5 | PB6 | bidirectional | PIO line PB6 of PIO Controller B; resets as input with pull-up enabled unless it is an External Bus Interface signal (Table 3-1 note 3). |
| T6 | PB16 | bidirectional | PIO line PB16 of PIO Controller B; resets as input with pull-up enabled unless it is an External Bus Interface signal (Table 3-1 note 3). |
| T7 | PD1 | bidirectional | PIO line PD1 of PIO Controller D; resets as input with pull-up enabled unless it is an External Bus Interface signal (Table 3-1 note 3). |
| T8 | PD11 | bidirectional | PIO line PD11 of PIO Controller D; resets as input with pull-up enabled unless it is an External Bus Interface signal (Table 3-1 note 3). |
| T9 | PD19 | bidirectional | PIO line PD19 of PIO Controller D; resets as input with pull-up enabled unless it is an External Bus Interface signal (Table 3-1 note 3). |
| T10 | PD30 | bidirectional | PIO line PD30 of PIO Controller D; resets as input with pull-up enabled unless it is an External Bus Interface signal (Table 3-1 note 3). |
| T11 | BMS | input | Boot mode select input; its function is not stated in the provided pages. |
| T12 | PB8 | bidirectional | PIO line PB8 of PIO Controller B; resets as input with pull-up enabled unless it is an External Bus Interface signal (Table 3-1 note 3). |
| T13 | PB30 | bidirectional | PIO line PB30 of PIO Controller B; resets as input with pull-up enabled unless it is an External Bus Interface signal (Table 3-1 note 3). |
| T14 | DDR_D2 | bidirectional | DDR2/LPDDR data bit 2; I/O on VDDIOM0, 1.65 V to 1.95 V (Section 5.1). |
| T15 | PB21 | bidirectional | PIO line PB21 of PIO Controller B; resets as input with pull-up enabled unless it is an External Bus Interface signal (Table 3-1 note 3). |
| T16 | PB23 | bidirectional | PIO line PB23 of PIO Controller B; resets as input with pull-up enabled unless it is an External Bus Interface signal (Table 3-1 note 3). |
| T17 | HHSDPA | bidirectional | USB high-speed port A data-plus line (name only); function per Section 9.4 (not in provided pages). |
| T18 | HFSDPA | bidirectional | USB full-speed port A data-plus line (name only); function per Section 9.4 (not in provided pages). |
| U1 | PA27 | bidirectional | PIO line PA27 of PIO Controller A; resets as input with pull-up enabled unless it is an External Bus Interface signal (Table 3-1 note 3). |
| U2 | PA29 | bidirectional | PIO line PA29 of PIO Controller A; resets as input with pull-up enabled unless it is an External Bus Interface signal (Table 3-1 note 3). |
| U3 | PA28 | bidirectional | PIO line PA28 of PIO Controller A; resets as input with pull-up enabled unless it is an External Bus Interface signal (Table 3-1 note 3). |
| U4 | PB3 | bidirectional | PIO line PB3 of PIO Controller B; resets as input with pull-up enabled unless it is an External Bus Interface signal (Table 3-1 note 3). |
| U5 | PB7 | bidirectional | PIO line PB7 of PIO Controller B; resets as input with pull-up enabled unless it is an External Bus Interface signal (Table 3-1 note 3). |
| U6 | PB17 | bidirectional | PIO line PB17 of PIO Controller B; resets as input with pull-up enabled unless it is an External Bus Interface signal (Table 3-1 note 3). |
| U7 | PD7 | bidirectional | PIO line PD7 of PIO Controller D; resets as input with pull-up enabled unless it is an External Bus Interface signal (Table 3-1 note 3). |
| U8 | PD10 | bidirectional | PIO line PD10 of PIO Controller D; resets as input with pull-up enabled unless it is an External Bus Interface signal (Table 3-1 note 3). |
| U9 | PD14 | bidirectional | PIO line PD14 of PIO Controller D; resets as input with pull-up enabled unless it is an External Bus Interface signal (Table 3-1 note 3). |
| U10 | TCK | input | JTAG test clock input of the boundary-scan TAP controller (Section 8.2); electrical limits are not stated in the provided pages. |
| U11 | VDDOSC | power_in | Supply for the main oscillator cells; 1.65 V to 3.6 V (Section 5.1). |
| U12 | GNDOSC | power_in | Ground shared by VDDPLLUTMI, VDDPLLA and VDDOSC (Section 5.1). |
| U13 | PB10 | bidirectional | PIO line PB10 of PIO Controller B; resets as input with pull-up enabled unless it is an External Bus Interface signal (Table 3-1 note 3). |
| U14 | PB26 | bidirectional | PIO line PB26 of PIO Controller B; resets as input with pull-up enabled unless it is an External Bus Interface signal (Table 3-1 note 3). |
| U15 | HHSDPB/DHSDP | bidirectional | USB high-speed port B data-plus line (name only); function per Section 9.4 (not in provided pages). |
| U16 | HHSDMB/DHSDM | bidirectional | USB high-speed port B data-minus line (name only); function per Section 9.4 (not in provided pages). |
| U17 | GNDUTMI | power_in | Ground for the VDDUTMIC and VDDUTMII UTMI+ supplies (Section 5.1). |
| U18 | VDDUTMIC | power_in | USB device and host UTMI+ core supply; 0.9 V to 1.1 V, 1.0 V typical (Section 5.1). |
| V1 | PA31 | bidirectional | PIO line PA31 of PIO Controller A; resets as input with pull-up enabled unless it is an External Bus Interface signal (Table 3-1 note 3). |
| V2 | PB1 | bidirectional | PIO line PB1 of PIO Controller B; resets as input with pull-up enabled unless it is an External Bus Interface signal (Table 3-1 note 3). |
| V3 | PB2 | bidirectional | PIO line PB2 of PIO Controller B; resets as input with pull-up enabled unless it is an External Bus Interface signal (Table 3-1 note 3). |
| V4 | PB5 | bidirectional | PIO line PB5 of PIO Controller B; resets as input with pull-up enabled unless it is an External Bus Interface signal (Table 3-1 note 3). |
| V5 | PB15 | bidirectional | PIO line PB15 of PIO Controller B; resets as input with pull-up enabled unless it is an External Bus Interface signal (Table 3-1 note 3). |
| V6 | PD3 | bidirectional | PIO line PD3 of PIO Controller D; resets as input with pull-up enabled unless it is an External Bus Interface signal (Table 3-1 note 3). |
| V7 | PD5 | bidirectional | PIO line PD5 of PIO Controller D; resets as input with pull-up enabled unless it is an External Bus Interface signal (Table 3-1 note 3). |
| V8 | PD12 | bidirectional | PIO line PD12 of PIO Controller D; resets as input with pull-up enabled unless it is an External Bus Interface signal (Table 3-1 note 3). |
| V9 | PD17 | bidirectional | PIO line PD17 of PIO Controller D; resets as input with pull-up enabled unless it is an External Bus Interface signal (Table 3-1 note 3). |
| V10 | TDO | output | JTAG test data output of the boundary-scan TAP controller (Section 8.2); electrical limits are not stated in the provided pages. |
| V11 | XOUT | output | 12 MHz main oscillator output; the main oscillator can be bypassed (Section 8.5). |
| V12 | XIN | input | 12 MHz main oscillator input; the main oscillator can be bypassed (Section 8.5). |
| V13 | VDDPLLUTMI | power_in | Supply for the PLLUTMI cell; 0.9 V to 1.1 V (Section 5.1). |
| V14 | VDDIOP2 | power_in | Peripheral I/O supply; 1.65 V to 3.6 V (Section 5.1). |
| V15 | HFSDPB/DFSDP | bidirectional | USB full-speed port B data-plus line (name only); function per Section 9.4 (not in provided pages). |
| V16 | HFSDMB/DFSDM | bidirectional | USB full-speed port B data-minus line (name only); function per Section 9.4 (not in provided pages). |
| V17 | VDDUTMII | power_in | USB UTMI+ interface supply; 3.0 V to 3.6 V, 3.3 V typical (Section 5.1). |
| V18 | VBG | passive | Bandgap voltage reference pin; no function or limit is stated in the provided pages. |

## Key specifications

| Parameter | Value |
|---|---|
| Manufacturer | Microchip Tech |
| Package | TFBGA-324 |
| Category | Single Chip Microcomputer/Microcontroller |
| Pins | 324 |

## Electrical characteristics

Limits as printed in the datasheet (page.json `metadata.characteristics` carries them as data).

| Parameter | Symbol | Min | Typ | Max | Unit | Conditions | Page |
|---|---|---|---|---|---|---|---|
| Operating temperature range |  | -40 |  | 85 | °C | Industrial grade, Green package, TFBGA324 (ordering table) | 50 |

## CAD (KiCad official)

- Symbol: `AT91SAM9G45C-CU-999`
- Footprint: `Package_BGA:TFBGA-324_12x12mm_Layout18x18_P0.65mm`
- 3D model: TFBGA-324, generated from the KiCad footprint (body from the F.Fab outline, terminals on the pads, 1.0 mm nominal BGA height). Neither the vendor nor KiCad ships a 3D model for this package, so the dimensions are nominal, not the manufacturer's CAD (STEP)
- 3D model files: `at91sam9g45c-cu-999-etched.step` / `at91sam9g45c-cu-999-etched.glb` carry the MPN laser-etched on the die in a toggleable `Adom.LaserEtch` group (Fusion-ready); `at91sam9g45c-cu-999.step` / `at91sam9g45c-cu-999.glb` are the bare package body.

## Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

- **Datasheet:** [Microchip Tech datasheet](docs/at91sam9g45c-cu-999-datasheet.pdf) (53 pp, sha256 `31a84aea709b592b`, retrieved 2026-10-29, tier: manufacturer)
- **Extractor:** parts-factory `2.0.0` / `extract_pins 0.3`, primary `claude-haiku-5-5` (text), consensus `claude-sonnet-5-5` (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
- **CAD:** KiCad official libraries (CC-BY-SA 4.0).

[Datasheet PDF](docs/at91sam9g45c-cu-999-datasheet.pdf)