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AT91SAM7X256C-AUR

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Microchip Tech Pre-ordered MCUs, LQFP-100(14x14). Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.

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AT91SAM7X256C-AUR

Microchip Tech · Pre-ordered MCUs · LQFP-100(14x14)

AT91SAM7X256C-AUR from Microchip Tech, in a LQFP-100(14x14). Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 ADVREF input ADC reference voltage; conversions span 0V to ADVREF, and ADVREF should be connected to GND when the ADC is not used.
2 GND power_in Ground pin; all GND pins should be connected as shortly as possible to the system ground plane.
3 AD4 input ADC analog input channel AD4; should be connected to GND when the voltage regulator and ADC are not used.
4 AD5 input ADC analog input channel AD5; should be connected to GND when the voltage regulator and ADC are not used.
5 AD6 input ADC analog input channel AD6; should be connected to GND when the voltage regulator and ADC are not used.
6 AD7 input ADC analog input channel AD7; should be connected to GND when the voltage regulator and ADC are not used.
7 VDDOUT power_out Output of the 1.8V voltage regulator, requiring 470 pF or 1 nF NPO plus 2.2 µF or 3.3 µF X7R decoupling to GND.
8 VDDIN power_in Supply input for the voltage regulator and ADC, 3.0V to 3.6V (3.3V nominal).
9 PB27/AD0 bidirectional PIO line PB27, also ADC analog input AD0.
10 PB28/AD1 bidirectional PIO line PB28, also ADC analog input AD1.
11 PB29/AD2 bidirectional PIO line PB29, also ADC analog input AD2.
12 PB30/AD3 bidirectional PIO line PB30, also ADC analog input AD3.
13 PA8/PGMM0 bidirectional PIO line PA8, also parallel programming mode pin PGMM0.
14 PA9/PGMM1 bidirectional PIO line PA9, also parallel programming mode pin PGMM1.
15 VDDCORE power_in Core logic supply, 1.65V to 1.95V (1.8V typical), required for the device and embedded Flash to operate.
16 GND power_in Ground pin; all GND pins should be connected as shortly as possible to the system ground plane.
17 VDDIO power_in I/O line supply, 3.0V to 3.6V (3.3V nominal).
18 PA10/PGMM2 bidirectional PIO line PA10, also parallel programming mode pin PGMM2.
19 PA11/PGMM3 bidirectional PIO line PA11, also parallel programming mode pin PGMM3.
20 PA12/PGMD0 bidirectional PIO line PA12, also parallel programming data pin PGMD0.
21 PA13/PGMD1 bidirectional PIO line PA13, also parallel programming data pin PGMD1.
22 PA14/PGMD2 bidirectional PIO line PA14, also parallel programming data pin PGMD2.
23 PA15/PGMD3 bidirectional PIO line PA15, also parallel programming data pin PGMD3.
24 PA16/PGMD4 bidirectional PIO line PA16, also parallel programming data pin PGMD4.
25 PA17/PGMD5 bidirectional PIO line PA17, also parallel programming data pin PGMD5.
26 PA18/PGMD6 bidirectional PIO line PA18, also parallel programming data pin PGMD6.
27 PB9 bidirectional PIO line PB9, also used as EMDIO (Ethernet management data input/output).
28 PB8 bidirectional PIO line PB8, also used as EMDC (Ethernet management data clock).
29 PB14 bidirectional PIO line PB14, also used as ERX3 (Ethernet receive data) and SPI0_NPCS2.
30 PB13 bidirectional PIO line PB13, also used as ERX2 (Ethernet receive data) and SPI0_NPCS1.
31 PB6 bidirectional PIO line PB6, also used as ERX1 (Ethernet receive data).
32 GND power_in Ground pin; all GND pins should be connected as shortly as possible to the system ground plane.
33 VDDIO power_in I/O line supply, 3.0V to 3.6V (3.3V nominal).
34 PB5 bidirectional PIO line PB5, also used as ERX0 (Ethernet receive data).
35 PB15 bidirectional PIO line PB15, also used as ERXDV/ECRSDV (Ethernet receive data valid or carrier sense).
36 PB17 bidirectional PIO line PB17, also used as ERXCK (Ethernet receive clock) and SPI0_NPCS3.
37 VDDCORE power_in Core logic supply, 1.65V to 1.95V (1.8V typical), required for the device and embedded Flash to operate.
38 PB7 bidirectional PIO line PB7, also used as ERXER (Ethernet receive error).
39 PB12 bidirectional PIO line PB12, also used as ETXER (Ethernet transmit error) and TCLK0.
40 PB0 bidirectional PIO line PB0, also used as ETXCK/EREFCK (Ethernet transmit clock or RMII reference clock) and PCK0.
41 PB1 bidirectional PIO line PB1, also used as ETXEN (Ethernet transmit enable).
42 PB2 bidirectional PIO line PB2, also used as ETX0 (Ethernet transmit data).
43 PB3 bidirectional PIO line PB3, also used as ETX1 (Ethernet transmit data).
44 PB10 bidirectional PIO line PB10, also used as ETX2 (Ethernet transmit data) and SPI1_NPCS1.
45 PB11 bidirectional PIO line PB11, also used as ETX3 (Ethernet transmit data) and SPI1_NPCS2.
46 PA19/PGMD7 bidirectional PIO line PA19, also used as CANRX (CAN receive) and parallel programming data pin PGMD7.
47 PA20/PGMD8 bidirectional PIO line PA20, also used as CANTX (CAN transmit) and parallel programming data pin PGMD8.
48 VDDIO power_in I/O line supply, 3.0V to 3.6V (3.3V nominal).
49 PA21/PGMD9 bidirectional PIO line PA21, also used as TF (SSC frame sync) and parallel programming data pin PGMD9.
50 PA22/PGMD10 bidirectional PIO line PA22, also used as TK (SSC clock) and parallel programming data pin PGMD10.
51 TDI input JTAG/ICE test data input.
52 GND power_in Ground pin; all GND pins should be connected as shortly as possible to the system ground plane.
53 PB16 bidirectional PIO line PB16, also used as ECOL (Ethernet collision detect) and SPI1_NPCS3.
54 PB4 bidirectional PIO line PB4, also used as ECRS (Ethernet carrier sense).
55 PA23/PGMD11 bidirectional PIO line PA23, also used as TD (SSC transmit data) and parallel programming data pin PGMD11.
56 PA24/PGMD12 bidirectional PIO line PA24, also used as RD (SSC receive data) and parallel programming data pin PGMD12.
57 NRST bidirectional Microcontroller reset, active low; an input/output that can be driven low by the reset controller.
58 TST input Test mode select; must be tied low to ensure normal operating conditions.
59 PA25/PGMD13 bidirectional PIO line PA25, also used as RK (SSC receive clock) and parallel programming data pin PGMD13.
60 PA26/PGMD14 bidirectional PIO line PA26, also used as RF (SSC receive frame sync) and parallel programming data pin PGMD14.
61 VDDIO power_in I/O line supply, 3.0V to 3.6V (3.3V nominal).
62 VDDCORE power_in Core logic supply, 1.65V to 1.95V (1.8V typical), required for the device and embedded Flash to operate.
63 PB18 bidirectional PIO line PB18, also used as EF100 (Ethernet force 100 Mbit/s) and ADTRG.
64 PB19 bidirectional PIO line PB19, also used as PWM0 and TCLK1.
65 PB20 bidirectional PIO line PB20, also used as PWM1 and PCK0.
66 PB21 bidirectional PIO line PB21, also used as PWM2 and PCK2.
67 PB22 bidirectional PIO line PB22, also used as PWM3 and PCK2.
68 GND power_in Ground pin; all GND pins should be connected as shortly as possible to the system ground plane.
69 PB23 bidirectional PIO line PB23, also used as TIOA0 and DCD1.
70 PB24 bidirectional PIO line PB24, also used as TIOB0 and DSR1.
71 PB25 bidirectional PIO line PB25, also used as TIOA1 and DTR1.
72 PB26 bidirectional PIO line PB26, also used as TIOB1 and RI1.
73 PA27/PGMD15 bidirectional PIO line PA27, also used as DRXD (Debug Unit receive data) and parallel programming data pin PGMD15.
74 PA28 bidirectional PIO line PA28, also used as DTXD (Debug Unit transmit data).
75 PA29 bidirectional PIO line PA29, also used as FIQ (fast interrupt input).
76 TDO output JTAG/ICE test data output.
77 JTAGSEL input JTAG selection; low selects EmbeddedICE mode, high selects IEEE 1149.1 JTAG boundary scan, and a chip reset is required after changing it.
78 TMS input JTAG/ICE test mode select.
79 TCK input JTAG/ICE test clock.
80 PA30 bidirectional PIO line PA30, also used as IRQ0 and PCK2.
81 PA0/PGMEN0 bidirectional PIO line PA0, also used as RXD0 and parallel programming enable pin PGMEN0.
82 PA1/PGMEN1 bidirectional PIO line PA1, also used as TXD0 and parallel programming enable pin PGMEN1.
83 GND power_in Ground pin; all GND pins should be connected as shortly as possible to the system ground plane.
84 VDDIO power_in I/O line supply, 3.0V to 3.6V (3.3V nominal).
85 PA3 bidirectional PIO line PA3, also used as RTS0 and SPI1_NPCS2.
86 PA2 bidirectional PIO line PA2, also used as SCK0 and SPI1_NPCS1.
87 VDDCORE power_in Core logic supply, 1.65V to 1.95V (1.8V typical), required for the device and embedded Flash to operate.
88 PA4/PGMNCMD bidirectional PIO line PA4, also used as CTS0 and parallel programming command pin PGMNCMD.
89 PA5/PGMRDY bidirectional PIO line PA5, also used as RXD1 and parallel programming ready pin PGMRDY.
90 PA6/PGMNOE bidirectional PIO line PA6, also used as TXD1 and parallel programming output enable pin PGMNOE.
91 PA7/PGMNVALID bidirectional PIO line PA7, also used as SCK1 and parallel programming valid pin PGMNVALID.
92 ERASE input External hardware ERASE request; the only way to reset the security bit once it is set.
93 DDM bidirectional USB device port D- data line.
94 DDP bidirectional USB device port D+ data line.
95 VDDFLASH power_in Supply for the USB transceivers and part of the Flash, 3.0V to 3.6V (3.3V nominal); required for Flash operation.
96 GND power_in Ground pin; all GND pins should be connected as shortly as possible to the system ground plane.
97 XIN/PGMCK input Main oscillator input, 3 to 20 MHz, also used as parallel programming clock PGMCK; the main oscillator can be bypassed.
98 XOUT output Main oscillator output, 3 to 20 MHz.
99 PLLRC input PLL loop filter connection for the clock generator PLL, which outputs 80 to 200 MHz.
100 VDDPLL power_in Supply for the oscillator and PLL; can be connected directly to VDDOUT.

Key specifications

Parameter Value
Manufacturer Microchip Tech
Package LQFP-100(14x14)
Category Embedded Processors & Controllers
Pins 100

Electrical characteristics

Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).

Parameter Symbol Min Typ Max Unit Conditions Page
Operating Temperature (Industrial) -40 85 °C 581
Storage Temperature -60 150 °C 581
Voltage on Input Pins with Respect to Ground -0.3 5.5 V 581
Maximum Operating Voltage (VDDCORE, and VDDPLL) 2 V 581
Total DC Output Current on all I/O lines 200 mA 100-lead LQFP package 581
DC Supply Core VVDDCORE 1.65 1.95 V 582
DC Supply PLL VVDDPLL 1.65 1.95 V 582
DC Supply I/Os VVDDIO 3 3.6 V 582
DC Supply Flash VVDDFLASH 3 3.6 V 582
Input Low-level Voltage VIL -0.3 0.8 V VVDDIO from 3.0V to 3.6V 582
Input High-level Voltage VIH 2 5.5 V VVDDIO from 3.0V to 3.6V 582
Output Low-level Voltage VOL 0.4 V IO = 8 mA, VVDDIO from 3.0V to 3.6V 582
Output Low-level Voltage (CMOS) VOL 0.1 V IO = 0.3 mA, (CMOS) VVDDIO from 3.0V to 3.6V 582
Input Leakage Current ILEAK 40 400 nA PA0-PA3, Pull-up resistors disabled (Typ: TA = 25°C, Max: TA = 85°C) 582
Input Leakage Current ILEAK 20 200 nA Other PIOs and NRST, Pull-up resistors disabled (Typ: TA = 25°C, Max: TA = 85°C) 582
Input Pull-up Current IPULLUP 10 20.6 60 µA PB27-PB30, VVDDIO from 3.0V to 3.6V, PAx connected to ground 582
Input Pull-up Current IPULLUP 143 321 600 µA Other PIOs and NRST, VVDDIO from 3.0V to 3.6V, PAx connected to ground 582
Input Pull-down Current (TST, ERASE, JTAGSEL) IPULLDOWN 135 295 550 µA VVDDIO from 3.0V to 3.6V, Pins connected to VVDDIO 582
Input Capacitance CIN 13.9 pF 100 LQFP Package 582
Static Current (SAM7X512/256/128) TA = 25°C ISC 12 60 µA On VVDDCORE = 1.85V, MCK = 500Hz; all inputs driven at 1 µA (including TMS, TDI, TCK, NRST); Flash in standby mode; all peripherals off 582
Static Current (SAM7X512/256/128) TA = 85°C ISC 100 400 µA On VVDDCORE = 1.85V, MCK = 500Hz; all inputs driven at 1 µA (including TMS, TDI, TCK, NRST); Flash in standby mode; all peripherals off 582
IO Output Current IO 16 mA PA0-PA3, VVDDIO from 3.0V to 3.6V 582
IO Output Current IO 2 mA PB27-PB30 and NRST, VVDDIO from 3.0V to 3.6V 582
IO Output Current IO 8 mA Other PIOs, VVDDIO from 3.0V to 3.6V 582
Supply Voltage VVDDIN 3 3.3 3.6 V 582
Output Voltage VVDDOUT 1.81 1.85 1.89 V IO = 20 mA 582
Current Consumption IVDDIN 10 25 µA After startup, Idle mode, no load 583
Maximum DC Output Current IO 100 mA VDDIN = 3.3V 583
VDDCORE Threshold Level VBOT18- 1.65 1.68 1.71 V 583
VDDCORE Hysteresis VHYST18 50 65 mV VHYST18 = VBOT18+ - VBOT18- 583
VDDFLASH Threshold Level VBOT33- 2.7 2.8 2.9 V 583
VDDFLASH Hysteresis VHYST33 70 120 mV VHYST33 = VBOT33+ - VBOT33- 583
Current Consumption IDD 24 30 µA BOD on (GPNVM0 bit active) 583
Current Consumption IDD 1 µA BOD off (GPNVM0 bit inactive) 583
Power-up delay TPU 45 µS 583
Standby current @25°C ISB 10 30 µA @25°C onto VDDCORE = 1.8V onto VDDFLASH = 3.3V 583
Standby current @85°C ISB 10 120 µA @85°C onto VDDCORE = 1.8V onto VDDFLASH = 3.3V 583
Active current Random Read @ 30MHz ICC 3 mA Random Read @ 30MHz onto VDDCORE = 1.8V 583
Active current Random Read @ 30MHz ICC 0.8 mA Random Read @ 30MHz onto VDDFLASH = 3.3V 583
RC Oscillator Frequency 1/(tCPRC) 22 32 42 kHz VDDPLL = 1.65V 586
Crystal Oscillator Frequency 1/(tCPMAIN) 3 16 20 MHz 587
Internal Load Capacitance (CL1 = CL2) CL1, CL2 34 40 46 pF Integrated Load Capacitance ((XIN or XOUT)) 587
Equivalent Load Capacitance CL 17 20 23 pF Integrated Load Capacitance (XIN and XOUT in series) 587
PLL Output Frequency FOUT 80 160 MHz Field out of CKGR_PLL is: 00 589
PLL Output Frequency FOUT 150 200 MHz Field out of CKGR_PLL is: 10 589
PLL Input Frequency FIN 1 32 MHz 589
High Level Output VOH 2.8 3.6 V Measured with RL of 14.25 kOhm tied to GND 590
Low Level Output VOL 0 0.3 V Measured with RL of 1.425 kOhm tied to 3.6V 590
Output Signal Crossover Voltage VCRS 1.3 2 V Measure conditions described in Figure 38-3 590
Master Clock Frequency 1/(tCPMCK) 55 MHz 593
Pin Group 1 frequency FreqMaxI01 12.5 MHz Pin Group 1 (PB27 to PB30), Load: 40 pF 593
Pin Group 3 frequency FreqMaxI03 30 MHz Pin Group 3 (PA0 to PA3), Load: 40 pF 593
ADC Clock Frequency 5 MHz 10-bit resolution mode 592
Integral Non-linearity -2 2 LSB 592
Absolute Accuracy -4 4 LSB 592
ETXER toggling from ETXCK rising EMAC8 25 ns Load: 20pF 596
Recommended External USB Series Resistor REXT 27 Ω In series with each USB pin 590
Recommended External USB Series Resistor tolerance REXT -5 5 % In series with each USB pin with ±5% 590

CAD (KiCad official)

  • Symbol: AT91SAM7X256C-AUR
  • Footprint: Package_QFP:LQFP-100_14x14mm_P0.5mm
  • 3D model: LQFP-100(14x14) (KiCad packages3D, STEP)
  • 3D model files: at91sam7x256c-aur-etched.step / at91sam7x256c-aur-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); at91sam7x256c-aur.step / at91sam7x256c-aur.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: Microchip Tech datasheet (662 pp, sha256 41e5028c31f5768b, retrieved 2026-10-27, tier: manufacturer)
  • Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-haiku-5-5 (text), consensus claude-sonnet-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF