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AT91SAM7X256C-AU
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Microchip Tech ATMEL & AVR, TQFP-100(14x14). Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.
Generated by kicad-footprint-generator · KiCad file format 20260206
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AT91SAM7X256C-AU
Microchip Tech · ATMEL & AVR · TQFP-100(14x14)
AT91SAM7X256C-AU from Microchip Tech, in a TQFP-100(14x14). Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.
Pinout
| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | ADVREF | power_in | ADC reference voltage; conversions span 0V to ADVREF, and it should be tied to GND if the ADC is unused. |
| 2 | GND | power_in | Ground; only shared GND pins are provided and should be connected as shortly as possible to the system ground plane. |
| 3 | AD4 | input | Dedicated ADC analog input channel 4; connect to GND if the ADC is not used. |
| 4 | AD5 | input | Dedicated ADC analog input channel 5; connect to GND if the ADC is not used. |
| 5 | AD6 | input | Dedicated ADC analog input channel 6; connect to GND if the ADC is not used. |
| 6 | AD7 | input | Dedicated ADC analog input channel 7; connect to GND if the ADC is not used. |
| 7 | VDDOUT | power_out | Output of the 1.8V voltage regulator, needing 470 pF (or 1 nF) NPO plus 2.2 µF (or 3.3 µF) X7R decoupling to GND; leave unconnected if the regulator is unused. |
| 8 | VDDIN | power_in | Powers the voltage regulator and the ADC, 3.0V to 3.6V (3.3V nominal); connect to GND if the regulator and ADC are not used. |
| 9 | PB27/AD0 | bidirectional | PIO line PB27 multiplexed with TIOA2/PWM0 and ADC analog input AD0. |
| 10 | PB28/AD1 | bidirectional | PIO line PB28 multiplexed with TIOB2/PWM1 and ADC analog input AD1. |
| 11 | PB29/AD2 | bidirectional | PIO line PB29 multiplexed with PCK1/PWM2 and ADC analog input AD2. |
| 12 | PB30/AD3 | bidirectional | PIO line PB30 multiplexed with PCK2/PWM3 and ADC analog input AD3. |
| 13 | PA8/PGMM0 | bidirectional | PIO line PA8 (RTS1/SPI0_NPCS2) that is also fast flash programming mode pin PGMM0. |
| 14 | PA9/PGMM1 | bidirectional | PIO line PA9 (CTS1/SPI0_NPCS3) that is also fast flash programming mode pin PGMM1. |
| 15 | VDDCORE | power_in | Powers the device logic and embedded Flash, 1.65V to 1.95V (1.8V typical); can be connected to VDDOUT with decoupling. |
| 16 | GND | power_in | Ground; connect as shortly as possible to the system ground plane. |
| 17 | VDDIO | power_in | Powers the I/O lines, 3.0V to 3.6V (3.3V nominal). |
| 18 | PA10/PGMM2 | bidirectional | PIO line PA10 (TWD) that is also fast flash programming mode pin PGMM2. |
| 19 | PA11/PGMM3 | bidirectional | PIO line PA11 (TWCK) that is also fast flash programming mode pin PGMM3. |
| 20 | PA12/PGMD0 | bidirectional | PIO line PA12 (SPI0_NPCS0) that is also fast flash programming data bit PGMD0. |
| 21 | PA13/PGMD1 | bidirectional | PIO line PA13 (SPI0_NPCS1/PCK1) that is also fast flash programming data bit PGMD1. |
| 22 | PA14/PGMD2 | bidirectional | PIO line PA14 (SPI0_NPCS2/IRQ1) that is also fast flash programming data bit PGMD2. |
| 23 | PA15/PGMD3 | bidirectional | PIO line PA15 (SPI0_NPCS3/TCLK2) that is also fast flash programming data bit PGMD3. |
| 24 | PA16/PGMD4 | bidirectional | PIO line PA16 (SPI0_MISO) that is also fast flash programming data bit PGMD4. |
| 25 | PA17/PGMD5 | bidirectional | PIO line PA17 (SPI0_MOSI) that is also fast flash programming data bit PGMD5. |
| 26 | PA18/PGMD6 | bidirectional | PIO line PA18 (SPI0_SPCK) that is also fast flash programming data bit PGMD6. |
| 27 | PB9 | bidirectional | PIO line PB9 multiplexed with EMAC management data input/output EMDIO. |
| 28 | PB8 | bidirectional | PIO line PB8 multiplexed with EMAC management data clock EMDC. |
| 29 | PB14 | bidirectional | PIO line PB14 multiplexed with EMAC receive data ERX3 and SPI0_NPCS2. |
| 30 | PB13 | bidirectional | PIO line PB13 multiplexed with EMAC receive data ERX2 and SPI0_NPCS1. |
| 31 | PB6 | bidirectional | PIO line PB6 multiplexed with EMAC receive data ERX1. |
| 32 | GND | power_in | Ground; connect as shortly as possible to the system ground plane. |
| 33 | VDDIO | power_in | Powers the I/O lines, 3.0V to 3.6V (3.3V nominal). |
| 34 | PB5 | bidirectional | PIO line PB5 multiplexed with EMAC receive data ERX0. |
| 35 | PB15 | bidirectional | PIO line PB15 multiplexed with EMAC ERXDV (MII) / ECRSDV (RMII). |
| 36 | PB17 | bidirectional | PIO line PB17 multiplexed with EMAC receive clock ERXCK and SPI0_NPCS3. |
| 37 | VDDCORE | power_in | Powers the device logic and embedded Flash, 1.65V to 1.95V (1.8V typical). |
| 38 | PB7 | bidirectional | PIO line PB7 multiplexed with EMAC receive error ERXER. |
| 39 | PB12 | bidirectional | PIO line PB12 multiplexed with EMAC transmit error ETXER and TCLK0. |
| 40 | PB0 | bidirectional | PIO line PB0 multiplexed with EMAC ETXCK/EREFCK and PCK0. |
| 41 | PB1 | bidirectional | PIO line PB1 multiplexed with EMAC transmit enable ETXEN. |
| 42 | PB2 | bidirectional | PIO line PB2 multiplexed with EMAC transmit data ETX0. |
| 43 | PB3 | bidirectional | PIO line PB3 multiplexed with EMAC transmit data ETX1. |
| 44 | PB10 | bidirectional | PIO line PB10 multiplexed with EMAC transmit data ETX2 and SPI1_NPCS1. |
| 45 | PB11 | bidirectional | PIO line PB11 multiplexed with EMAC transmit data ETX3 and SPI1_NPCS2. |
| 46 | PA19/PGMD7 | bidirectional | PIO line PA19 (CANRX) that is also fast flash programming data bit PGMD7. |
| 47 | PA20/PGMD8 | bidirectional | PIO line PA20 (CANTX) that is also fast flash programming data bit PGMD8. |
| 48 | VDDIO | power_in | Powers the I/O lines, 3.0V to 3.6V (3.3V nominal). |
| 49 | PA21/PGMD9 | bidirectional | PIO line PA21 (TF/SPI1_NPCS0) that is also fast flash programming data bit PGMD9. |
| 50 | PA22/PGMD10 | bidirectional | PIO line PA22 (TK/SPI1_SPCK) that is also fast flash programming data bit PGMD10. |
| 51 | TDI | input | JTAG Test Data In input. |
| 52 | GND | power_in | Ground; connect as shortly as possible to the system ground plane. |
| 53 | PB16 | bidirectional | PIO line PB16 multiplexed with EMAC collision detect ECOL (MII only) and SPI1_NPCS3. |
| 54 | PB4 | bidirectional | PIO line PB4 multiplexed with EMAC carrier sense ECRS (MII only). |
| 55 | PA23/PGMD11 | bidirectional | PIO line PA23 (TD/SPI1_MOSI) that is also fast flash programming data bit PGMD11. |
| 56 | PA24/PGMD12 | bidirectional | PIO line PA24 (RD/SPI1_MISO) that is also fast flash programming data bit PGMD12. |
| 57 | NRST | bidirectional | Active-low microcontroller reset, input/output. |
| 58 | TST | input | Test mode select, active high; must be tied low for normal operation. |
| 59 | PA25/PGMD13 | bidirectional | PIO line PA25 (RK/SPI1_NPCS1) that is also fast flash programming data bit PGMD13. |
| 60 | PA26/PGMD14 | bidirectional | PIO line PA26 (RF/SPI1_NPCS2) that is also fast flash programming data bit PGMD14. |
| 61 | VDDIO | power_in | Powers the I/O lines, 3.0V to 3.6V (3.3V nominal). |
| 62 | VDDCORE | power_in | Powers the device logic and embedded Flash, 1.65V to 1.95V (1.8V typical). |
| 63 | PB18 | bidirectional | PIO line PB18 multiplexed with EMAC EF100 and ADC external trigger ADTRG. |
| 64 | PB19 | bidirectional | PIO line PB19 multiplexed with PWM0 and TCLK1. |
| 65 | PB20 | bidirectional | PIO line PB20 multiplexed with PWM1 and PCK0. |
| 66 | PB21 | bidirectional | PIO line PB21 multiplexed with PWM2 and PCK2. |
| 67 | PB22 | bidirectional | PIO line PB22 multiplexed with PWM3 and PCK2. |
| 68 | GND | power_in | Ground; connect as shortly as possible to the system ground plane. |
| 69 | PB23 | bidirectional | PIO line PB23 multiplexed with TIOA0 and DCD1. |
| 70 | PB24 | bidirectional | PIO line PB24 multiplexed with TIOB0 and DSR1. |
| 71 | PB25 | bidirectional | PIO line PB25 multiplexed with TIOA1 and DTR1. |
| 72 | PB26 | bidirectional | PIO line PB26 multiplexed with TIOB1 and RI1. |
| 73 | PA27/PGMD15 | bidirectional | PIO line PA27 (DRXD/PCK3) that is also fast flash programming data bit PGMD15. |
| 74 | PA28 | bidirectional | PIO line PA28 multiplexed with debug transmit data DTXD. |
| 75 | PA29 | bidirectional | PIO line PA29 multiplexed with FIQ and SPI1_NPCS3. |
| 76 | TDO | output | JTAG Test Data Out output. |
| 77 | JTAGSEL | input | JTAG selection: low selects EmbeddedICE mode, high enables IEEE 1149.1 boundary scan; a chip reset is required after changing it. |
| 78 | TMS | input | JTAG Test Mode Select input. |
| 79 | TCK | input | JTAG Test Clock input. |
| 80 | PA30 | bidirectional | PIO line PA30 multiplexed with IRQ0 and PCK2. |
| 81 | PA0/PGMEN0 | bidirectional | PIO line PA0 (RXD0) that is also fast flash programming enable pin PGMEN0. |
| 82 | PA1/PGMEN1 | bidirectional | PIO line PA1 (TXD0) that is also fast flash programming enable pin PGMEN1. |
| 83 | GND | power_in | Ground; connect as shortly as possible to the system ground plane. |
| 84 | VDDIO | power_in | Powers the I/O lines, 3.0V to 3.6V (3.3V nominal). |
| 85 | PA3 | bidirectional | PIO line PA3 multiplexed with RTS0 and SPI1_NPCS2. |
| 86 | PA2 | bidirectional | PIO line PA2 multiplexed with SCK0 and SPI1_NPCS1. |
| 87 | VDDCORE | power_in | Powers the device logic and embedded Flash, 1.65V to 1.95V (1.8V typical). |
| 88 | PA4/PGMNCMD | bidirectional | PIO line PA4 (CTS0/SPI1_NPCS3) that is also fast flash programming pin PGMNCMD. |
| 89 | PA5/PGMRDY | bidirectional | PIO line PA5 (RXD1) that is also fast flash programming pin PGMRDY. |
| 90 | PA6/PGMNOE | bidirectional | PIO line PA6 (TXD1) that is also fast flash programming pin PGMNOE. |
| 91 | PA7/PGMNVALID | bidirectional | PIO line PA7 (SCK1/SPI0_NPCS1) that is also fast flash programming pin PGMNVALID. |
| 92 | ERASE | input | Hardware Flash erase request; the only way to reset the security bit, erasing the full memory plane and clearing lock and GPNVM bits. |
| 93 | DDM | bidirectional | USB device port data minus (D-) line. |
| 94 | DDP | bidirectional | USB device port data plus (D+) line. |
| 95 | VDDFLASH | power_in | Powers the USB transceivers and part of the Flash, required for Flash operation; 3.0V to 3.6V (3.3V nominal). |
| 96 | GND | power_in | Ground; connect as shortly as possible to the system ground plane. |
| 97 | XIN/PGMCK | input | Main oscillator input (3 to 20 MHz, can be bypassed) that is also fast flash programming clock PGMCK. |
| 98 | XOUT | output | Main oscillator output. |
| 99 | PLLRC | passive | PLL external RC filter connection (PLL output ranges 80 to 200 MHz). |
| 100 | VDDPLL | power_in | Powers the oscillator and the PLL; can be connected directly to VDDOUT. |
Key specifications
| Parameter | Value |
|---|---|
| Manufacturer | Microchip Tech |
| Package | TQFP-100(14x14) |
| Category | Embedded Processors & Controllers |
| Pins | 100 |
CAD (KiCad official)
- Symbol:
AT91SAM7X256C-AU - Footprint:
Package_QFP:TQFP-100_14x14mm_P0.5mm - 3D model: TQFP-100(14x14) (KiCad packages3D, STEP)
- 3D model files:
at91sam7x256c-au-etched.step/at91sam7x256c-au-etched.glbcarry the MPN laser-etched on the die in a toggleableAdom.LaserEtchgroup (Fusion-ready);at91sam7x256c-au.step/at91sam7x256c-au.glbare the bare package body.
Provenance
Data extracted from the manufacturer datasheet, not a distributor listing:
- Datasheet: Microchip Tech datasheet (662 pp, sha256
50c7960c1f4db2dc, retrieved 2026-10-22, tier: manufacturer) - Extractor: parts-factory
2.0.0/extract_pins 0.3, primaryclaude-sonnet-5-5(text), consensusclaude-sonnet-5-5(agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish. - CAD: KiCad official libraries (CC-BY-SA 4.0).