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AT91SAM7S64C-AU
Public Made by Adomby adom
Microchip Tech Microcontrollers (MCU/MPU/SOC), LQFP-64(10x10). Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.
3D Model
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Symbol & Footprint
Schematic Symbol
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PCB Footprint
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Datasheet
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README
markdownAT91SAM7S64C-AU
Microchip Tech · Microcontrollers (MCU/MPU/SOC) · LQFP-64(10x10)
AT91SAM7S64C-AU from Microchip Tech, in a LQFP-64(10x10). Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.
Pinout
| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | ADVREF | power_in | ADC analog reference input, shared with the 8-channel 10-bit ADC. |
| 2 | GND | power_in | Ground; the datasheet provides no separate ground pins per supply, so GND pins should be connected as short as possible to the system ground plane. |
| 3 | AD4 | input | ADC analog input channel 4 (analog-only); connect to GND if the ADC is not used. |
| 4 | AD5 | input | ADC analog input channel 5 (analog-only); connect to GND if the ADC is not used. |
| 5 | AD6 | input | ADC analog input channel 6 (analog-only); connect to GND if the ADC is not used. |
| 6 | AD7 | input | ADC analog input channel 7 (analog-only); connect to GND if the ADC is not used. |
| 7 | VDDIN | power_in | Supplies the voltage regulator and the ADC, 3.0 V to 3.6 V (3.3 V nominal). |
| 8 | VDDOUT | power_out | Output of the 1.8 V regulator (100 mA in Normal Mode), decoupled with 470 pF (or 1 nF) NPO plus 2.2 µF (or 3.3 µF) X7R to GND close to the chip. |
| 9 | PA17/PGMD5/AD0 | bidirectional | PIOA line 17 multiplexed with Fast Flash programming data PGMD5 and ADC input AD0; AD0-AD3 are listed as pulled-up digital inputs at reset. |
| 10 | PA18/PGMD6/AD1 | bidirectional | PIOA line 18 multiplexed with Fast Flash programming data PGMD6 and ADC input AD1; AD0-AD3 are listed as pulled-up digital inputs at reset. |
| 11 | PA21/PGMD9 | bidirectional | PIOA line 21 multiplexed with Fast Flash programming data PGMD9; PIO lines are 5 V-tolerant on this device. |
| 12 | VDDCORE | power_in | Core logic supply, 1.65 V to 1.95 V (1.8 V typical); required for the device including embedded Flash to operate. |
| 13 | PA19/PGMD7/AD2 | bidirectional | PIOA line 19 multiplexed with Fast Flash programming data PGMD7 and ADC input AD2; AD0-AD3 are listed as pulled-up digital inputs at reset. |
| 14 | PA22/PGMD10 | bidirectional | PIOA line 22 multiplexed with Fast Flash programming data PGMD10; PIO lines are 5 V-tolerant on this device. |
| 15 | PA23/PGMD11 | bidirectional | PIOA line 23 multiplexed with Fast Flash programming data PGMD11; PIO lines are 5 V-tolerant on this device. |
| 16 | PA20/PGMD8/AD3 | bidirectional | PIOA line 20 multiplexed with Fast Flash programming data PGMD8 and ADC input AD3; AD0-AD3 are listed as pulled-up digital inputs at reset. |
| 17 | GND | power_in | Ground; connect as short as possible to the system ground plane. |
| 18 | VDDIO | power_in | I/O and USB transceiver supply, 3.0 V to 3.6 V (3.3 V nominal) or 1.65 V to 1.95 V (1.8 V nominal); below 3.0 V the USB transceivers cannot be used. |
| 19 | PA16/PGMD4 | bidirectional | PIOA line 16 multiplexed with Fast Flash programming data PGMD4; PIO lines are 5 V-tolerant on this device. |
| 20 | PA15/PGMD3 | bidirectional | PIOA line 15 multiplexed with Fast Flash programming data PGMD3; PIO lines are 5 V-tolerant on this device. |
| 21 | PA14/PGMD2 | bidirectional | PIOA line 14 multiplexed with Fast Flash programming data PGMD2; PIO lines are 5 V-tolerant on this device. |
| 22 | PA13/PGMD1 | bidirectional | PIOA line 13 multiplexed with Fast Flash programming data PGMD1; PIO lines are 5 V-tolerant on this device. |
| 23 | PA24/PGMD12 | bidirectional | PIOA line 24 multiplexed with Fast Flash programming data PGMD12; PIO lines are 5 V-tolerant on this device. |
| 24 | VDDCORE | power_in | Core logic supply, 1.65 V to 1.95 V (1.8 V typical). |
| 25 | PA25/PGMD13 | bidirectional | PIOA line 25 multiplexed with Fast Flash programming data PGMD13; PIO lines are 5 V-tolerant on this device. |
| 26 | PA26/PGMD14 | bidirectional | PIOA line 26 multiplexed with Fast Flash programming data PGMD14; PIO lines are 5 V-tolerant on this device. |
| 27 | PA12/PGMD0 | bidirectional | PIOA line 12 multiplexed with Fast Flash programming data PGMD0; PIO lines are 5 V-tolerant on this device. |
| 28 | PA11/PGMM3 | bidirectional | PIOA line 11 multiplexed with Fast Flash programming mode input PGMM3; PIO lines are 5 V-tolerant on this device. |
| 29 | PA10/PGMM2 | bidirectional | PIOA line 10 multiplexed with Fast Flash programming mode input PGMM2; PIO lines are 5 V-tolerant on this device. |
| 30 | PA9/PGMM1 | bidirectional | PIOA line 9 multiplexed with Fast Flash programming mode input PGMM1; PIO lines are 5 V-tolerant on this device. |
| 31 | PA8/PGMM0 | bidirectional | PIOA line 8 multiplexed with Fast Flash programming mode input PGMM0; PIO lines are 5 V-tolerant on this device. |
| 32 | PA7/PGMNVALID | bidirectional | PIOA line 7 multiplexed with Fast Flash programming data direction output PGMNVALID (active low); PIO lines are 5 V-tolerant on this device. |
| 33 | TDI | input | JTAG test data input for the IEEE 1149.1 boundary scan and ICE interface. |
| 34 | PA6/PGMNOE | bidirectional | PIOA line 6 multiplexed with Fast Flash programming read input PGMNOE (active low); PIO lines are 5 V-tolerant on this device. |
| 35 | PA5/PGMRDY | bidirectional | PIOA line 5 multiplexed with Fast Flash programming ready output PGMRDY (active high); PIO lines are 5 V-tolerant on this device. |
| 36 | PA4/PGMNCMD | bidirectional | PIOA line 4 multiplexed with Fast Flash programming command input PGMNCMD (active low); PIO lines are 5 V-tolerant on this device. |
| 37 | PA27/PGMD15 | bidirectional | PIOA line 27 multiplexed with Fast Flash programming data PGMD15; PIO lines are 5 V-tolerant on this device. |
| 38 | PA28 | bidirectional | PIOA line 28; PIO lines are 5 V-tolerant on this device. |
| 39 | NRST | input | External reset input, shaped by the reset controller, which also supplies reset source status. |
| 40 | TST | input | Test pin, which is part of the SAM-BA boot recovery procedure and requires a board power cycle when used that way. |
| 41 | PA29 | bidirectional | PIOA line 29; PIO lines are 5 V-tolerant on this device. |
| 42 | PA30 | bidirectional | PIOA line 30; PIO lines are 5 V-tolerant on this device. |
| 43 | PA3 | bidirectional | PIOA line 3; PIO lines are 5 V-tolerant on this device. |
| 44 | PA2/PGMEN2 | bidirectional | PIOA line 2 multiplexed with Fast Flash programming enable input PGMEN2; PIO lines are 5 V-tolerant on this device. |
| 45 | VDDIO | power_in | I/O and USB transceiver supply, 3.0 V to 3.6 V (3.3 V nominal) or 1.65 V to 1.95 V (1.8 V nominal). |
| 46 | GND | power_in | Ground; connect as short as possible to the system ground plane. |
| 47 | PA1/PGMEN1 | bidirectional | PIOA line 1 multiplexed with Fast Flash programming enable input PGMEN1; PIO lines are 5 V-tolerant on this device. |
| 48 | PA0/PGMEN0 | bidirectional | PIOA line 0 multiplexed with Fast Flash programming enable input PGMEN0; PIO lines are 5 V-tolerant on this device. |
| 49 | TDO | output | JTAG test data output for the IEEE 1149.1 boundary scan and ICE interface. |
| 50 | JTAGSEL | input | JTAG selection input shown in the block diagram; its functional limits are not given in this excerpt. |
| 51 | TMS | input | JTAG test mode select input for the IEEE 1149.1 boundary scan and ICE interface. |
| 52 | PA31 | bidirectional | PIOA line 31; PIO lines are 5 V-tolerant on this device. |
| 53 | TCK | input | JTAG test clock input for the IEEE 1149.1 boundary scan and ICE interface. |
| 54 | VDDCORE | power_in | Core logic supply, 1.65 V to 1.95 V (1.8 V typical). |
| 55 | ERASE | input | Erase input for the device; its function and limits are not given in this excerpt. |
| 56 | DDM | bidirectional | USB 2.0 Full Speed device D- data line on the on-chip transceiver. |
| 57 | DDP | bidirectional | USB 2.0 Full Speed device D+ data line on the on-chip transceiver (12 Mbit/s). |
| 58 | VDDIO | power_in | I/O and USB transceiver supply, 3.0 V to 3.6 V (3.3 V nominal) or 1.65 V to 1.95 V (1.8 V nominal). |
| 59 | VDDFLASH | power_in | Supplies part of the Flash, 3.0 V to 3.6 V (3.3 V nominal), and is required for correct Flash operation. |
| 60 | GND | power_in | Ground; connect as short as possible to the system ground plane. |
| 61 | XOUT | output | Crystal oscillator output of the 3 to 20 MHz on-chip oscillator. |
| 62 | XIN/PGMCK | input | Crystal oscillator input of the 3 to 20 MHz on-chip oscillator, also used as the Fast Flash programming clock input PGMCK. |
| 63 | PLLRC | passive | PLL connection from the block diagram; its required external network is not given in this excerpt. |
| 64 | VDDPLL | power_in | Supplies the oscillator and the PLL; it can be connected directly to VDDOUT. |
Key specifications
| Parameter | Value |
|---|---|
| Manufacturer | Microchip Tech |
| Package | LQFP-64(10x10) |
| Category | Embedded Processors & Controllers |
| Pins | 64 |
Electrical characteristics
Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).
| Parameter | Symbol | Min | Typ | Max | Unit | Conditions | Page |
|---|---|---|---|---|---|---|---|
| Operating temperature range (industrial) | -40 | 85 | °C | Green LQFP 64 package, industrial range | 47 | ||
| VDDIN supply voltage (voltage regulator and ADC) | VDDIN | 3 | 3.3 | 3.6 | V | 3.3 V nominal | 12 |
| VDDIO supply voltage (3.3 V range) | VDDIO | 3 | 3.3 | 3.6 | V | 3.3 V nominal range; below 3.0 V USB transceivers cannot be used | 12 |
| VDDIO supply voltage (1.8 V range) | VDDIO | 1.65 | 1.8 | 1.95 | V | 1.8 V nominal range | 12 |
| VDDFLASH supply voltage | VDDFLASH | 3 | 3.3 | 3.6 | V | 3.3 V nominal; powers part of the Flash | 12 |
| VDDCORE supply voltage | VDDCORE | 1.65 | 1.8 | 1.95 | V | Powers device logic, including embedded Flash | 12 |
| VDDCORE slope during startup | VDDCORE | 6 | V/ms | During startup | 12 | ||
| Fully static operating frequency | 55 | MHz | 1.65 V and 85 °C worst case conditions | 3 | |||
| Single-cycle Flash access frequency | 30 | MHz | Worst case conditions | 1 | |||
| RC oscillator frequency range | 22 | 42 | kHz | Low-power RC oscillator | 29 | ||
| Main oscillator frequency range | 3 | 20 | MHz | Main oscillator; can be bypassed | 29 | ||
| PLL output frequency range | 80 | 220 | MHz | PLL output | 29 | ||
| Brownout detector threshold accuracy | Vbot | -2 | 2 | % | Typical threshold 1.68 V, factory calibrated | 28 | |
| VDDCORE static current | 60 | µA | 25 °C; includes RC oscillator, voltage regulator and power-on reset | 12 | |||
| Brownout detector static current (enabled) | 20 | µA | Brownout detector enabled | 28 | |||
| Brownout detector static current (deactivated) | 1 | µA | Brownout detector deactivated via GPNVM bit 0 | 28 | |||
| VDDCORE dynamic power consumption | 50 | mA | Full speed, running out of Flash | 12 | |||
| VDDFLASH power consumption | 10 | mA | Full speed, running out of Flash | 12 | |||
| Voltage regulator static current (Normal Mode) | 100 | µA | Normal Mode | 12 | |||
| Voltage regulator output current (Normal Mode) | 100 | mA | Normal Mode | 12 | |||
| Voltage regulator static current (Low-power Mode) | 25 | µA | Low-power Mode | 12 | |||
| Voltage regulator output current (Low-power Mode) | 1 | mA | Low-power Mode | 12 | |||
| High-drive I/O current (PA0 to PA3) | 16 | mA | Each line, permanently | 14 | |||
| Standard I/O line current | 8 | mA | Remaining I/O lines | 14 | |||
| Total I/O line current | 150 | mA | Total drawn by all I/O lines | 14 | |||
| 5V-tolerant I/O maximum drive voltage | 5.5 | V | 5V-tolerant I/O lines, driven above VDDIO; pull-up enabled current path to VDDIO | 14 | |||
| Flash write endurance | 10000 | write cycles | 1 | ||||
| Flash data retention | 10 | years | 1 | ||||
| Brownout detector typical threshold | Vbot | 1.68 | V | Accuracy ±2%, factory calibrated | 28 | ||
| Brownout detector hysteresis | 50 | mV | About 50 mV | 28 | |||
| Power-on reset threshold | 1.5 | V | Limited-accuracy threshold, around 1.5 V | 28 | |||
| JTAGSEL internal pull-down resistor | 15 | kΩ | Permanent pull-down to GND, about 15 kΩ | 14 | |||
| TST internal pull-down resistor | 15 | kΩ | Permanent pull-down to GND, about 15 kΩ | 14 | |||
| ERASE internal pull-down resistor | 15 | kΩ | Permanent pull-down to GND, about 15 kΩ | 14 |
CAD (KiCad official)
- Symbol:
AT91SAM7S64C-AU - Footprint:
Package_QFP:LQFP-64_10x10mm_P0.5mm - 3D model: LQFP-64(10x10) (KiCad packages3D, STEP)
- 3D model files:
at91sam7s64c-au-etched.step/at91sam7s64c-au-etched.glbcarry the MPN laser-etched on the die in a toggleableAdom.LaserEtchgroup (Fusion-ready);at91sam7s64c-au.step/at91sam7s64c-au.glbare the bare package body.
Provenance
Data extracted from the manufacturer datasheet, not a distributor listing:
- Datasheet: Microchip Tech datasheet (50 pp, sha256
694a6ccac5320b6b, retrieved 2026-10-18, tier: lcsc) - Extractor: parts-factory
2.0.0/extract_pins 0.3, primaryclaude-haiku-5-5(text), consensusclaude-sonnet-5-5(agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish. - CAD: KiCad official libraries (CC-BY-SA 4.0).