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AT89S52-24PU
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Microchip Tech Microcontrollers (MCU/MPU/SOC), DIP-40. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.
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Symbol & Footprint
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README
markdownAT89S52-24PU
Microchip Tech · Microcontrollers (MCU/MPU/SOC) · DIP-40
AT89S52-24PU from Microchip Tech, in a DIP-40. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.
Pinout
| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | P1.0 (T2) | bidirectional | Port 1 bidirectional I/O with internal pull-ups that sinks/sources four TTL inputs; alternate function is the Timer/Counter 2 external count input (T2) and clock-out. |
| 2 | P1.1 | bidirectional | Port 1 bidirectional I/O with internal pull-ups that sinks/sources four TTL inputs; alternate function is the Timer/Counter 2 capture/reload trigger and direction control (T2EX). |
| 3 | P1.2 | bidirectional | Port 1 bidirectional I/O with internal pull-ups that sinks/sources four TTL inputs; receives low-order address bytes during Flash programming and verification. |
| 4 | P1.3 | bidirectional | Port 1 bidirectional I/O with internal pull-ups that sinks/sources four TTL inputs; receives low-order address bytes during Flash programming and verification. |
| 5 | P1.4 | bidirectional | Port 1 bidirectional I/O with internal pull-ups that sinks/sources four TTL inputs; receives low-order address bytes during Flash programming and verification. |
| 6 | P1.5 | bidirectional | Port 1 bidirectional I/O with internal pull-ups that sinks/sources four TTL inputs; alternate function MOSI is used for In-System Programming. |
| 7 | P1.6 | bidirectional | Port 1 bidirectional I/O with internal pull-ups that sinks/sources four TTL inputs; alternate function MISO is used for In-System Programming. |
| 8 | P1.7 | bidirectional | Port 1 bidirectional I/O with internal pull-ups that sinks/sources four TTL inputs; alternate function SCK is used for In-System Programming. |
| 9 | RST | input | Reset input; a high on this pin for two machine cycles while the oscillator is running resets the device. |
| 10 | P3.0 (RXD) | bidirectional | Port 3 bidirectional I/O with internal pull-ups that sinks/sources four TTL inputs; alternate function RXD is the serial input port. |
| 11 | P3.1 (TXD) | bidirectional | Port 3 bidirectional I/O with internal pull-ups that sinks/sources four TTL inputs; alternate function TXD is the serial output port. |
| 12 | P3.2 (INT0) | bidirectional | Port 3 bidirectional I/O with internal pull-ups that sinks/sources four TTL inputs; alternate function INT0 is external interrupt 0. |
| 13 | P3.3 (INT1) | bidirectional | Port 3 bidirectional I/O with internal pull-ups that sinks/sources four TTL inputs; alternate function INT1 is external interrupt 1. |
| 14 | P3.4 (T0) | bidirectional | Port 3 bidirectional I/O with internal pull-ups that sinks/sources four TTL inputs; alternate function T0 is the Timer 0 external input. |
| 15 | P3.5 (T1) | bidirectional | Port 3 bidirectional I/O with internal pull-ups that sinks/sources four TTL inputs; alternate function T1 is the Timer 1 external input. |
| 16 | P3.6 (WR) | bidirectional | Port 3 bidirectional I/O with internal pull-ups that sinks/sources four TTL inputs; alternate function WR is the external data memory write strobe. |
| 17 | P3.7 (RD) | bidirectional | Port 3 bidirectional I/O with internal pull-ups that sinks/sources four TTL inputs; alternate function RD is the external data memory read strobe. |
| 18 | XTAL2 | output | Oscillator pin XTAL2; the pages provided name this pin but do not state its electrical limits. |
| 19 | XTAL1 | input | Oscillator pin XTAL1; the pages provided name this pin but do not state its electrical limits. |
| 20 | GND | power_in | Ground reference for the device. |
| 21 | P2.0 (A8) | bidirectional | Port 2 bidirectional I/O with internal pull-ups that sinks/sources four TTL inputs; emits the high-order address byte (A8) during external program fetches and 16-bit external data accesses. |
| 22 | P2.1 (A9) | bidirectional | Port 2 bidirectional I/O with internal pull-ups that sinks/sources four TTL inputs; emits the high-order address byte (A9) during external program fetches and 16-bit external data accesses. |
| 23 | P2.2 (A10) | bidirectional | Port 2 bidirectional I/O with internal pull-ups that sinks/sources four TTL inputs; emits the high-order address byte (A10) during external program fetches and 16-bit external data accesses. |
| 24 | P2.3 (A11) | bidirectional | Port 2 bidirectional I/O with internal pull-ups that sinks/sources four TTL inputs; emits the high-order address byte (A11) during external program fetches and 16-bit external data accesses. |
| 25 | P2.4 (A12) | bidirectional | Port 2 bidirectional I/O with internal pull-ups that sinks/sources four TTL inputs; emits the high-order address byte (A12) during external program fetches and 16-bit external data accesses. |
| 26 | P2.5 (A13) | bidirectional | Port 2 bidirectional I/O with internal pull-ups that sinks/sources four TTL inputs; emits the high-order address byte (A13) during external program fetches and 16-bit external data accesses. |
| 27 | P2.6 (A14) | bidirectional | Port 2 bidirectional I/O with internal pull-ups that sinks/sources four TTL inputs; emits the high-order address byte (A14) during external program fetches and 16-bit external data accesses. |
| 28 | P2.7 (A15) | bidirectional | Port 2 bidirectional I/O with internal pull-ups that sinks/sources four TTL inputs; emits the high-order address byte (A15) during external program fetches and 16-bit external data accesses. |
| 29 | PSEN | output | Program store enable; the pages provided list this pin in the pinout but do not describe its timing or limits. |
| 30 | ALE/PROG | bidirectional | Address Latch Enable output pulses at 1/6 the oscillator frequency to latch the low address byte during external memory access, and is the program pulse input (PROG) during Flash programming. |
| 31 | EA/VPP | input | Shared EA/VPP pin; the pages provided name this pin but do not state its electrical limits or behavior. |
| 32 | P0.7 (AD7) | bidirectional | Port 0 open-drain bidirectional I/O that sinks eight TTL inputs; multiplexed as the low-order address/data bus (AD7) with internal pull-ups in that mode, and needs external pull-ups during program verification. |
| 33 | P0.6 (AD6) | bidirectional | Port 0 open-drain bidirectional I/O that sinks eight TTL inputs; multiplexed as the low-order address/data bus (AD6) with internal pull-ups in that mode, and needs external pull-ups during program verification. |
| 34 | P0.5 (AD5) | bidirectional | Port 0 open-drain bidirectional I/O that sinks eight TTL inputs; multiplexed as the low-order address/data bus (AD5) with internal pull-ups in that mode, and needs external pull-ups during program verification. |
| 35 | P0.4 (AD4) | bidirectional | Port 0 open-drain bidirectional I/O that sinks eight TTL inputs; multiplexed as the low-order address/data bus (AD4) with internal pull-ups in that mode, and needs external pull-ups during program verification. |
| 36 | P0.3 (AD3) | bidirectional | Port 0 open-drain bidirectional I/O that sinks eight TTL inputs; multiplexed as the low-order address/data bus (AD3) with internal pull-ups in that mode, and needs external pull-ups during program verification. |
| 37 | P0.2 (AD2) | bidirectional | Port 0 open-drain bidirectional I/O that sinks eight TTL inputs; multiplexed as the low-order address/data bus (AD2) with internal pull-ups in that mode, and needs external pull-ups during program verification. |
| 38 | P0.1 (AD1) | bidirectional | Port 0 open-drain bidirectional I/O that sinks eight TTL inputs; multiplexed as the low-order address/data bus (AD1) with internal pull-ups in that mode, and needs external pull-ups during program verification. |
| 39 | P0.0 (AD0) | bidirectional | Port 0 open-drain bidirectional I/O that sinks eight TTL inputs; multiplexed as the low-order address/data bus (AD0) with internal pull-ups in that mode, and needs external pull-ups during program verification. |
| 40 | VCC | power_in | Supply voltage; the ordering information specifies 4.0V to 5.5V for the 24 MHz -24PU part. |
Key specifications
| Parameter | Value |
|---|---|
| Manufacturer | Microchip Tech |
| Package | DIP-40 |
| Category | Embedded Processors & Controllers |
| Pins | 40 |
Electrical characteristics
Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).
| Parameter | Symbol | Min | Typ | Max | Unit | Conditions | Page |
|---|---|---|---|---|---|---|---|
| Operating Temperature | -55 | 125 | °C | 29 | |||
| Storage Temperature | -65 | 150 | °C | 29 | |||
| Voltage on Any Pin with Respect to Ground | -1 | 7 | V | 29 | |||
| Maximum Operating Voltage | 6.6 | V | 29 | ||||
| DC Output Current | 15 | mA | 29 | ||||
| Supply voltage (AT89S52-24 speed grade) | VCC | 4 | 5.5 | V | AT89S52-24PU ordering option (24 MHz, 4.0V to 5.5V) | 34 | |
| Operating temperature (Industrial) | -40 | 85 | °C | Industrial operation range | 34 | ||
| Maximum IOL per port pin | IOL | 10 | mA | Steady state (non-transient), note 1 | 29 | ||
| Maximum IOL per 8-bit port 0 | IOL | 26 | mA | Port 0, steady state, note 1 | 29 | ||
| Maximum IOL per 8-bit port 1, 2, 3 | IOL | 15 | mA | Ports 1, 2, 3, steady state, note 1 | 29 | ||
| Maximum total IOL for all output pins | IOL | 71 | mA | Steady state, note 1 | 29 | ||
| Minimum VCC for Power-down | VCC | 2 | V | Minimum VCC for Power-down (note 2) | 29 | ||
| Input Low Voltage (Except EA) | VIL | -0.5 | V | 29 | |||
| Input Low Voltage (EA) | VIL1 | -0.5 | V | 29 | |||
| Output Low Voltage (Ports 1,2,3) | VOL | 0.45 | V | IOL = 1.6 mA | 29 | ||
| Output Low Voltage (Port 0, ALE, PSEN) | VOL1 | 0.45 | V | IOL = 3.2 mA | 29 | ||
| Output High Voltage (Ports 1,2,3, ALE, PSEN) | VOH | 2.4 | V | IOH = -60 µA, VCC = 5V ± 10% | 29 | ||
| Output High Voltage (Port 0 in External Bus Mode) | VOH1 | 2.4 | V | IOH = -800 µA, VCC = 5V ± 10% | 29 | ||
| Logical 0 Input Current (Ports 1,2,3) | IIL | -50 | µA | VIN = 0.45V | 29 | ||
| Logical 1 to 0 Transition Current (Ports 1,2,3) | ITL | -300 | µA | VIN = 2V, VCC = 5V ± 10% | 29 | ||
| Input Leakage Current (Port 0, EA) | ILI | -10 | 10 | µA | 0.45 < VIN < VCC | 29 | |
| Reset Pulldown Resistor | RRST | 50 | 300 | KΩ | 29 | ||
| Pin Capacitance | CIO | 10 | pF | Test Freq. = 1 MHz, TA = 25°C | 29 | ||
| Power Supply Current, Active Mode | ICC | 25 | mA | Active Mode, 12 MHz | 29 | ||
| Power Supply Current, Idle Mode | ICC | 6.5 | mA | Idle Mode, 12 MHz | 29 | ||
| Power Supply Current, Power-down Mode | ICC | 50 | µA | VCC = 5.5V | 29 | ||
| Oscillator Frequency (variable oscillator) | 1/tCLCL | 0 | 33 | MHz | 30 | ||
| PSEN Low to Address Float | tPLAZ | 10 | ns | 30 | |||
| Input Instruction Hold After PSEN | tPXIX | 0 | ns | 30 | |||
| Data Hold After RD | tRHDX | 0 | ns | 30 | |||
| RD Low to Address Float | tRLAZ | 0 | ns | 30 | |||
| Input Data Hold After Clock Rising Edge (shift register mode) | tXHDX | 0 | ns | Variable oscillator, load 80 pF | 31 | ||
| Oscillator Frequency (serial programming) | 1/tCLCL | 3 | 33 | MHz | TA = -40°C to 85°C, VCC = 4.0-5.5V | 28 | |
| Oscillator Period | tCLCL | 30 | ns | TA = -40°C to 85°C, VCC = 4.0-5.5V | 28 | ||
| Serial Data Low to MISO Valid | tSLIV | 10 | 16 | 32 | ns | TA = -40°C to 85°C, VCC = 4.0-5.5V | 28 |
| Chip Erase Instruction Cycle Time | tERASE | 500 | ms | TA = -40°C to 85°C, VCC = 4.0-5.5V | 28 | ||
| Programming Supply Voltage | VPP | 11.5 | 12.5 | V | TA = 20°C to 30°C, VCC = 4.5 to 5.5V | 25 | |
| Programming Supply Current | IPP | 10 | mA | TA = 20°C to 30°C, VCC = 4.5 to 5.5V | 25 | ||
| VCC Supply Current (parallel programming) | ICC | 30 | mA | TA = 20°C to 30°C, VCC = 4.5 to 5.5V | 25 | ||
| Oscillator Frequency (parallel programming) | 1/tCLCL | 3 | 33 | MHz | TA = 20°C to 30°C, VCC = 4.5 to 5.5V | 25 | |
| VPP Setup to PROG Low | tSHGL | 10 | µs | TA = 20°C to 30°C, VCC = 4.5 to 5.5V | 25 | ||
| VPP Hold After PROG | tGHSL | 10 | µs | TA = 20°C to 30°C, VCC = 4.5 to 5.5V | 25 | ||
| PROG Width | tGLGH | 0.2 | 1 | µs | TA = 20°C to 30°C, VCC = 4.5 to 5.5V | 25 | |
| PROG High to BUSY Low | tGHBL | 1 | µs | TA = 20°C to 30°C, VCC = 4.5 to 5.5V | 25 | ||
| Byte Write Cycle Time | tWC | 50 | µs | TA = 20°C to 30°C, VCC = 4.5 to 5.5V | 25 |
CAD (KiCad official)
- Symbol:
AT89S52-24PU - Footprint:
Package_DIP:DIP-40_W25.4mm - 3D model: DIP-40 (KiCad packages3D, STEP)
- 3D model files:
at89s52-24pu-etched.step/at89s52-24pu-etched.glbcarry the MPN laser-etched on the die in a toggleableAdom.LaserEtchgroup (Fusion-ready);at89s52-24pu.step/at89s52-24pu.glbare the bare package body.
Provenance
Data extracted from the manufacturer datasheet, not a distributor listing:
- Datasheet: Microchip Tech datasheet (38 pp, sha256
6f1fe5ec41885436, retrieved 2026-10-19, tier: lcsc) - Extractor: parts-factory
2.0.0/extract_pins 0.3, primaryclaude-haiku-5-5(text), consensusclaude-sonnet-5-5(agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish. - CAD: KiCad official libraries (CC-BY-SA 4.0).