# AT89S52-24AUR

**Microchip Tech** · MICROCHIP · TQFP-44(10x10)

AT89S52-24AUR from Microchip Tech, in a TQFP-44(10x10). Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

## Pinout

| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | P1.5 (MOSI) | bidirectional | Port 1 bit 5 with internal pull-ups; alternate function MOSI is used for In-System Programming. |
| 2 | P1.6 (MISO) | bidirectional | Port 1 bit 6 with internal pull-ups; alternate function MISO is used for In-System Programming. |
| 3 | P1.7 (SCK) | bidirectional | Port 1 bit 7 with internal pull-ups; alternate function SCK is used for In-System Programming. |
| 4 | RST | input | Reset input; a high on this pin for two machine cycles while the oscillator is running resets the device. |
| 5 | P3.0 (RXD) | bidirectional | Port 3 bit 0 with internal pull-ups; alternate function RXD is the serial input port. |
| 6 | NC | unconnected | No internal connection on this pin; leave unconnected. |
| 7 | P3.1 (TXD) | bidirectional | Port 3 bit 1 with internal pull-ups; alternate function TXD is the serial output port. |
| 8 | P3.2 (INT0) | bidirectional | Port 3 bit 2 with internal pull-ups; alternate function INT0 is external interrupt 0. |
| 9 | P3.3 (INT1) | bidirectional | Port 3 bit 3 with internal pull-ups; alternate function INT1 is external interrupt 1. |
| 10 | P3.4 (T0) | bidirectional | Port 3 bit 4 with internal pull-ups; alternate function T0 is the timer 0 external input. |
| 11 | P3.5 (T1) | bidirectional | Port 3 bit 5 with internal pull-ups; alternate function T1 is the timer 1 external input. |
| 12 | P3.6 (WR) | bidirectional | Port 3 bit 6 with internal pull-ups; alternate function WR is the external data memory write strobe. |
| 13 | P3.7 (RD) | bidirectional | Port 3 bit 7 with internal pull-ups; alternate function RD is the external data memory read strobe. |
| 14 | XTAL2 | output | Output of the on-chip oscillator circuit, connected to the external crystal. |
| 15 | XTAL1 | input | Input to the on-chip oscillator circuit, connected to the external crystal. |
| 16 | GND | power_in | Ground. |
| 17 | GND | power_in | Ground. |
| 18 | P2.0 (A8) | bidirectional | Port 2 bit 0 with internal pull-ups; emits the high-order address byte A8 during external memory accesses. |
| 19 | P2.1 (A9) | bidirectional | Port 2 bit 1 with internal pull-ups; emits the high-order address byte A9 during external memory accesses. |
| 20 | P2.2 (A10) | bidirectional | Port 2 bit 2 with internal pull-ups; emits the high-order address byte A10 during external memory accesses. |
| 21 | P2.3 (A11) | bidirectional | Port 2 bit 3 with internal pull-ups; emits the high-order address byte A11 during external memory accesses. |
| 22 | P2.4 (A12) | bidirectional | Port 2 bit 4 with internal pull-ups; emits the high-order address byte A12 during external memory accesses. |
| 23 | P2.5 (A13) | bidirectional | Port 2 bit 5 with internal pull-ups; emits the high-order address byte A13 during external memory accesses. |
| 24 | P2.6 (A14) | bidirectional | Port 2 bit 6 with internal pull-ups; emits the high-order address byte A14 during external memory accesses. |
| 25 | P2.7 (A15) | bidirectional | Port 2 bit 7 with internal pull-ups; emits the high-order address byte A15 during external memory accesses. |
| 26 | PSEN | output | Program store enable strobe for external program memory. |
| 27 | ALE/PROG | bidirectional | Address latch enable output at 1/6 of the oscillator frequency; program pulse input during Flash programming. |
| 28 | NC | unconnected | No internal connection on this pin; leave unconnected. |
| 29 | EA/VPP | input | External access enable and programming voltage input for Flash programming. |
| 30 | P0.7 (AD7) | bidirectional | Port 0 bit 7, open-drain; multiplexed low-order address/data bus during external memory access, and needs external pull-ups during program verification. |
| 31 | P0.6 (AD6) | bidirectional | Port 0 bit 6, open-drain; multiplexed low-order address/data bus during external memory access, and needs external pull-ups during program verification. |
| 32 | P0.5 (AD5) | bidirectional | Port 0 bit 5, open-drain; multiplexed low-order address/data bus during external memory access, and needs external pull-ups during program verification. |
| 33 | P0.4 (AD4) | bidirectional | Port 0 bit 4, open-drain; multiplexed low-order address/data bus during external memory access, and needs external pull-ups during program verification. |
| 34 | P0.3 (AD3) | bidirectional | Port 0 bit 3, open-drain; multiplexed low-order address/data bus during external memory access, and needs external pull-ups during program verification. |
| 35 | P0.2 (AD2) | bidirectional | Port 0 bit 2, open-drain; multiplexed low-order address/data bus during external memory access, and needs external pull-ups during program verification. |
| 36 | P0.1 (AD1) | bidirectional | Port 0 bit 1, open-drain; multiplexed low-order address/data bus during external memory access, and needs external pull-ups during program verification. |
| 37 | P0.0 (AD0) | bidirectional | Port 0 bit 0, open-drain; multiplexed low-order address/data bus during external memory access, and needs external pull-ups during program verification. |
| 38 | VCC | power_in | Supply voltage; operating range 4.0V to 5.5V for the -24 speed grade. |
| 39 | NC | unconnected | No internal connection on this pin; leave unconnected. |
| 40 | P1.0 (T2) | bidirectional | Port 1 bit 0 with internal pull-ups; alternate function T2 is the external count input to Timer/Counter 2. |
| 41 | P1.1 (T2 EX) | bidirectional | Port 1 bit 1 with internal pull-ups; alternate function T2EX is the Timer/Counter 2 capture/reload trigger and direction control. |
| 42 | P1.2 | bidirectional | Port 1 bit 2 general-purpose I/O with internal pull-ups. |
| 43 | P1.3 | bidirectional | Port 1 bit 3 general-purpose I/O with internal pull-ups. |
| 44 | P1.4 | bidirectional | Port 1 bit 4 general-purpose I/O with internal pull-ups. |

## Key specifications

| Parameter | Value |
|---|---|
| Manufacturer | Microchip Tech |
| Package | TQFP-44(10x10) |
| Category | Embedded Processors & Controllers |
| Pins | 44 |

## CAD (KiCad official)

- Symbol: `AT89S52-24AUR`
- Footprint: `Package_QFP:TQFP-44_10x10mm_P0.8mm`
- 3D model: TQFP-44(10x10) (KiCad packages3D, STEP)
- 3D model files: `at89s52-24aur-etched.step` / `at89s52-24aur-etched.glb` carry the MPN laser-etched on the die in a toggleable `Adom.LaserEtch` group (Fusion-ready); `at89s52-24aur.step` / `at89s52-24aur.glb` are the bare package body.

## Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

- **Datasheet:** [Microchip Tech datasheet](docs/at89s52-24aur-datasheet.pdf) (38 pp, sha256 `944094fe7c814eeb`, retrieved 2026-10-30, tier: manufacturer)
- **Extractor:** parts-factory `2.0.0` / `extract_pins 0.3`, primary `claude-haiku-5-5` (text), consensus `claude-sonnet-5-5` (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
- **CAD:** KiCad official libraries (CC-BY-SA 4.0).

[Datasheet PDF](docs/at89s52-24aur-datasheet.pdf)