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AT89S52-24AU

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Microchip Tech Microcontrollers (MCU/MPU/SOC), TQFP-44(10x10). Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.

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AT89S52-24AU

Microchip Tech · Microcontrollers (MCU/MPU/SOC) · TQFP-44(10x10)

AT89S52-24AU from Microchip Tech, in a TQFP-44(10x10). Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 P1.5 bidirectional Port 1 bit 5 with internal pull-ups; also serves as MOSI for In-System Programming.
2 P1.6 bidirectional Port 1 bit 6 with internal pull-ups; also serves as MISO for In-System Programming.
3 P1.7 bidirectional Port 1 bit 7 with internal pull-ups; also serves as SCK for In-System Programming.
4 RST input Reset input; a high for two machine cycles while the oscillator runs resets the device, and the pin is driven high for 98 oscillator periods after a Watchdog timeout unless DISRTO is set.
5 P3.0 bidirectional Port 3 bit 0 with internal pull-ups; serial data input of the UART.
6 NC unconnected Not connected; no internal connection to the die as marked on the pin diagram.
7 P3.1 bidirectional Port 3 bit 1 with internal pull-ups; serial data output of the UART.
8 P3.2 bidirectional Port 3 bit 2 with internal pull-ups; external interrupt 0 input.
9 P3.3 bidirectional Port 3 bit 3 with internal pull-ups; external interrupt 1 input.
10 P3.4 bidirectional Port 3 bit 4 with internal pull-ups; external input to Timer/Counter 0.
11 P3.5 bidirectional Port 3 bit 5 with internal pull-ups; external input to Timer/Counter 1.
12 P3.6 bidirectional Port 3 bit 6 with internal pull-ups; external data memory write strobe.
13 P3.7 bidirectional Port 3 bit 7 with internal pull-ups; external data memory read strobe.
14 XTAL2 output Crystal oscillator output pin; the provided pages show the pin label but no electrical limits.
15 XTAL1 input Crystal oscillator input pin; the provided pages show the pin label but no electrical limits.
16 GND power_in Ground.
17 GND power_in Ground.
18 P2.0 (A8) bidirectional Port 2 bit 0 with internal pull-ups; emits the high-order address byte during external program fetches and 16-bit MOVX accesses.
19 P2.1 (A9) bidirectional Port 2 bit 1 with internal pull-ups; emits the high-order address byte during external program fetches and 16-bit MOVX accesses.
20 P2.2 (A10) bidirectional Port 2 bit 2 with internal pull-ups; emits the high-order address byte during external program fetches and 16-bit MOVX accesses.
21 P2.3 (A11) bidirectional Port 2 bit 3 with internal pull-ups; emits the high-order address byte during external program fetches and 16-bit MOVX accesses.
22 P2.4 (A12) bidirectional Port 2 bit 4 with internal pull-ups; emits the high-order address byte during external program fetches and 16-bit MOVX accesses.
23 P2.5 (A13) bidirectional Port 2 bit 5 with internal pull-ups; emits the high-order address byte during external program fetches and 16-bit MOVX accesses.
24 P2.6 (A14) bidirectional Port 2 bit 6 with internal pull-ups; emits the high-order address byte during external program fetches and 16-bit MOVX accesses.
25 P2.7 (A15) bidirectional Port 2 bit 7 with internal pull-ups; emits the high-order address byte during external program fetches and 16-bit MOVX accesses.
26 PSEN output Program store enable output; the provided pages list the pin but do not state its timing or limits.
27 ALE/PROG bidirectional Address Latch Enable output pulse at 1/6 the oscillator frequency for latching the low address byte; serves as the program pulse input (PROG) during Flash programming.
28 NC unconnected Not connected; no internal connection as marked on the pin diagram.
29 EA/VPP input External access enable/programming voltage pin as labelled on the pin diagram; the provided pages do not state its logic levels or limits.
30 P0.7 (AD7) bidirectional Open-drain bidirectional Port 0 bit 7; can sink eight TTL inputs and is the multiplexed address/data bus during external memory access, with external pull-ups required for program verification.
31 P0.6 (AD6) bidirectional Open-drain bidirectional Port 0 bit 6; can sink eight TTL inputs and is the multiplexed address/data bus during external memory access, with external pull-ups required for program verification.
32 P0.5 (AD5) bidirectional Open-drain bidirectional Port 0 bit 5; can sink eight TTL inputs and is the multiplexed address/data bus during external memory access, with external pull-ups required for program verification.
33 P0.4 (AD4) bidirectional Open-drain bidirectional Port 0 bit 4; can sink eight TTL inputs and is the multiplexed address/data bus during external memory access, with external pull-ups required for program verification.
34 P0.3 (AD3) bidirectional Open-drain bidirectional Port 0 bit 3; can sink eight TTL inputs and is the multiplexed address/data bus during external memory access, with external pull-ups required for program verification.
35 P0.2 (AD2) bidirectional Open-drain bidirectional Port 0 bit 2; can sink eight TTL inputs and is the multiplexed address/data bus during external memory access, with external pull-ups required for program verification.
36 P0.1 (AD1) bidirectional Open-drain bidirectional Port 0 bit 1; can sink eight TTL inputs and is the multiplexed address/data bus during external memory access, with external pull-ups required for program verification.
37 P0.0 (AD0) bidirectional Open-drain bidirectional Port 0 bit 0; can sink eight TTL inputs and is the multiplexed address/data bus during external memory access, with external pull-ups required for program verification.
38 VCC power_in Supply voltage; 4.0V to 5.5V for the -24 speed grade per the ordering information.
39 NC unconnected Not connected; no internal connection as marked on the pin diagram.
40 P1.0 (T2) bidirectional Port 1 bit 0 with internal pull-ups; external count input to Timer/Counter 2 and clock-out.
41 P1.1 bidirectional Port 1 bit 1 with internal pull-ups; Timer/Counter 2 capture/reload trigger and direction control input.
42 P1.2 bidirectional General-purpose Port 1 bit 2 with internal pull-ups; output buffers sink/source four TTL inputs.
43 P1.3 bidirectional General-purpose Port 1 bit 3 with internal pull-ups; output buffers sink/source four TTL inputs.
44 P1.4 bidirectional General-purpose Port 1 bit 4 with internal pull-ups; output buffers sink/source four TTL inputs.

Key specifications

Parameter Value
Manufacturer Microchip Tech
Package TQFP-44(10x10)
Category Embedded Processors & Controllers
Pins 44

Electrical characteristics

Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).

Parameter Symbol Min Typ Max Unit Conditions Page
Input Low Voltage (Except EA) VIL -0.5 V TA = -40°C to 85°C, VCC = 4.0V to 5.5V 29
Input Low Voltage (EA) VIL1 -0.5 V TA = -40°C to 85°C, VCC = 4.0V to 5.5V 29
Output Low Voltage (Ports 1,2,3) VOL 0.45 V IOL = 1.6 mA 29
Output Low Voltage (Port 0, ALE, PSEN) VOL1 0.45 V IOL = 3.2 mA 29
Output High Voltage (Ports 1,2,3, ALE, PSEN) VOH 2.4 V IOH = -60 µA, VCC = 5V ± 10% 29
Output High Voltage (Port 0 in External Bus Mode) VOH1 2.4 V IOH = -800 µA, VCC = 5V ± 10% 29
Logical 0 Input Current (Ports 1,2,3) IIL -50 µA VIN = 0.45V 29
Logical 1 to 0 Transition Current (Ports 1,2,3) ITL -300 µA VIN = 2V, VCC = 5V ± 10% 29
Input Leakage Current (Port 0, EA) ILI -10 10 µA 0.45 < VIN < VCC 29
Reset Pulldown Resistor RRST 50 300 KΩ 29
Pin Capacitance CIO 10 pF Test Freq. = 1 MHz, TA = 25°C 29
Power Supply Current, Active Mode ICC 25 mA Active Mode, 12 MHz 29
Power Supply Current, Idle Mode ICC 6.5 mA Idle Mode, 12 MHz 29
Power Supply Current, Power-down Mode ICC 50 µA VCC = 5.5V 29
Operating Temperature -55 125 °C 29
Storage Temperature -65 150 °C 29
Voltage on Any Pin with Respect to Ground -1 7 V 29
Maximum Operating Voltage 6.6 V 29
DC Output Current 15 mA 29
Supply Voltage (24 MHz speed grade) VCC 4 5.5 V Ordering info: speed 24 MHz, 4.0V to 5.5V 34
Operating Temperature (Industrial) -40 85 °C Industrial operation range 34
Oscillator Frequency (Serial Programming) 1/tCLCL 3 33 MHz TA = -40°C to 85°C, VCC = 4.0-5.5V 28
Oscillator Period tCLCL 30 ns TA = -40°C to 85°C, VCC = 4.0-5.5V 28
SCK Low to MISO Valid tSLIV 10 16 32 ns TA = -40°C to 85°C, VCC = 4.0-5.5V 28
Chip Erase Instruction Cycle Time tERASE 500 ms TA = -40°C to 85°C, VCC = 4.0-5.5V 28
Programming Supply Voltage VPP 11.5 12.5 V TA = 20°C to 30°C, VCC = 4.5 to 5.5V 25
Programming Supply Current IPP 10 mA TA = 20°C to 30°C, VCC = 4.5 to 5.5V 25
VCC Supply Current (Programming) ICC 30 mA TA = 20°C to 30°C, VCC = 4.5 to 5.5V 25
Oscillator Frequency (Parallel Programming) 1/tCLCL 3 33 MHz TA = 20°C to 30°C, VCC = 4.5 to 5.5V 25
VPP Setup to PROG Low tSHGL 10 µs TA = 20°C to 30°C, VCC = 4.5 to 5.5V 25
VPP Hold After PROG tGHSL 10 µs TA = 20°C to 30°C, VCC = 4.5 to 5.5V 25
PROG Width tGLGH 0.2 1 µs TA = 20°C to 30°C, VCC = 4.5 to 5.5V 25
ALE Pulse Width tLHLL 127 ns 12 MHz oscillator 30
Address Valid to ALE Low tAVLL 43 ns 12 MHz oscillator 30
Address Hold After ALE Low tLLAX 48 ns 12 MHz oscillator 30
ALE Low to Valid Instruction In tLLIV 233 ns 12 MHz oscillator 30
ALE Low to PSEN Low tLLPL 43 ns 12 MHz oscillator 30
PSEN Pulse Width tPLPH 205 ns 12 MHz oscillator 30
PSEN Low to Valid Instruction In tPLIV 145 ns 12 MHz oscillator 30
Input Instruction Float After PSEN tPXIZ 59 ns 12 MHz oscillator 30
PSEN to Address Valid tPXAV 75 ns 12 MHz oscillator 30
Address to Valid Instruction In tAVIV 312 ns 12 MHz oscillator 30
RD Pulse Width tRLRH 400 ns 12 MHz oscillator 30
WR Pulse Width tWLWH 400 ns 12 MHz oscillator 30
RD Low to Valid Data In tRLDV 252 ns 12 MHz oscillator 30
Data Float After RD tRHDZ 97 ns 12 MHz oscillator 30
ALE Low to Valid Data In tLLDV 517 ns 12 MHz oscillator 30
Address to Valid Data In tAVDV 585 ns 12 MHz oscillator 30
ALE Low to RD or WR Low tLLWL 200 300 ns 12 MHz oscillator 30
Address to RD or WR Low tAVWL 203 ns 12 MHz oscillator 30
Data Valid to WR Transition tQVWX 23 ns 12 MHz oscillator 30
Data Valid to WR High tQVWH 433 ns 12 MHz oscillator 30
Data Hold After WR tWHQX 33 ns 12 MHz oscillator 30
RD or WR High to ALE High tWHLH 43 123 ns 12 MHz oscillator 30
Serial Port Clock Cycle Time tXLXL 1 µs 12 MHz Osc; VCC = 4.0V to 5.5V, Load Capacitance = 80 pF 33
Output Data Setup to Clock Rising Edge tQVXH 700 ns 12 MHz Osc; VCC = 4.0V to 5.5V, Load Capacitance = 80 pF 33
Output Data Hold After Clock Rising Edge tXHQX 50 ns 12 MHz Osc; VCC = 4.0V to 5.5V, Load Capacitance = 80 pF 33
Clock Rising Edge to Input Data Valid tXHDV 700 ns 12 MHz Osc; VCC = 4.0V to 5.5V, Load Capacitance = 80 pF 33

CAD (KiCad official)

  • Symbol: AT89S52-24AU
  • Footprint: Package_QFP:TQFP-44_10x10mm_P0.8mm
  • 3D model: TQFP-44(10x10) (KiCad packages3D, STEP)
  • 3D model files: at89s52-24au-etched.step / at89s52-24au-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); at89s52-24au.step / at89s52-24au.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: Microchip Tech datasheet (38 pp, sha256 6f1fe5ec41885436, retrieved 2026-10-18, tier: lcsc)
  • Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-haiku-5-5 (text), consensus claude-sonnet-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF