# AT89LP51ED2-20AU

**Microchip Tech** · Pre-ordered MCUs · TQFP-44(10x10)

AT89LP51ED2-20AU from Microchip Tech, in a TQFP-44(10x10). Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

## Pinout

| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | P1.5 | bidirectional | Port 1 bit 5 configurable I/O, with MISO (SPI master-in/slave-out), MOSI in remap mode (input during ISP), and CEX2 (PCA module 2 capture/compare). |
| 2 | P1.6 | bidirectional | Port 1 bit 6 configurable I/O, with SCK (SPI clock), MISO in remap mode (output during ISP), and CEX3 (PCA module 3 capture/compare). |
| 3 | P1.7 | bidirectional | Port 1 bit 7 configurable I/O, with MOSI (SPI master-out/slave-in), SCK in remap mode (input during ISP), and CEX4 (PCA module 4 capture/compare). |
| 4 | RST | bidirectional | External reset input with polarity set by the POL pin, can output a pulse on watchdog reset or POR, and doubles as DCL serial debug clock input when OCD is enabled. |
| 5 | P3.0 | bidirectional | Port 3 bit 0 configurable I/O, also RXD serial port receiver input. |
| 6 | P4.1 | bidirectional | Port 4 bit 1 configurable I/O, also SDA TWI bidirectional serial data line. |
| 7 | P3.1 | bidirectional | Port 3 bit 1 configurable I/O, also TXD serial port transmitter output. |
| 8 | P3.2 | bidirectional | Port 3 bit 2 configurable I/O, also INT0 external interrupt 0 or Timer 0 gate input. |
| 9 | P3.3 | bidirectional | Port 3 bit 3 configurable I/O, also INT1 external interrupt 1 or Timer 1 gate input. |
| 10 | P3.4 | bidirectional | Port 3 bit 4 configurable I/O, also T0 Timer/Counter 0 external input or output. |
| 11 | P3.5 | bidirectional | Port 3 bit 5 configurable I/O, also T1 Timer/Counter 1 external input or output. |
| 12 | P3.6 | bidirectional | Port 3 bit 6 configurable I/O, also WR external memory write strobe (active-low). |
| 13 | P3.7 | bidirectional | Port 3 bit 7 configurable I/O, also RD external memory read strobe (active-low). |
| 14 | P4.7 | bidirectional | Port 4 bit 7 configurable I/O, also XTAL2A oscillator A amplifier output; usable as a port pin if internal RC oscillator or external clock is selected. |
| 15 | P4.6 | bidirectional | Port 4 bit 6 configurable I/O, also XTAL1A oscillator A amplifier input and clock generation input; usable as a port pin if internal RC oscillator is selected. |
| 16 | GND | power_in | Ground. |
| 17 | P4.3 | bidirectional | Port 4 bit 3 configurable I/O, also DDA bidirectional debug data line when OCD is enabled. |
| 18 | P2.0 | bidirectional | Port 2 bit 0 configurable I/O, also A8 external memory address bit 8. |
| 19 | P2.1 | bidirectional | Port 2 bit 1 configurable I/O, also A9 external memory address bit 9. |
| 20 | P2.2 | bidirectional | Port 2 bit 2 configurable I/O, with DA- DAC negative differential output and A10 external memory address bit 10. |
| 21 | P2.3 | bidirectional | Port 2 bit 3 configurable I/O, with DA+ DAC positive differential output and A11 external memory address bit 11. |
| 22 | P2.4 | bidirectional | Port 2 bit 4 configurable I/O, with AIN0 analog comparator input 0 and A12 external memory address bit 12. |
| 23 | P2.5 | bidirectional | Port 2 bit 5 configurable I/O, with AIN1 analog comparator input 1 and A13 external memory address bit 13. |
| 24 | P2.6 | bidirectional | Port 2 bit 6 configurable I/O, with AIN2 analog comparator input 2 and A14 external memory address bit 14. |
| 25 | P2.7 | bidirectional | Port 2 bit 7 configurable I/O, with AIN3 analog comparator input 3 and A15 external memory address bit 15. |
| 26 | P4.5 | bidirectional | Port 4 bit 5 configurable I/O, also PSEN external memory program store enable (active-low). |
| 27 | P4.4 | bidirectional | Port 4 bit 4 configurable I/O, also ALE external memory address latch enable. |
| 28 | P4.0 | bidirectional | Port 4 bit 0 configurable I/O, also SCL TWI serial clock (output in master mode, input in slave mode). |
| 29 | POL | input | Reset polarity select: high makes RST active high with pull-down, low makes RST active low with pull-up. |
| 30 | P0.7 | bidirectional | Port 0 bit 7 configurable I/O, also AD7 external memory address/data bit 7. |
| 31 | P0.6 | bidirectional | Port 0 bit 6 configurable I/O, with AD6 external memory address/data bit 6 and ADC6 analog input. |
| 32 | P0.5 | bidirectional | Port 0 bit 5 configurable I/O, with AD5 external memory address/data bit 5 and ADC5 analog input. |
| 33 | P0.4 | bidirectional | Port 0 bit 4 configurable I/O, with AD4 external memory address/data bit 4 and ADC4 analog input. |
| 34 | P0.3 | bidirectional | Port 0 bit 3 configurable I/O, with AD3 external memory address/data bit 3 and ADC3 analog input. |
| 35 | P0.2 | bidirectional | Port 0 bit 2 configurable I/O, with AD2 external memory address/data bit 2 and ADC2 analog input. |
| 36 | P0.1 | bidirectional | Port 0 bit 1 configurable I/O, with AD1 external memory address/data bit 1 and ADC1 analog input. |
| 37 | P0.0 | bidirectional | Port 0 bit 0 configurable I/O, with AD0 external memory address/data bit 0 and ADC0 analog input. |
| 38 | VDD | power_in | Supply voltage, 2.4V to 5.5V operating range. |
| 39 | P4.2 | bidirectional | Port 4 bit 2 configurable I/O, also XTAL2B low-frequency oscillator B amplifier output (AT89LP51ID2 only). |
| 40 | P1.0 | bidirectional | Port 1 bit 0 configurable I/O, with T2 Timer 2 external input or clock output and XTAL1B low-frequency oscillator B input. |
| 41 | P1.1 | bidirectional | Port 1 bit 1 configurable I/O, with T2EX Timer 2 external capture/reload input and SS SPI slave-select. |
| 42 | P1.2 | bidirectional | Port 1 bit 2 configurable I/O (ECI per pinout figure). |
| 43 | P1.3 | bidirectional | Port 1 bit 3 configurable I/O, also CEX0 PCA module 0 capture/compare external I/O. |
| 44 | P1.4 | bidirectional | Port 1 bit 4 configurable I/O, with SS SPI slave-select in remap mode (input for ISP) and CEX1 PCA module 1 capture/compare I/O. |

## Key specifications

| Parameter | Value |
|---|---|
| Manufacturer | Microchip Tech |
| Package | TQFP-44(10x10) |
| Category | Embedded Processors & Controllers |
| Pins | 44 |

## Electrical characteristics

Limits as printed in the datasheet (page.json `metadata.characteristics` carries them as data).

| Parameter | Symbol | Min | Typ | Max | Unit | Conditions | Page |
|---|---|---|---|---|---|---|---|
| VCC supply voltage range | VCC | 2.4 |  | 5.5 | V |  | 1 |
| Operating temperature range (industrial) |  | -40 |  | 85 | °C |  | 1 |
| Operating frequency, single-cycle |  | 0 |  | 20 | MHz | Single-cycle, 2.4V-5.5V | 1 |

## CAD (KiCad official)

- Symbol: `AT89LP51ED2-20AU`
- Footprint: `Package_QFP:TQFP-44_10x10mm_P0.8mm`
- 3D model: TQFP-44(10x10) (KiCad packages3D, STEP)
- 3D model files: `at89lp51ed2-20au-etched.step` / `at89lp51ed2-20au-etched.glb` carry the MPN laser-etched on the die in a toggleable `Adom.LaserEtch` group (Fusion-ready); `at89lp51ed2-20au.step` / `at89lp51ed2-20au.glb` are the bare package body.

## Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

- **Datasheet:** [Microchip Tech datasheet](docs/at89lp51ed2-20au-datasheet.pdf) (26 pp, sha256 `3c04a18eb05a6e48`, retrieved 2026-10-31, tier: lcsc)
- **Extractor:** parts-factory `2.0.0` / `extract_pins 0.3`, primary `claude-haiku-5-5` (text), consensus `claude-sonnet-5-5` (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
- **CAD:** KiCad official libraries (CC-BY-SA 4.0).

[Datasheet PDF](docs/at89lp51ed2-20au-datasheet.pdf)