component
AT88RF1354-ZU
Public Made by Adomby adom
Microchip Tech Pre-ordered MCUs, QFN-36-EP(6x6). Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.
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AT88RF1354-ZU
Microchip Tech · Pre-ordered MCUs · QFN-36-EP(6x6)
AT88RF1354-ZU from Microchip Tech, in a QFN-36-EP(6x6). Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.
Pinout
| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | VCC_ANT | power_in | Antenna supply voltage powering the transmitter and antenna drive circuits; requires 15 nF (within 3 mm) and 2.2 uF (within 5 mm) bypass capacitors to VSS_ANT. |
| 2 | VSS_ANT | power_in | Antenna ground, high current return path for transmitter and antenna drive circuit; connect to VSS at only a single point. |
| 3 | ANT | output | Antenna driver output generating the 13.56 MHz carrier, shaped into a sine wave by external passive circuitry. |
| 4 | Xtal1 | passive | Crystal pin 1; a 13.56 MHz crystal is connected between Xtal1 and Xtal2. |
| 5 | Xtal2 | passive | Crystal pin 2; a 13.56 MHz crystal is connected between Xtal1 and Xtal2. |
| 6 | C5 | passive | Bypass capacitor pin requiring 0.33 uF to VSS for the digital circuits, placed within 3 mm of the package. |
| 7 | Test1 | input | Test input pin 1; must be connected to VSS on the board to prevent the IC from entering test mode. |
| 8 | CLKO | output | Programmable clock output from the PLL (default 1.978 MHz; 1.978/3.955/7.910/15.82 MHz options), disabled via the ENB bit of the PLL register if unused. |
| 9 | ResetB | input | Active-low reset input; must be pulled high by the host microcontroller and/or an external resistor to VCC when in use. |
| 10 | ISEL | input | Interface select input; low selects TWI, high selects SPI mode 0. |
| 11 | TestD | unconnected | Test output pin D; must be left open by the user. |
| 12 | Istat | output | Serial interface handshaking output; high indicates a byte is ready to read, and the device will not accept commands while it is high. |
| 13 | SSB | input | SPI slave select (active low) input; in TWI mode not used and connected to VSS. |
| 14 | SCK | input | Serial clock input for both SPI and TWI modes. |
| 15 | SDI | bidirectional | SPI serial data input, or TWI serial data input/output in TWI mode. |
| 16 | Test2 | input | Test input pin 2; must be connected to VSS on the board to prevent the IC from entering test mode. |
| 17 | Test3 | input | Test input pin 3; must be connected to VSS on the board to prevent the IC from entering test mode. |
| 18 | N.C. | unconnected | Not used; can be left open. |
| 19 | SDO | output | SPI serial data output; not used in TWI mode. |
| 20 | ADDR | input | TWI device address select input (VSS gives $50/$51, VCC gives $D4/$D5); connect to VSS in SPI mode. |
| 21 | C1 | passive | Bypass capacitor pin requiring 0.33 uF to VSS for the digital circuits, placed within 3 mm of the package. |
| 22 | VSS | power_in | Digital ground for I/O buffers and digital circuits; keep separated from VSSA and VSS_ANT planes by a minimum of 20 mils. |
| 23 | VSSA | power_in | Analog ground; connect to VSS at only a single point within 1 cm of pins 22 and 23, not directly to VSS_ANT. |
| 24 | VCC | power_in | Supply for I/O buffers, digital and analog circuits (3.0 to 3.6 V or 4.5 to 5.5 V), matching the microcontroller I/O voltage; requires 15 nF and 2.2 uF bypass capacitors. |
| 25 | C4 | passive | Bypass capacitor pin requiring 0.33 uF to VSSA for the analog circuits, placed within 3 mm of the package. |
| 26 | C2 | passive | Bypass capacitor pin requiring 47 nF to VSSA for the analog circuits, placed within 3 mm of the package. |
| 27 | C3 | passive | Bypass capacitor pin requiring 47 nF to VSSA for the analog circuits, placed within 3 mm of the package. |
| 28 | N.C. | unconnected | Not used; can be left open. |
| 29 | C7 | passive | Bypass capacitor pin requiring 47 nF to VSSA for the analog circuits, placed within 3 mm of the package. |
| 30 | N.C. | unconnected | Not used; can be left open. |
| 31 | TestR | unconnected | Test output pin R (analog out); must be left open by the user. |
| 32 | RFin | input | RF receiver input; a resistor/capacitor filter limits the peak-to-peak voltage on this pin to a safe level. |
| 33 | N.C. | unconnected | Not used; can be left open. |
| 34 | Rmod | passive | Analog test pin that must be connected to VSS_ANT on the board. |
| 35 | C6 | passive | Antenna bypass capacitor pin that provides power to the antenna circuits and modulates the power level for communications. |
| 36 | N.C. | unconnected | Not used; can be left open. |
| 37 | EP | passive | Exposed pad (from the footprint; not named in the datasheet pin table). |
Key specifications
| Parameter | Value |
|---|---|
| Manufacturer | Microchip Tech |
| Package | QFN-36-EP(6x6) |
| Category | Embedded Processors & Controllers |
| Pins | 37 |
Electrical characteristics
Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).
| Parameter | Symbol | Min | Typ | Max | Unit | Conditions | Page |
|---|---|---|---|---|---|---|---|
| Supply voltage VCC (5 V digital interface) | VCC | 4.5 | 5 | 5.5 | V | 5 Volt Digital interface | 16 |
| Supply voltage VCC (3.3 V digital interface) | VCC | 3 | 3.3 | 3.6 | V | 3.3 Volt Digital Interface | 16 |
| Antenna driver supply voltage, high output power | VCC_ANT | 4.5 | 5 | 5.5 | V | High Output Power | 16 |
| Antenna driver supply voltage, low output power | VCC_ANT | 3 | 3.3 | 3.6 | V | Low Output Power | 16 |
| Operating temperature (case) | -40 | 85 | °C | TC | 1 | ||
| Operating temperature (case) | -40 | 85 | °C | case temp | 16 | ||
| Storage temperature (case) | -65 | 150 | °C | case temp | 16 | ||
| Power dissipation | 2 | W | 16 | ||||
| Maximum operating voltage VCC | VCC | 6 | V | 16 | |||
| Maximum operating voltage VCC_ANT | VCC_ANT | 6 | V | 16 | |||
| DC current VCC pin | 100 | mA | 16 | ||||
| HBM ESD | 2000 | V | minimum | 16 | |||
| Output low voltage (SDI pin, TWI mode only) | VOL1 | 0 | 0.4 | V | VCC = max, IOL = 3 mA | 17 | |
| SDA pull-up resistor, VCC 3.0-3.6 V, 100 kHz | RSDA | 1 | 4 | kOhm | TWI mode, SCK = 100kHz | 17 | |
| SDA pull-up resistor, VCC 4.5-5.5 V, 100 kHz | RSDA | 1.7 | 8 | kOhm | TWI mode, SCK = 100kHz | 17 | |
| SDA pull-up resistor, VCC 3.0-3.6 V, 1 MHz | RSDA | 1 | 2 | kOhm | TWI mode, SCK = 1 MHz | 17 | |
| SDA pull-up resistor, VCC 4.5-5.5 V, 1 MHz | RSDA | 1.7 | 3.3 | kOhm | TWI mode, SCK = 1 MHz | 17 | |
| Serial clock frequency, TWI mode | fSCK | 1 | MHz | TWI mode | 17 | ||
| Serial clock frequency, SPI mode | fSCK | 2 | MHz | SPI mode | 17 | ||
| Minimum pulse width on ResetB pin | tRST | 500 | uS | 17 | |||
| Crystal oscillator start-up time | tOSC | 1000 | uS | At power-up | 17 | ||
| Carrier frequency | fc | 13.553 | 13.56 | 13.567 | MHz | RF Enabled | 21 |
| Field modulation index | M.I. | 8 | 11 | 14 | percent | RF Enabled, Transmitting Data | 21 |
| Elementary time unit (transmit) | ETU | 9.4346 | 9.4395 | 9.4444 | uS | RF Enabled, Transmitting Data | 21 |
| Elementary time unit (receive) | ETU | 9.4346 | 9.4395 | 9.4444 | uS | RF Enabled, Receiving Data | 21 |
| Thermal resistance junction to ambient | θJA | 30.9 | °C/W | JEDEC multilayer board, nine thermal vias | 22 | ||
| Thermal characterization parameter junction to board | ψJB | 12.1 | °C/W | JEDEC multilayer board, nine thermal vias | 22 | ||
| ResetB pull-up resistor | RRST | 10 | kOhm | 17 | |||
| Input pull-up resistor | RPU | 10 | kOhm | Unused input pin | 17 |
Materials and finish
As the datasheet states them (page.json metadata.appearance; the 3D model's colours follow it).
| Part | Material | Colour / plating | Datasheet says | Page |
|---|---|---|---|---|
| contacts | copper | and thermal pad region, type of vias, board thickness, copper thickness, lead finish on the package, surface finish on | 33 |
CAD (KiCad official)
- Symbol:
AT88RF1354-ZU - Footprint:
Package_DFN_QFN:QFN-36-1EP_6x6mm_P0.5mm_EP3.7x3.7mm - 3D model: QFN-36-EP(6x6) (KiCad packages3D, STEP)
- 3D model files:
at88rf1354-zu-etched.step/at88rf1354-zu-etched.glbcarry the MPN laser-etched on the die in a toggleableAdom.LaserEtchgroup (Fusion-ready);at88rf1354-zu.step/at88rf1354-zu.glbare the bare package body.
Provenance
Data extracted from the manufacturer datasheet, not a distributor listing:
- Datasheet: Microchip Tech datasheet (48 pp, sha256
e5d543468a8a09ab, retrieved 2026-10-31, tier: lcsc) - Extractor: parts-factory
2.0.0/extract_pins 0.3, primaryclaude-sonnet-5-5(text), consensusclaude-sonnet-5-5(agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish. - CAD: KiCad official libraries (CC-BY-SA 4.0).
# AT88RF1354-ZU
**Microchip Tech** · Pre-ordered MCUs · QFN-36-EP(6x6)
AT88RF1354-ZU from Microchip Tech, in a QFN-36-EP(6x6). Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.
## Pinout
| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | VCC_ANT | power_in | Antenna supply voltage powering the transmitter and antenna drive circuits; requires 15 nF (within 3 mm) and 2.2 uF (within 5 mm) bypass capacitors to VSS_ANT. |
| 2 | VSS_ANT | power_in | Antenna ground, high current return path for transmitter and antenna drive circuit; connect to VSS at only a single point. |
| 3 | ANT | output | Antenna driver output generating the 13.56 MHz carrier, shaped into a sine wave by external passive circuitry. |
| 4 | Xtal1 | passive | Crystal pin 1; a 13.56 MHz crystal is connected between Xtal1 and Xtal2. |
| 5 | Xtal2 | passive | Crystal pin 2; a 13.56 MHz crystal is connected between Xtal1 and Xtal2. |
| 6 | C5 | passive | Bypass capacitor pin requiring 0.33 uF to VSS for the digital circuits, placed within 3 mm of the package. |
| 7 | Test1 | input | Test input pin 1; must be connected to VSS on the board to prevent the IC from entering test mode. |
| 8 | CLKO | output | Programmable clock output from the PLL (default 1.978 MHz; 1.978/3.955/7.910/15.82 MHz options), disabled via the ENB bit of the PLL register if unused. |
| 9 | ResetB | input | Active-low reset input; must be pulled high by the host microcontroller and/or an external resistor to VCC when in use. |
| 10 | ISEL | input | Interface select input; low selects TWI, high selects SPI mode 0. |
| 11 | TestD | unconnected | Test output pin D; must be left open by the user. |
| 12 | Istat | output | Serial interface handshaking output; high indicates a byte is ready to read, and the device will not accept commands while it is high. |
| 13 | SSB | input | SPI slave select (active low) input; in TWI mode not used and connected to VSS. |
| 14 | SCK | input | Serial clock input for both SPI and TWI modes. |
| 15 | SDI | bidirectional | SPI serial data input, or TWI serial data input/output in TWI mode. |
| 16 | Test2 | input | Test input pin 2; must be connected to VSS on the board to prevent the IC from entering test mode. |
| 17 | Test3 | input | Test input pin 3; must be connected to VSS on the board to prevent the IC from entering test mode. |
| 18 | N.C. | unconnected | Not used; can be left open. |
| 19 | SDO | output | SPI serial data output; not used in TWI mode. |
| 20 | ADDR | input | TWI device address select input (VSS gives $50/$51, VCC gives $D4/$D5); connect to VSS in SPI mode. |
| 21 | C1 | passive | Bypass capacitor pin requiring 0.33 uF to VSS for the digital circuits, placed within 3 mm of the package. |
| 22 | VSS | power_in | Digital ground for I/O buffers and digital circuits; keep separated from VSSA and VSS_ANT planes by a minimum of 20 mils. |
| 23 | VSSA | power_in | Analog ground; connect to VSS at only a single point within 1 cm of pins 22 and 23, not directly to VSS_ANT. |
| 24 | VCC | power_in | Supply for I/O buffers, digital and analog circuits (3.0 to 3.6 V or 4.5 to 5.5 V), matching the microcontroller I/O voltage; requires 15 nF and 2.2 uF bypass capacitors. |
| 25 | C4 | passive | Bypass capacitor pin requiring 0.33 uF to VSSA for the analog circuits, placed within 3 mm of the package. |
| 26 | C2 | passive | Bypass capacitor pin requiring 47 nF to VSSA for the analog circuits, placed within 3 mm of the package. |
| 27 | C3 | passive | Bypass capacitor pin requiring 47 nF to VSSA for the analog circuits, placed within 3 mm of the package. |
| 28 | N.C. | unconnected | Not used; can be left open. |
| 29 | C7 | passive | Bypass capacitor pin requiring 47 nF to VSSA for the analog circuits, placed within 3 mm of the package. |
| 30 | N.C. | unconnected | Not used; can be left open. |
| 31 | TestR | unconnected | Test output pin R (analog out); must be left open by the user. |
| 32 | RFin | input | RF receiver input; a resistor/capacitor filter limits the peak-to-peak voltage on this pin to a safe level. |
| 33 | N.C. | unconnected | Not used; can be left open. |
| 34 | Rmod | passive | Analog test pin that must be connected to VSS_ANT on the board. |
| 35 | C6 | passive | Antenna bypass capacitor pin that provides power to the antenna circuits and modulates the power level for communications. |
| 36 | N.C. | unconnected | Not used; can be left open. |
| 37 | EP | passive | Exposed pad (from the footprint; not named in the datasheet pin table). |
## Key specifications
| Parameter | Value |
|---|---|
| Manufacturer | Microchip Tech |
| Package | QFN-36-EP(6x6) |
| Category | Embedded Processors & Controllers |
| Pins | 37 |
## Electrical characteristics
Limits as printed in the datasheet (page.json `metadata.characteristics` carries them as data).
| Parameter | Symbol | Min | Typ | Max | Unit | Conditions | Page |
|---|---|---|---|---|---|---|---|
| Supply voltage VCC (5 V digital interface) | VCC | 4.5 | 5 | 5.5 | V | 5 Volt Digital interface | 16 |
| Supply voltage VCC (3.3 V digital interface) | VCC | 3 | 3.3 | 3.6 | V | 3.3 Volt Digital Interface | 16 |
| Antenna driver supply voltage, high output power | VCC_ANT | 4.5 | 5 | 5.5 | V | High Output Power | 16 |
| Antenna driver supply voltage, low output power | VCC_ANT | 3 | 3.3 | 3.6 | V | Low Output Power | 16 |
| Operating temperature (case) | | -40 | | 85 | °C | TC | 1 |
| Operating temperature (case) | | -40 | | 85 | °C | case temp | 16 |
| Storage temperature (case) | | -65 | | 150 | °C | case temp | 16 |
| Power dissipation | | | | 2 | W | | 16 |
| Maximum operating voltage VCC | VCC | | | 6 | V | | 16 |
| Maximum operating voltage VCC_ANT | VCC_ANT | | | 6 | V | | 16 |
| DC current VCC pin | | | | 100 | mA | | 16 |
| HBM ESD | | 2000 | | | V | minimum | 16 |
| Output low voltage (SDI pin, TWI mode only) | VOL1 | 0 | | 0.4 | V | VCC = max, IOL = 3 mA | 17 |
| SDA pull-up resistor, VCC 3.0-3.6 V, 100 kHz | RSDA | 1 | | 4 | kOhm | TWI mode, SCK = 100kHz | 17 |
| SDA pull-up resistor, VCC 4.5-5.5 V, 100 kHz | RSDA | 1.7 | | 8 | kOhm | TWI mode, SCK = 100kHz | 17 |
| SDA pull-up resistor, VCC 3.0-3.6 V, 1 MHz | RSDA | 1 | | 2 | kOhm | TWI mode, SCK = 1 MHz | 17 |
| SDA pull-up resistor, VCC 4.5-5.5 V, 1 MHz | RSDA | 1.7 | | 3.3 | kOhm | TWI mode, SCK = 1 MHz | 17 |
| Serial clock frequency, TWI mode | fSCK | | | 1 | MHz | TWI mode | 17 |
| Serial clock frequency, SPI mode | fSCK | | | 2 | MHz | SPI mode | 17 |
| Minimum pulse width on ResetB pin | tRST | 500 | | | uS | | 17 |
| Crystal oscillator start-up time | tOSC | | | 1000 | uS | At power-up | 17 |
| Carrier frequency | fc | 13.553 | 13.56 | 13.567 | MHz | RF Enabled | 21 |
| Field modulation index | M.I. | 8 | 11 | 14 | percent | RF Enabled, Transmitting Data | 21 |
| Elementary time unit (transmit) | ETU | 9.4346 | 9.4395 | 9.4444 | uS | RF Enabled, Transmitting Data | 21 |
| Elementary time unit (receive) | ETU | 9.4346 | 9.4395 | 9.4444 | uS | RF Enabled, Receiving Data | 21 |
| Thermal resistance junction to ambient | θJA | | 30.9 | | °C/W | JEDEC multilayer board, nine thermal vias | 22 |
| Thermal characterization parameter junction to board | ψJB | | 12.1 | | °C/W | JEDEC multilayer board, nine thermal vias | 22 |
| ResetB pull-up resistor | RRST | | 10 | | kOhm | | 17 |
| Input pull-up resistor | RPU | | 10 | | kOhm | Unused input pin | 17 |
## Materials and finish
As the datasheet states them (page.json `metadata.appearance`; the 3D model's colours follow it).
| Part | Material | Colour / plating | Datasheet says | Page |
|---|---|---|---|---|
| contacts | copper | | and thermal pad region, type of vias, board thickness, copper thickness, lead finish on the package, surface finish on | 33 |
## CAD (KiCad official)
- Symbol: `AT88RF1354-ZU`
- Footprint: `Package_DFN_QFN:QFN-36-1EP_6x6mm_P0.5mm_EP3.7x3.7mm`
- 3D model: QFN-36-EP(6x6) (KiCad packages3D, STEP)
- 3D model files: `at88rf1354-zu-etched.step` / `at88rf1354-zu-etched.glb` carry the MPN laser-etched on the die in a toggleable `Adom.LaserEtch` group (Fusion-ready); `at88rf1354-zu.step` / `at88rf1354-zu.glb` are the bare package body.
## Provenance
Data extracted from the manufacturer datasheet, not a distributor listing:
- **Datasheet:** [Microchip Tech datasheet](docs/at88rf1354-zu-datasheet.pdf) (48 pp, sha256 `e5d543468a8a09ab`, retrieved 2026-10-31, tier: lcsc)
- **Extractor:** parts-factory `2.0.0` / `extract_pins 0.3`, primary `claude-sonnet-5-5` (text), consensus `claude-sonnet-5-5` (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
- **CAD:** KiCad official libraries (CC-BY-SA 4.0).
[Datasheet PDF](docs/at88rf1354-zu-datasheet.pdf)