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AT86RF233-ZU

Public Made by Adom

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Microchip Tech RF Transceiver ICs, QFN-32-EP(5x5). Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.

componentrf & radioat86rf233-zufactory-2.0.0extractor-text

Verified AT86RF233-ZU

by Ray · last 30 Oct 2026 · 1 record · files match
SymbolFootprint3D modelPins

Verification log 1 record

30 Oct 2026RayPublished by the parts factory: tier mfr, 33 pinsfiles match
SymbolFootprint3D modelPinsfor all variants
  • ✓component-page-verify: PASS
  • ✓cad_props: Datasheet, MPN and distributor properties match page.json
  • ✓component: AT86RF233-ZU · QFN-32-EP(5x5) · 33 pins
  • ✓copper: 33 copper pads, none touching another net
  • ✓datasheet: all 33 pin names found in the 225-page datasheet
  • ✓distributor: lcsc C177148, digikey AT86RF233-ZU-ND, mouser 556-AT86RF233-ZU
  • ✓family: QFN-32-1EP_5x5mm_P0.5mm_EP3.3x3.3mm
  • ✓files: 7 declared files present
  • ✓hero: docs/hero.png 4000x2500
  • ✓lbr: OK: /tmp/cpv-xdu51wwr/x.lbr is a valid EAGLE .lbr with complete deviceset
  • ✓license: CC-BY-SA-4.0
  • ✓models_3d: 2 records
  • •package_fit (skip): the datasheet dimensions give no height or body size to compare (datasheet p.209)
  • ✓pads: 33 pins = 33 pads
  • ✓pose: 2 STEP(s) Z-up, seated, centred
  • ✓symbol: 33 pins agree
  • ✓visibility: public, source open
Evidencedatasheet
Verified files✓ at86rf233-zu.kicad_sym✓ at86rf233-zu.kicad_mod✓ at86rf233-zu.step
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Generated by kicad-footprint-generator · KiCad file format 20260206
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docs Publish 0.1.0 · Ray 5d ago
viewers at86rf233-zu: viewers · Ray 5d ago
at86rf233-zu-etched.glb Publish 0.1.0 · Ray 5d ago
at86rf233-zu-etched.step at86rf233-zu: factory component page (tier=mfr) · Ray 5d ago
at86rf233-zu-hero.glb at86rf233-zu: hero GLB from the etched model (keeps the MPN mark) · Ray 5d ago
at86rf233-zu-hero.overlay.json Publish 0.1.0 · Ray 5d ago
at86rf233-zu.glb Publish 0.1.0 · Ray 5d ago
at86rf233-zu.kicad_mod Publish 0.1.0 · Ray 5d ago
at86rf233-zu.kicad_sym Publish 0.1.0 · Ray 5d ago
at86rf233-zu.lbr Publish 0.1.0 · Ray 5d ago
at86rf233-zu.step Publish 0.1.0 · Ray 5d ago
package.json Publish 0.1.0 · Ray 5d ago
page.json Set visibility: public · Ray 5d ago
README.md Publish 0.1.0 · Ray 5d ago
verification.json Verified: Published by the parts factory: tier mfr, 33 pins · Ray 5d ago

AT86RF233-ZU

Microchip Tech · RF Transceiver ICs · QFN-32-EP(5x5)

AT86RF233-ZU from Microchip Tech, in a QFN-32-EP(5x5). Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 DIG3 output Digital output providing the RX/TX indicator (Section 11.5), with pull-down to AVSS enabled when the function is disabled.
2 DIG4 output Digital output providing the RX/TX indicator inverted relative to DIG3 (Section 11.5), with pull-down to AVSS enabled when the function is disabled.
3 AVSS power_in Analog ground for RF signals.
4 RFP bidirectional Differential RF port designed for a 100Ω differential load; a DC path to ground or supply voltage is not allowed.
5 RFN bidirectional Differential RF port designed for a 100Ω differential load; a DC path to ground or supply voltage is not allowed.
6 AVSS power_in Analog ground for RF signals.
7 DVSS power_in Digital ground; analog and digital power domains should be separated on the PCB.
8 /RST input Active-low chip reset input; internal pull-up is active only in P_ON and DEEP_SLEEP states.
9 DIG1 output Digital output for antenna diversity RF switch control (Section 11.4), with pull-down to DVSS enabled when the function is disabled.
10 DIG2 output Digital output for antenna diversity switch control (inverted DIG1), RX and TX frame time stamping (Section 11.6), with pull-down to DVSS when disabled.
11 SLP_TR input Digital input controlling sleep, deep sleep, transmit start and receive states; active high (Section 6.6).
12 DVSS power_in Digital ground.
13 DVDD power_out Regulated 1.8V digital regulator output or regulated voltage input (digital domain); outputs shall be bypassed by 100nF.
14 DVDD power_out Regulated 1.8V digital regulator output or regulated voltage input (digital domain); outputs shall be bypassed by 100nF.
15 DEVDD power_in External supply voltage for the digital domain, specified as 1.8V to 3.6V.
16 DVSS power_in Digital ground.
17 CLKM output Master clock signal output, low when disabled; capacitive load should be no larger than 50pF.
18 DVSS power_in Digital ground.
19 SCLK input SPI clock input.
20 MISO output SPI data output (master input slave output); driver strength is fixed and capacitive load should be no larger than 50pF.
21 DVSS power_in Digital ground.
22 MOSI input SPI data input (master output slave input).
23 /SEL input SPI select input, active low.
24 IRQ output Interrupt request output, configurable as active high or active low; also serves as an active-high Frame Buffer Empty indicator (Section 11.7).
25 XTAL2 input Crystal oscillator pin; parasitic pin capacitance of 3pF must be considered as additional load capacitance on the crystal.
26 XTAL1 input Crystal oscillator input, or external clock supply input when an external reference clock is used.
27 AVSS power_in Analog ground.
28 EVDD power_in External supply voltage for the analog domain, specified as 1.8V to 3.6V.
29 AVDD power_out Regulated 1.8V analog regulator output for the analog domain; output shall be bypassed by 100nF.
30 AVSS power_in Analog ground.
31 AVSS power_in Analog ground.
32 AVSS power_in Analog ground.
33 AVSS passive Exposed pad (from the footprint; not named in the datasheet pin table).

Key specifications

Parameter Value
Manufacturer Microchip Tech
Package QFN-32-EP(5x5)
Category RF & Radio
Pins 33

Electrical characteristics

Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).

Parameter Symbol Min Typ Max Unit Conditions Page
Storage temperature TSTOR -50 150 °C 189
Lead temperature TLEAD 260 °C T = 10s (soldering profile compliant with IPC/JEDEC J STD 020B) 189
ESD robustness, Human Body Model VESD 4 kV Human Body Model (HBM) 189
Input RF level PRF 10 dBm 189
Voltage on all pins VDIG -0.3 V Except pins 4, 5, 13, 14, 29; upper limit printed as VDD+0.3 V 189
Voltage on pins 4, 5, 13, 14, 29 VANA -0.3 2 V Pins 4, 5, 13, 14, 29 189
Operating temperature range TOP -40 25 85 °C 189
Supply voltage VDD 1.8 3 3.6 V Voltage on pins 15, 28 189
Supply voltage (on pins 13, 14, 29) VDD1.8 1.7 1.8 1.9 V External voltage supply 189
Low level input voltage VIL 0.4 V TOP = +25°C 190
Low level output voltage VOL 0.4 V TOP = +25°C 190
Capacitive load CLoad 50 pF TOP = +25°C; should not be larger than 50pF for all I/Os 190
SCLK frequency, synchronous operation fsync 8 MHz Synchronous operation; TOP = +25°C, VDD = 3.0V, CLoad = 50pF 190
/SEL falling edge to MISO active t1 180 ns TOP = +25°C, VDD = 3.0V, CLoad = 50pF 190
MOSI setup time t3 10 ns TOP = +25°C, VDD = 3.0V, CLoad = 50pF 190
LSB last byte to MSB next byte (SPI read/write, standard SRAM and frame access modes) t5 250 ns TOP = +25°C, VDD = 3.0V, CLoad = 50pF 190
SLP_TR pulse width, TX start trigger t7 62.5 ns TX start trigger; maximum pulse width less than TX frame length + 16µs 190
Reset pulse width t10 625 ns ≥ 10 clock cycles at 16MHz 190
Frame buffer empty indicator latency t12 750 ns Rising edge of last SCLK of Frame Buffer read command byte to rising edge of IRQ 190
IRQ_2, IRQ_3, IRQ_4 latency tIRQ 9 µs Relative to the event to be indicated 190
Frequency range fRF 2405 2445 2480 MHz VDD = 3.0V, fRF = 2445MHz, TOP = +25°C; as specified in [1], [2] 191
Frequency range, 500kHz spacing fRF 2322 2527 MHz VDD = 3.0V, fRF = 2445MHz, TOP = +25°C; 500kHz spacing 191
Symbol rate deviation (reference frequency accuracy), 250kb/s fSRD -60 60 ppm VDD = 3.0V, fRF = 2445MHz, TOP = +25°C; PSDU bit rate 250kb/s 191
Symbol rate deviation (reference frequency accuracy), 500kb/s fSRD -40 40 ppm VDD = 3.0V, fRF = 2445MHz, TOP = +25°C; PSDU bit rate 500kb/s 191
Symbol rate deviation (reference frequency accuracy), 1000kb/s fSRD -40 40 ppm VDD = 3.0V, fRF = 2445MHz, TOP = +25°C; PSDU bit rate 1000kb/s 191
Symbol rate deviation (reference frequency accuracy), 2000kb/s fSRD -30 30 ppm VDD = 3.0V, fRF = 2445MHz, TOP = +25°C; PSDU bit rate 2000kb/s 191
TX output power (maximum configurable) PTX_MAX 4 dBm VDD = 3.0V, fRF = 2445MHz, TOP = +25°C; register bit TX_PWR = 0 192
Output power tolerance PACC -2 2 dB VDD = 3.0V, fRF = 2445MHz, TOP = +25°C 192
Error vector magnitude EVM 12 %rms VDD = 3.0V, fRF = 2445MHz, TOP = +25°C 192
2nd harmonic PHARM -40 dBm VDD = 3.0V, fRF = 2445MHz, TOP = +25°C 192
3rd harmonic PHARM -45 dBm VDD = 3.0V, fRF = 2445MHz, TOP = +25°C 192
Spurious emissions, 30 to ≤1000 MHz PSPUR_TX -36 dBm VDD = 3.0V, fRF = 2445MHz, TOP = +25°C; 30, ≤1000 MHz 192
Spurious emissions, >1 to 12.75 GHz PSPUR_TX -30 dBm VDD = 3.0V, fRF = 2445MHz, TOP = +25°C; >1, 12.75 GHz 192
Receiver sensitivity, 250kb/s PSENS -101 dBm VDD = 3.0V, fRF = 2445MHz, TOP = +25°C, fPSDU = 250kb/s; AWGN channel, PER ≤ 1%, PSDU length 20 octets 192
Receiver sensitivity, 2000kb/s PSENS -88 dBm VDD = 3.0V, fRF = 2445MHz, TOP = +25°C; 2000kb/s; AWGN channel, PER ≤ 1%, PSDU length 20 octets 192
RX return loss RLRX 10 dB VDD = 3.0V, fRF = 2445MHz, TOP = +25°C; 100Ω differential impedance 192
Noise figure NF 6 dB VDD = 3.0V, fRF = 2445MHz, TOP = +25°C 192
Maximum RX input level, 250kb/s PRX_MAX 8 dBm VDD = 3.0V, fRF = 2445MHz, TOP = +25°C; 250kb/s 192
Spurious emissions: LO leakage PSPUR_RX -70 dBm VDD = 3.0V, fRF = 2445MHz, TOP = +25°C; LO leakage 193
TX/RX carrier frequency offset fCAR_OFFS -300 300 kHz VDD = 3.0V, fRF = 2445MHz, TOP = +25°C; sensitivity loss ≤ 2dB; offset equals ±120ppm 193
3rd-order intercept point (IIP3) IIP3 -10 dBm VDD = 3.0V, fRF = 2445MHz, TOP = +25°C; at maximum gain; offset freq. interferer 1 = 5MHz, interferer 2 = 10MHz 193
RSSI tolerance RSSITOL -5 5 dB VDD = 3.0V, fRF = 2445MHz, TOP = +25°C; tolerance within gain step 193
RSSI dynamic range RSSIRANGE 87 dB VDD = 3.0V, fRF = 2445MHz, TOP = +25°C 193
Supply current, transmit state, PTX = +4dBm IBUSY_TX 13.8 mA VDD = 3.0V, fRF = 2445MHz, TOP = +25°C; PTX = +4dBm 193
Supply current, transmit state, PTX = +0dBm IBUSY_TX 11.8 mA VDD = 3.0V, fRF = 2445MHz, TOP = +25°C; PTX = +0dBm 193
Supply current, transmit state, PTX = -17dBm IBUSY_TX 7.2 mA VDD = 3.0V, fRF = 2445MHz, TOP = +25°C; PTX = -17dBm 193
Supply current, RX_ON state, high sensitivity IRX_ON 11.8 mA VDD = 3.0V, fRF = 2445MHz, TOP = +25°C; high sensitivity, RX_PDT_LEVEL = [0x0] 193
Supply current, RX_ON state, with receiver desensitize IRX_ON_L0 11.3 mA VDD = 3.0V, fRF = 2445MHz, TOP = +25°C; RX_PDT_LEVEL = [0x1, …, 0xE, 0xF] 193
Supply current, PLL_ON state IPLL_ON 5.2 mA VDD = 3.0V, fRF = 2445MHz, TOP = +25°C; PLL_ON state 193
Supply current, TRX_OFF state ITRX_OFF 300 µA VDD = 3.0V, fRF = 2445MHz, TOP = +25°C; TRX_OFF state 193
Supply current, SLEEP state ISLEEP 0.2 µA VDD = 3.0V, fRF = 2445MHz, TOP = +25°C; SLEEP state 194
Supply current, DEEP_SLEEP state IDEEP_SLEEP 0.02 µA VDD = 3.0V, fRF = 2445MHz, TOP = +25°C; DEEP_SLEEP state 194
Crystal load capacitance CL 8 14 pF TOP = +25°C, VDD = 3.0V 194
Crystal shunt capacitance C0 7 pF TOP = +25°C, VDD = 3.0V 194
Equivalent series resistance ESR 100 Ω TOP = +25°C, VDD = 3.0V 194
Package thermal resistance, junction to ambient, 0 m/s Theta ja 40.9 K/W Air velocity 0 m/s 208

CAD (KiCad official)

  • Symbol: AT86RF233-ZU
  • Footprint: Package_DFN_QFN:QFN-32-1EP_5x5mm_P0.5mm_EP3.3x3.3mm
  • 3D model: QFN-32-EP(5x5) (KiCad packages3D, STEP)
  • 3D model files: at86rf233-zu-etched.step / at86rf233-zu-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); at86rf233-zu.step / at86rf233-zu.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: Microchip Tech datasheet (225 pp, sha256 a10810f104df0459, retrieved 2026-10-30, tier: manufacturer)
  • Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-haiku-5-5 (text), consensus claude-sonnet-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF