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AT86RF231-ZUR

Public Made by Adom

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Microchip Tech Pre-ordered MCUs, QFN-32-EP(5x5). Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.

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Symbol & Footprint

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Contents

README

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AT86RF231-ZUR

Microchip Tech · Pre-ordered MCUs · QFN-32-EP(5x5)

AT86RF231-ZUR from Microchip Tech, in a QFN-32-EP(5x5). Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 DIG3 output RX/TX indicator output; if disabled, a pull-down to AVSS is enabled.
2 DIG4 output RX/TX indicator output, inverted relative to DIG3; if disabled, a pull-down to AVSS is enabled.
3 AVSS power_in Analog ground for RF signals.
4 RFP bidirectional Differential RF signal pin designed for a 100 Ω differential load; DC to ground or supply is not allowed.
5 RFN bidirectional Differential RF signal pin designed for a 100 Ω differential load; DC to ground or supply is not allowed.
6 AVSS power_in Analog ground for RF signals.
7 DVSS power_in Digital ground.
8 /RST input Chip reset input, active low.
9 DIG1 output Antenna diversity RF switch control output; if disabled, a pull-down to DVSS is enabled.
10 DIG2 output Antenna diversity RF switch control output, inverted relative to DIG1; also carries IRQ_2 (RX_START) for RX frame time stamping; if functions are disabled, a pull-down to DVSS is enabled.
11 SLP_TR input Controls sleep, transmit start and receive states; active high.
12 DVSS power_in Digital ground.
13 DVDD power_out Output of the internal regulated 1.8V voltage regulator for the digital domain.
14 DVDD power_out Output of the internal regulated 1.8V voltage regulator for the digital domain.
15 DEVDD power_in External supply voltage input for the digital domain.
16 DVSS power_in Digital ground.
17 CLKM output Master clock signal output; low if disabled.
18 DVSS power_in Digital ground.
19 SCLK input SPI clock input.
20 MISO output SPI data output (Master Input Slave Output).
21 DVSS power_in Digital ground.
22 MOSI input SPI data input (Master Output Slave Input).
23 /SEL input SPI select input, active low.
24 IRQ output Interrupt request output, configurable as active high or active low; also serves as Frame Buffer Empty indicator, active high.
25 XTAL2 input Crystal pin for the oscillator.
26 XTAL1 input Crystal pin or external clock supply input.
27 AVSS power_in Analog ground.
28 EVDD power_in External supply voltage input for the analog domain.
29 AVDD power_out Output of the internal regulated 1.8V voltage regulator for the analog domain.
30 AVSS power_in Analog ground.
31 AVSS power_in Analog ground.
32 AVSS power_in Analog ground.
33 EP passive Exposed pad (from the footprint; not named in the datasheet pin table).

Key specifications

Parameter Value
Manufacturer Microchip Tech
Package QFN-32-EP(5x5)
Category Embedded Processors & Controllers
Pins 33

Electrical characteristics

Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).

Parameter Symbol Min Typ Max Unit Conditions Page
Operating temperature range TOP -40 85 °C 156
Supply voltage VDD 1.8 3 3.6 V Voltage on pins 15, 28 156
Supply voltage VDD1.8 1.7 1.8 1.9 V External voltage supply on pins 13, 14, 29 156
Storage temperature TSTOR -50 150 °C 156
Lead temperature TLEAD 260 °C T = 10s, soldering profile compliant with IPC/JEDEC J STD 020B 156
ESD robustness VESD 5000 V Compl. to [3] 156
ESD robustness VESD 1500 V Compl. to [4] 156
Input RF level PRF 10 dBm 156
Voltage on all pins (except pins 4, 5, 13, 14, 29) VDIG -0.3 V Maximum VDD+0.3 V 156
Voltage on pins 4, 5, 13, 14, 29 VANA -0.3 2 V 156
Low level input voltage VIL 0.4 V 157
Low level output voltage VOL 0.4 V For all output driver strengths defined in TRX_CTRL_0 157
SCLK frequency synchronous operation fsync 8 MHz Synchronous operation 157
SCLK frequency asynchronous operation fasync 7.5 MHz Asynchronous operation 157
/SEL low to MISO active t1 180 ns 157
SCLK to MISO out data hold time t2 10 ns 157
LSB last byte to MSB next byte t5 250 ns 157
/SEL high to MISO tri state t6 10 ns 157
SPI idle time (SEL rising to falling edge) t8 250 ns SPI read/write, standard SRAM and Frame Buffer access modes, idle time between consecutive SPI accesses 157
SPI idle time (SEL rising to falling edge) t8 500 ns SPI Fast SRAM read/write access mode, idle time between consecutive SPI accesses 157
Reset pulse width t10 625 ns 10 clock cycles at 16 MHz 157
SPI access latency after reset t11 625 ns 10 clock cycles at 16 MHz 157
Interrupt event latency tIRQ 9 µs Relative to the event to be indicated 157
Frequency range fRF 2405 2480 MHz As specified in [1], [2] 158
Reference oscillator settling time tXTAL 330 1000 µs Leaving SLEEP state to clock available at pin 17 (CLKM) 158
Symbol rate deviation (reference frequency accuracy) -60 60 ppm PSDU bit rate 250 kb/s 158
Symbol rate deviation (reference frequency accuracy) -40 40 ppm PSDU bit rate 500 kb/s 158
Symbol rate deviation (reference frequency accuracy) -30 30 ppm PSDU bit rate 2000 kb/s 158
TX output power PTX 0 3 6 dBm Maximum configurable TX output power value; register bit TX_PWR = 0 159
Output power tolerance PACC -3 3 dB 159
EVM EVM 8 %rms 159
2nd harmonic PHARM -45 dBm 2nd harmonic 159
Spurious emissions PSPUR -36 dBm 30 - ≤ 1000 MHz 159
Receiver sensitivity PSENS -101 dBm 250 kb/s; AWGN channel, PER ≤ 1%, PSDU length 20 octets 160
Receiver sensitivity PSENS -97 dBm 500 kb/s; High Data Rate Modes: PSDU length 20 octets 160
Receiver sensitivity PSENS -95 dBm 1000 kb/s; High Data Rate Modes: PSDU length 20 octets 160
Receiver sensitivity PSENS -89 dBm 2000 kb/s; High Data Rate Modes: PSDU length 20 octets 160
Receiver sensitivity with antenna diversity PSENS -99 dBm Antenna Diversity 250 kb/s, PSDU 20 octets 160
Maximum RX input level PRXMX 10 dBm PER ≤ 1%, PSDU length of 20 octets 160
Adjacent channel rejection PACRN 32 dB Δf = -5 MHz; PER ≤ 1%, PSDU length of 20 octets, PRF = -82 dBm 160
Adjacent channel rejection PACRP 35 dB Δf = +5 MHz; PER ≤ 1%, PSDU length of 20 octets, PRF = -82 dBm 160
Alternate channel rejection PAACR1 48 dB Δf = /10 MHz/; PER ≤ 1%, PSDU length of 20 octets, PRF = -82 dBm 160
TX/RX carrier frequency offset fRXTXOFFS -300 300 kHz Sensitivity loss < 2 dB 160
3rd - order intercept point IIP3 -10 dBm At maximum gain; Offset freq. interf. 1 = 5 MHz; Offset freq. interf. 2 = 10 MHz 160
Supply current transmit state IBUSY_TX 14 mA PTX = 3 dBm 161
Supply current transmit state IBUSY_TX 11.6 mA PTX = 0 dBm 161
Supply current transmit state IBUSY_TX 7.4 mA PTX = -17 dBm 161
Supply current RX_ON state IRX_ON 10.3 mA RX_ON state - high input level 161
Supply current RX_ON state IRX_ON 12.3 mA RX_ON state - high sensitivity 161
Supply current RX_ON state with sensitivity threshold IPLL_ON_P 11.8 mA RX_ON state, with register setting RX_PDT_LEVEL > 0 161
Supply current PLL_ON state IPLL_ON 5.6 mA PLL_ON state 161
Supply current TRX_OFF state ITRX_OFF 0.4 mA TRX_OFF state 161
Supply current SLEEP state ISLEEP 0.02 µA SLEEP state 161
Load capacitance (crystal requirement) CL 8 14 pF 161
Static capacitance (crystal requirement) C0 7 pF 161
Series resistance (crystal requirement) R1 100 Ω 161
Thermal resistance junction to ambient Theta ja 40.9 K/W Air velocity 0 m/s 173
Thermal resistance junction to ambient Theta ja 35.7 K/W Air velocity 1 m/s 173
Thermal resistance junction to ambient Theta ja 32 K/W Air velocity 2.5 m/s 173

Materials and finish

As the datasheet states them (page.json metadata.appearance; the 3D model's colours follow it).

Part Material Colour / plating Datasheet says Page
housing abs RSSI_BASE_VAL. The range is 84 dB with a resolution of 1 dB and an absolute accuracy of 93

CAD (KiCad official)

  • Symbol: AT86RF231-ZUR
  • Footprint: Package_DFN_QFN:QFN-32-1EP_5x5mm_P0.5mm_EP3.3x3.3mm
  • 3D model: QFN-32-EP(5x5) (KiCad packages3D, STEP)
  • 3D model files: at86rf231-zur-etched.step / at86rf231-zur-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); at86rf231-zur.step / at86rf231-zur.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: Microchip Tech datasheet (198 pp, sha256 9141421be924bd6b, retrieved 2026-10-28, tier: lcsc)
  • Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-haiku-5-5 (text), consensus claude-sonnet-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF