component
AT45DB161E-SSHD-B
Public Made by Adomby adom
Dialog Semiconductor NOR FLASH, SOIC-8. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.
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AT45DB161E-SSHD-B
Dialog Semiconductor · NOR FLASH · SOIC-8
AT45DB161E-SSHD-B from Dialog Semiconductor, in a SOIC-8. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.
Pinout
| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | SI | input | Serial Input shifts in all command, address and data bits, latched on the rising edge of SCK and ignored while the device is deselected. |
| 2 | SCK | input | Serial Clock controls data flow to and from the device, with input latched on the rising edge and output clocked out on the falling edge of SCK. |
| 3 | RESET | input | Active-low reset terminates the operation in progress and holds the internal state machine idle while low; drive it high externally if unused. |
| 4 | CS | input | Active-low Chip Select selects the device when asserted, and when deasserted deselects it into standby and puts SO in high impedance. |
| 5 | WP | input | Active-low Write Protect protects the sectors set in the Sector Protection Register against program and erase; it is internally pulled high and may be left floating if unused. |
| 6 | VCC | power_in | Device power supply, operated from 2.5V to 3.6V for the D option (2.3V to 3.6V for the F option), and operation at invalid VCC voltages should not be attempted. |
| 7 | GND | power_in | Ground reference for the power supply, to be connected to the system ground. |
| 8 | SO | output | Serial Output shifts data out on the falling edge of SCK and is in a high-impedance state whenever the device is deselected. |
Key specifications
| Parameter | Value |
|---|---|
| Manufacturer | Dialog Semiconductor |
| Package | SOIC-8 |
| Category | Memory |
| Pins | 8 |
Electrical characteristics
Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).
| Parameter | Symbol | Min | Typ | Max | Unit | Conditions | Page |
|---|---|---|---|---|---|---|---|
| Supply voltage VCC (2.5V version) | VCC | 2.5 | 3.6 | V | AT45DB161E 2.5V Version | 46 | |
| Operating temperature (case), industrial | -40 | 85 | C | AT45DB161E 2.5V Version | 46 | ||
| All output voltages with respect to ground | -0.6 | 4.2 | V | Max VCC of 3.6V + 0.6V | 46 | ||
| All input voltages with respect to ground (excluding VCC pin, including NC pins) | -0.6 | 4.2 | V | Max VCC of 3.6V + 0.6V | 46 | ||
| Storage temperature | -65 | 150 | C | 46 | |||
| Temperature under bias | -55 | 125 | C | 46 | |||
| Ultra-Deep Power-Down current | IUDPD | 0.4 | 1 | µA | CS= VCC. All other inputs at 0V or VCC | 47 | |
| Deep Power-Down current | IDPD | 5 | 12 | µA | CS= VCC. All other inputs at 0V or VCC | 47 | |
| Standby current | ISB | 25 | 50 | µA | CS= VCC. All other inputs at 0V or VCC | 47 | |
| Active current, low power read (01h) operation | ICC1 | 6 | 9 | mA | f = 1MHz; IOUT = 0mA | 47 | |
| Active current, low power read (01h) operation | ICC1 | 7 | 11 | mA | f = 15MHz; IOUT = 0mA | 47 | |
| Active current, read operation | ICC2 | 12 | 17 | mA | f = 50MHz; IOUT = 0mA | 47 | |
| Active current, read operation | ICC2 | 16 | 22 | mA | f = 85MHz; IOUT = 0mA | 47 | |
| Active current, program operation | ICC3 | 12 | 18 | mA | CS=VCC | 47 | |
| Active current, erase operation | ICC4 | 12 | 18 | mA | CS=VCC | 47 | |
| Input load current | ILI | 1 | µA | All inputs at CMOS levels | 47 | ||
| Output leakage current | ILO | 1 | µA | All inputs at CMOS levels | 47 | ||
| Output low voltage | VOL | 0.4 | V | IOL = 100µA | 47 | ||
| SCK frequency | fSCK | 70 | MHz | AT45DB161E 2.5V Version | 48 | ||
| SCK frequency for continuous read (0x0B) | fCAR1 | 85 | MHz | AT45DB161E 2.5V Version | 48 | ||
| SCK frequency for continuous read (0x03) (low frequency) | fCAR2 | 50 | MHz | AT45DB161E 2.5V Version | 48 | ||
| SCK frequency for continuous read (low power mode, 01h opcode) | fCAR3 | 15 | MHz | AT45DB161E 2.5V Version | 48 | ||
| SCK frequency for continuous read (0x1B) | fCAR4 | 104 | MHz | AT45DB161E 2.5V Version | 48 | ||
| SCK high time | tWH | 4 | ns | AT45DB161E 2.5V Version | 48 | ||
| SCK low time | tWL | 4 | ns | AT45DB161E 2.5V Version | 48 | ||
| SCK rise time, peak-to-peak | tSCKR | 0.1 | V/ns | AT45DB161E 2.5V Version | 48 | ||
| SCK fall time, peak-to-peak | tSCKF | 0.1 | V/ns | AT45DB161E 2.5V Version | 48 | ||
| Minimum CS high time | tCS | 20 | ns | AT45DB161E 2.5V Version | 48 | ||
| CS setup time | tCSS | 5 | ns | AT45DB161E 2.5V Version | 48 | ||
| CS hold time | tCSH | 5 | ns | AT45DB161E 2.5V Version | 48 | ||
| Data in setup time | tSU | 2 | ns | AT45DB161E 2.5V Version | 48 | ||
| Data in hold time | tH | 1 | ns | AT45DB161E 2.5V Version | 48 | ||
| Output hold time | tHO | 0 | ns | AT45DB161E 2.5V Version | 48 | ||
| Output disable time | tDIS | 6 | ns | AT45DB161E 2.5V Version | 48 | ||
| Output valid | tV | 7 | ns | AT45DB161E 2.5V Version | 48 | ||
| WP low to protection enabled | tWPE | 1 | µs | AT45DB161E 2.5V Version | 48 | ||
| WP high to protection disabled | tWPD | 1 | µs | AT45DB161E 2.5V Version | 48 | ||
| Freeze sector lockdown time (from CS high) | tLOCK | 100 | µs | AT45DB161E 2.5V Version | 48 | ||
| CS high to ultra-deep power-down | tEUDPD | 4 | µs | AT45DB161E 2.5V Version | 48 | ||
| Minimum CS low time to exit ultra-deep power-down | tCSLU | 20 | ns | AT45DB161E 2.5V Version | 48 | ||
| Exit ultra-deep power-down time | tXUDPD | 180 | µs | AT45DB161E 2.5V Version | 48 | ||
| CS high to deep power-down | tEDPD | 2 | µs | AT45DB161E 2.5V Version | 48 | ||
| Resume from deep power-down time | tRDPD | 35 | µs | AT45DB161E 2.5V Version | 48 | ||
| Page to buffer transfer time | tXFR | 200 | µs | AT45DB161E 2.5V Version | 48 | ||
| Page to buffer compare time | tCOMP | 200 | µs | AT45DB161E 2.5V Version | 48 | ||
| RESET pulse width | tRST | 10 | µs | AT45DB161E 2.5V Version | 48 | ||
| RESET recovery time | tREC | 1 | µs | AT45DB161E 2.5V Version | 48 | ||
| Software reset time | tSWRST | 35 | µs | AT45DB161E 2.5V Version | 48 | ||
| Page erase and programming time (512/528 bytes) | tEP | 17 | 25 | ms | 49 | ||
| Page programming time | tP | 3 | 4 | ms | 49 | ||
| Page erase time | tPE | 12 | 35 | ms | 49 | ||
| Block erase time | tBE | 45 | 100 | ms | 49 | ||
| Sector erase time | tSE | 1.4 | 2 | s | 49 | ||
| Chip erase time | tCE | 22 | 40 | s | 49 | ||
| Suspend time, program | tSUSP | 10 | 15 | µs | Program | 49 | |
| Suspend time, erase | tSUSP | 20 | 30 | µs | Erase | 49 | |
| Resume time, program | tRES | 10 | 15 | µs | Program | 49 | |
| Resume time, erase | tRES | 20 | 30 | µs | Erase | 49 | |
| OTP security register program time | tOTPP | 200 | 500 | µs | 49 |
CAD (KiCad official)
- Symbol:
AT45DB161E-SSHD-B - Footprint:
Package_SO:SOIC-8_3.9x4.9mm_P1.27mm - 3D model: SOIC-8 (KiCad packages3D, STEP)
- 3D model files:
at45db161e-sshd-b-etched.step/at45db161e-sshd-b-etched.glbcarry the MPN laser-etched on the die in a toggleableAdom.LaserEtchgroup (Fusion-ready);at45db161e-sshd-b.step/at45db161e-sshd-b.glbare the bare package body.
Provenance
Data extracted from the manufacturer datasheet, not a distributor listing:
- Datasheet: Dialog Semiconductor datasheet (74 pp, sha256
ac36775344285e29, retrieved 2026-10-29, tier: lcsc) - Extractor: parts-factory
2.0.0/extract_pins 0.3, primaryclaude-haiku-5-5(text), consensusclaude-sonnet-5-5(agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish. - CAD: KiCad official libraries (CC-BY-SA 4.0).
# AT45DB161E-SSHD-B
**Dialog Semiconductor** · NOR FLASH · SOIC-8
AT45DB161E-SSHD-B from Dialog Semiconductor, in a SOIC-8. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.
## Pinout
| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | SI | input | Serial Input shifts in all command, address and data bits, latched on the rising edge of SCK and ignored while the device is deselected. |
| 2 | SCK | input | Serial Clock controls data flow to and from the device, with input latched on the rising edge and output clocked out on the falling edge of SCK. |
| 3 | RESET | input | Active-low reset terminates the operation in progress and holds the internal state machine idle while low; drive it high externally if unused. |
| 4 | CS | input | Active-low Chip Select selects the device when asserted, and when deasserted deselects it into standby and puts SO in high impedance. |
| 5 | WP | input | Active-low Write Protect protects the sectors set in the Sector Protection Register against program and erase; it is internally pulled high and may be left floating if unused. |
| 6 | VCC | power_in | Device power supply, operated from 2.5V to 3.6V for the D option (2.3V to 3.6V for the F option), and operation at invalid VCC voltages should not be attempted. |
| 7 | GND | power_in | Ground reference for the power supply, to be connected to the system ground. |
| 8 | SO | output | Serial Output shifts data out on the falling edge of SCK and is in a high-impedance state whenever the device is deselected. |
## Key specifications
| Parameter | Value |
|---|---|
| Manufacturer | Dialog Semiconductor |
| Package | SOIC-8 |
| Category | Memory |
| Pins | 8 |
## Electrical characteristics
Limits as printed in the datasheet (page.json `metadata.characteristics` carries them as data).
| Parameter | Symbol | Min | Typ | Max | Unit | Conditions | Page |
|---|---|---|---|---|---|---|---|
| Supply voltage VCC (2.5V version) | VCC | 2.5 | | 3.6 | V | AT45DB161E 2.5V Version | 46 |
| Operating temperature (case), industrial | | -40 | | 85 | C | AT45DB161E 2.5V Version | 46 |
| All output voltages with respect to ground | | -0.6 | | 4.2 | V | Max VCC of 3.6V + 0.6V | 46 |
| All input voltages with respect to ground (excluding VCC pin, including NC pins) | | -0.6 | | 4.2 | V | Max VCC of 3.6V + 0.6V | 46 |
| Storage temperature | | -65 | | 150 | C | | 46 |
| Temperature under bias | | -55 | | 125 | C | | 46 |
| Ultra-Deep Power-Down current | IUDPD | | 0.4 | 1 | µA | CS= VCC. All other inputs at 0V or VCC | 47 |
| Deep Power-Down current | IDPD | | 5 | 12 | µA | CS= VCC. All other inputs at 0V or VCC | 47 |
| Standby current | ISB | | 25 | 50 | µA | CS= VCC. All other inputs at 0V or VCC | 47 |
| Active current, low power read (01h) operation | ICC1 | | 6 | 9 | mA | f = 1MHz; IOUT = 0mA | 47 |
| Active current, low power read (01h) operation | ICC1 | | 7 | 11 | mA | f = 15MHz; IOUT = 0mA | 47 |
| Active current, read operation | ICC2 | | 12 | 17 | mA | f = 50MHz; IOUT = 0mA | 47 |
| Active current, read operation | ICC2 | | 16 | 22 | mA | f = 85MHz; IOUT = 0mA | 47 |
| Active current, program operation | ICC3 | | 12 | 18 | mA | CS=VCC | 47 |
| Active current, erase operation | ICC4 | | 12 | 18 | mA | CS=VCC | 47 |
| Input load current | ILI | | | 1 | µA | All inputs at CMOS levels | 47 |
| Output leakage current | ILO | | | 1 | µA | All inputs at CMOS levels | 47 |
| Output low voltage | VOL | | | 0.4 | V | IOL = 100µA | 47 |
| SCK frequency | fSCK | | | 70 | MHz | AT45DB161E 2.5V Version | 48 |
| SCK frequency for continuous read (0x0B) | fCAR1 | | | 85 | MHz | AT45DB161E 2.5V Version | 48 |
| SCK frequency for continuous read (0x03) (low frequency) | fCAR2 | | | 50 | MHz | AT45DB161E 2.5V Version | 48 |
| SCK frequency for continuous read (low power mode, 01h opcode) | fCAR3 | | | 15 | MHz | AT45DB161E 2.5V Version | 48 |
| SCK frequency for continuous read (0x1B) | fCAR4 | | | 104 | MHz | AT45DB161E 2.5V Version | 48 |
| SCK high time | tWH | 4 | | | ns | AT45DB161E 2.5V Version | 48 |
| SCK low time | tWL | 4 | | | ns | AT45DB161E 2.5V Version | 48 |
| SCK rise time, peak-to-peak | tSCKR | | | 0.1 | V/ns | AT45DB161E 2.5V Version | 48 |
| SCK fall time, peak-to-peak | tSCKF | | | 0.1 | V/ns | AT45DB161E 2.5V Version | 48 |
| Minimum CS high time | tCS | 20 | | | ns | AT45DB161E 2.5V Version | 48 |
| CS setup time | tCSS | 5 | | | ns | AT45DB161E 2.5V Version | 48 |
| CS hold time | tCSH | 5 | | | ns | AT45DB161E 2.5V Version | 48 |
| Data in setup time | tSU | 2 | | | ns | AT45DB161E 2.5V Version | 48 |
| Data in hold time | tH | 1 | | | ns | AT45DB161E 2.5V Version | 48 |
| Output hold time | tHO | 0 | | | ns | AT45DB161E 2.5V Version | 48 |
| Output disable time | tDIS | | | 6 | ns | AT45DB161E 2.5V Version | 48 |
| Output valid | tV | | | 7 | ns | AT45DB161E 2.5V Version | 48 |
| WP low to protection enabled | tWPE | | | 1 | µs | AT45DB161E 2.5V Version | 48 |
| WP high to protection disabled | tWPD | | | 1 | µs | AT45DB161E 2.5V Version | 48 |
| Freeze sector lockdown time (from CS high) | tLOCK | | | 100 | µs | AT45DB161E 2.5V Version | 48 |
| CS high to ultra-deep power-down | tEUDPD | | | 4 | µs | AT45DB161E 2.5V Version | 48 |
| Minimum CS low time to exit ultra-deep power-down | tCSLU | 20 | | | ns | AT45DB161E 2.5V Version | 48 |
| Exit ultra-deep power-down time | tXUDPD | | | 180 | µs | AT45DB161E 2.5V Version | 48 |
| CS high to deep power-down | tEDPD | | | 2 | µs | AT45DB161E 2.5V Version | 48 |
| Resume from deep power-down time | tRDPD | | | 35 | µs | AT45DB161E 2.5V Version | 48 |
| Page to buffer transfer time | tXFR | | | 200 | µs | AT45DB161E 2.5V Version | 48 |
| Page to buffer compare time | tCOMP | | | 200 | µs | AT45DB161E 2.5V Version | 48 |
| RESET pulse width | tRST | 10 | | | µs | AT45DB161E 2.5V Version | 48 |
| RESET recovery time | tREC | 1 | | | µs | AT45DB161E 2.5V Version | 48 |
| Software reset time | tSWRST | | | 35 | µs | AT45DB161E 2.5V Version | 48 |
| Page erase and programming time (512/528 bytes) | tEP | | 17 | 25 | ms | | 49 |
| Page programming time | tP | | 3 | 4 | ms | | 49 |
| Page erase time | tPE | | 12 | 35 | ms | | 49 |
| Block erase time | tBE | | 45 | 100 | ms | | 49 |
| Sector erase time | tSE | | 1.4 | 2 | s | | 49 |
| Chip erase time | tCE | | 22 | 40 | s | | 49 |
| Suspend time, program | tSUSP | | 10 | 15 | µs | Program | 49 |
| Suspend time, erase | tSUSP | | 20 | 30 | µs | Erase | 49 |
| Resume time, program | tRES | | 10 | 15 | µs | Program | 49 |
| Resume time, erase | tRES | | 20 | 30 | µs | Erase | 49 |
| OTP security register program time | tOTPP | | 200 | 500 | µs | | 49 |
## CAD (KiCad official)
- Symbol: `AT45DB161E-SSHD-B`
- Footprint: `Package_SO:SOIC-8_3.9x4.9mm_P1.27mm`
- 3D model: SOIC-8 (KiCad packages3D, STEP)
- 3D model files: `at45db161e-sshd-b-etched.step` / `at45db161e-sshd-b-etched.glb` carry the MPN laser-etched on the die in a toggleable `Adom.LaserEtch` group (Fusion-ready); `at45db161e-sshd-b.step` / `at45db161e-sshd-b.glb` are the bare package body.
## Provenance
Data extracted from the manufacturer datasheet, not a distributor listing:
- **Datasheet:** [Dialog Semiconductor datasheet](docs/at45db161e-sshd-b-datasheet.pdf) (74 pp, sha256 `ac36775344285e29`, retrieved 2026-10-29, tier: lcsc)
- **Extractor:** parts-factory `2.0.0` / `extract_pins 0.3`, primary `claude-haiku-5-5` (text), consensus `claude-sonnet-5-5` (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
- **CAD:** KiCad official libraries (CC-BY-SA 4.0).
[Datasheet PDF](docs/at45db161e-sshd-b-datasheet.pdf)