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AT45DB041E-MHN-T

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Adesto Technologies NOR FLASH, UDFN-8-EP(5x6). Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.

componentmemoryat45db041e-mhn-tfactory-2.0.0extractor-text

Verified AT45DB041E-MHN-T

by Ray · last 2 Nov 2026 · 1 record · files match
SymbolFootprint3D modelPins

Verification log 1 record

2 Nov 2026RayPublished by the parts factory: tier lcsc, 9 pinsfiles match
SymbolFootprint3D modelPinsfor all variants
  • ✓component-page-verify: PASS
  • ✓cad_props: Datasheet, MPN and distributor properties match page.json
  • ✓component: AT45DB041E-MHN-T · UDFN-8-EP(5x6) · 9 pins
  • ✓copper: 16 copper pads, none touching another net
  • ✓datasheet: all 9 pin names found in the 70-page datasheet
  • ✓distributor: lcsc C2061634, digikey AT45DB041E-MHN-TTR-ND, mouser 988-AT45DB041E-MHN-T
  • ✓family: DFN-S-8-1EP_6x5mm_P1.27mm
  • ✓files: 7 declared files present
  • ✓hero: docs/hero.png 4000x2500
  • ✓lbr: OK: /tmp/cpv-ve25etud/x.lbr is a valid EAGLE .lbr with complete deviceset
  • ✓license: CC-BY-SA-4.0
  • ✓models_3d: 2 records
  • •package_fit (skip): no component.package_dims on the page: the model is unchecked against the datasheet drawing
  • ✓pads: 9 pins = 9 pads
  • ✓pose: 2 STEP(s) Z-up, seated, centred
  • ✓symbol: 9 pins agree
  • ✓visibility: public, source open
Evidencedatasheet
Verified files✓ at45db041e-mhn-t.kicad_sym✓ at45db041e-mhn-t.kicad_mod✓ at45db041e-mhn-t.step
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Ray Publish 0.1.0 67acfc6 2d ago

AT45DB041E-MHN-T

Adesto Technologies · NOR FLASH · UDFN-8-EP(5x6)

AT45DB041E-MHN-T from Adesto Technologies, in a UDFN-8-EP(5x6). Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 SI input Serial Input shifts command, address and data into the device and is latched on the rising edge of SCK, and it is ignored while CS is deasserted.
2 SCK input Serial Clock controls data flow to and from the device, with input latched on the rising edge and output on SO clocked out on the falling edge of SCK.
3 RESET input Active-low reset terminates the operation in progress and holds the internal state machine idle while low, and it should be driven high externally if unused.
4 CS input Active-low Chip Select selects the device, a high-to-low transition starts an operation, and when deasserted the device is deselected (normally standby) and SO goes high-impedance.
5 WP input Active-low Write Protect protects the sectors set in the Sector Protection Register against program and erase, is internally pulled high, and should preferably be tied to VCC if unused.
6 VCC power_in Device power supply pin for the 1.65V to 3.6V supply, where operation at invalid VCC voltages may produce spurious results.
7 GND power_in Ground reference for the power supply, to be connected to system ground.
8 SO tri_state Serial Output shifts data out of the device on the falling edge of SCK and is in a high-impedance state whenever the device is deselected.
9 EP passive Exposed pad (from the footprint; not named in the datasheet pin table).

Key specifications

Parameter Value
Manufacturer Adesto Technologies
Package UDFN-8-EP(5x6)
Category Memory
Pins 9

Electrical characteristics

Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).

Parameter Symbol Min Typ Max Unit Conditions Page
VCC Power Supply VCC 1.65 3.6 V 46
Operating Temperature (Case) Industrial -40 85 C 46
Storage Temperature -65 150 C 46
Temperature under Bias -55 125 C 46
All Output Voltages with Respect to Ground -0.6 4.2 V Max VCC of 3.6V + 0.6V 46
All Input Voltages with Respect to Ground -0.6 4.2 V Excluding VCC pin, including NC pins; Max VCC of 3.6V + 0.6V 46
Ultra-Deep Power-Down Current IUDPD 0.4 1 µA CS= VCC. All other inputs at 0V or VCC 47
Deep Power-Down Current IDPD 4.5 12 µA CS= VCC. All other inputs at 0V or VCC 47
Standby Current ISB 25 40 µA CS= VCC. All other inputs at 0V or VCC 47
Active Current, Low Power Read (01h) Operation ICC1 6 9 mA f = 1MHz; IOUT = 0mA 47
Active Current, Low Power Read (01h) Operation ICC1 7 10 mA f = 15MHz; IOUT = 0mA 47
Active Current, Read Operation ICC2 10 12 mA f = 50MHz; IOUT = 0mA 47
Active Current, Read Operation ICC2 12 15 mA f = 85MHz; IOUT = 0mA 47
Active Current, Program Operation ICC3 14 16 mA CS=VCC 47
Active Current, Erase Operation ICC4 8 12 mA CS=VCC 47
Input Load Current ILI 1 µA All inputs at CMOS levels 47
Output Leakage Current ILO 1 µA All inputs at CMOS levels 47
Output Low Voltage VOL 0.4 V IOL = 100µA 47
SCK Frequency fSCK 70 MHz 1.65 to 3.6V 48
SCK Frequency for Continuous Read (0x0B) fCAR1 70 MHz 1.65 to 3.6V 48
SCK Frequency for Continuous Read (0x03) (Low Frequency) fCAR2 40 MHz 1.65 to 3.6V 48
SCK Frequency for Continuous Read (Low Power Mode, 01h Opcode) fCAR3 15 MHz 1.65 to 3.6V 48
SCK Frequency for Continuous Read (0x1B) fCAR4 85 MHz 1.65 to 3.6V 48
SCK High Time tWH 4 ns 1.65 to 3.6V 48
SCK Low Time tWL 4 ns 1.65 to 3.6V 48
SCK Rise Time, Peak-to-peak tSCKR 0.1 V/ns 1.65 to 3.6V 48
SCK Fall Time, Peak-to-peak tSCKF 0.1 V/ns 1.65 to 3.6V 48
Minimum CS High Time tCS 20 ns 1.65 to 3.6V 48
CS Setup Time tCSS 6 ns 1.65 to 3.6V 48
CS Hold Time tCSH 5 ns 1.65 to 3.6V 48
Data In Setup Time tSU 2 ns 1.65 to 3.6V 48
Data In Hold Time tH 1 ns 1.65 to 3.6V 48
Output Hold Time tHO 0 ns 1.65 to 3.6V 48
Output Disable Time tDIS 8 ns 1.65 to 3.6V 48
Output Valid tV 7 ns 1.65 to 3.6V 48
WP Low to Protection Enabled tWPE 1 µs 1.65 to 3.6V 48
WP High to Protection Disabled tWPD 1 µs 1.65 to 3.6V 48
Freeze Sector Lockdown Time (from CS High) tLOCK 200 µs 1.65 to 3.6V 48
CS High to Ultra-Deep Power-Down tEUDPD 3 µs 1.65 to 3.6V 48
Minimum CS Low Time to Exit Ultra-Deep Power-Down tCSLU 20 ns 1.65 to 3.6V 48
Exit Ultra-Deep Power-Down Time tXUDPD 280 µs 1.65 to 3.6V 48
CS High to Deep Power-Down tEDPD 2 µs 1.65 to 3.6V 48
Resume from Deep Power-Down Time tRDPD 35 µs 1.65 to 3.6V 48
Page to Buffer Transfer Time tXFR 100 µs 1.65 to 3.6V 48
Page to Buffer Compare Time tCOMP 100 µs 1.65 to 3.6V 48
RESET Pulse Width tRST 10 µs 1.65 to 3.6V 48
RESET Recovery Time tREC 1 µs 1.65 to 3.6V 48
Software Reset Time tSWRST 35 µs 1.65 to 3.6V 48
Page Erase and Programming Time (256/264 bytes) tEP 10 25 ms 49
Page Programming Time tP 1.5 3 ms 49
Byte Programming Time tBP 8 µs 49
Page Erase Time tPE 12 25 ms 49
Block Erase Time tBE 30 35 ms 49
Sector Erase Time tSE 0.7 1.1 s 49
Chip Erase Time tCE 6 17 s 49
Suspend Time (Program) tSUSP 8 15 µs 49
Suspend Time (Erase) tSUSP 20 30 µs 49
Resume Time (Program) tRES 8 15 µs 49
Resume Time (Erase) tRES 20 30 µs 49
OTP Security Register Program Time tOTPP 200 500 µs 49

CAD (KiCad official)

  • Symbol: AT45DB041E-MHN-T
  • Footprint: Package_DFN_QFN:DFN-S-8-1EP_6x5mm_P1.27mm
  • 3D model: UDFN-8-EP(5x6) (KiCad packages3D, STEP)
  • 3D model files: at45db041e-mhn-t-etched.step / at45db041e-mhn-t-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); at45db041e-mhn-t.step / at45db041e-mhn-t.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: Adesto Technologies datasheet (70 pp, sha256 c630b496f0a3c17a, retrieved 2026-11-02, tier: lcsc)
  • Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-haiku-5-5 (text), consensus claude-sonnet-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF