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AT42QT2100-MUR

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Microchip Tech Pre-ordered MCUs, VQFN-32-EP(5x5). Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.

componentembedded processors & controllersat42qt2100-murfactory-2.0.0extractor-text

Verified AT42QT2100-MUR

by Ray · last 5 Nov 2026 · 1 record · files match
SymbolFootprint3D modelPins

Verification log 1 record

5 Nov 2026RayPublished by the parts factory: tier mfr, 33 pinsfiles match
SymbolFootprint3D modelPinsfor all variants
  • ✓component-page-verify: PASS
  • ✓cad_props: Datasheet, MPN and distributor properties match page.json
  • ✓component: AT42QT2100-MUR · VQFN-32-EP(5x5) · 33 pins
  • ✓copper: 33 copper pads, none touching another net
  • ✓datasheet: all 33 pin names found in the 44-page datasheet
  • ✓distributor: lcsc C618029, digikey AT42QT2100-MURTR-ND, mouser 556-AT42QT2100-MUR
  • ✓family: QFN-32-1EP_5x5mm_P0.5mm_EP3.3x3.3mm
  • ✓files: 7 declared files present
  • ✓hero: docs/hero.png 4000x2500
  • ✓lbr: OK: /tmp/cpv-eda8hlsz/x.lbr is a valid EAGLE .lbr with complete deviceset
  • ✓license: CC-BY-SA-4.0
  • ✓models_3d: 2 records
  • •package_fit (skip): no component.package_dims on the page: the model is unchecked against the datasheet drawing
  • ✓pads: 33 pins = 33 pads
  • ✓pose: 2 STEP(s) Z-up, seated, centred
  • ✓symbol: 33 pins agree
  • ✓symbol_text: no pin names collide
  • ✓visibility: public, source open
Evidencedatasheet
Verified files✓ at42qt2100-mur.kicad_sym✓ at42qt2100-mur.kicad_mod✓ at42qt2100-mur.step
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AT42QT2100-MUR

Microchip Tech · Pre-ordered MCUs · VQFN-32-EP(5x5)

AT42QT2100-MUR from Microchip Tech, in a VQFN-32-EP(5x5). Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 SNSKB2 bidirectional Sense pin for the B group; connect to any CsB + key, or leave open if unused.
2 SNSB3 bidirectional Sense pin for the B group; connect to CsB3, or leave open if unused.
3 SNSKB3 bidirectional Sense pin for the B group; connect to any CsB + key, or leave open if unused.
4 VDD power_in Power supply; the device operates from 2.0 V to 5.5 V.
5 VSS power_in Ground.
6 SNSKB4 bidirectional Sense pin for the B group; connect to any CsB + key, or leave open if unused.
7 SNSB4 bidirectional Sense pin for the B group; connect to CsB4, or leave open if unused.
8 SNSB5 bidirectional Sense pin for the B group; connect to CsB5, or leave open if unused.
9 SNSKB5 bidirectional Sense pin for the B group; connect to any CsB + key, or leave open if unused.
10 SNSKB6 bidirectional Sense pin for the B group; connect to any CsB + key, or leave open if unused.
11 SNSKB7 bidirectional Sense pin for the B group; connect to any CsB + key, or leave open if unused.
12 SNSB6 bidirectional Sense pin for the B group; connect to CsB6, or leave open if unused.
13 SNSB7 bidirectional Sense pin for the B group; connect to CsB7, or leave open if unused.
14 SS input SPI slave select, active low.
15 MOSI input SPI master out / slave in data input.
16 MISO tri_state SPI master in / serial out data output; this CMOS output can float during Reset, Sleep or LP modes.
17 SCK input SPI clock input.
18 VDD power_in Power supply; the device operates from 2.0 V to 5.5 V.
19 DRDY tri_state SPI data-ready handshake line; this CMOS output can float during Reset, Sleep or LP modes, and may need a pull-down resistor; leave open if unused.
20 CHANGE tri_state State change notification output; this CMOS output can float during Reset, Sleep or LP modes, and may need a pull-down resistor; leave open if unused.
21 VSS power_in Ground.
22 SPREAD output Spread-spectrum enable: connect to Vdd (high) to enable or to Vss (low) to disable; CMOS open-drain output with pull-up to Vdd.
23 SNSA1 bidirectional Sense pin for the A group; connect to CsA1, or leave open if unused.
24 SNSKA1 bidirectional Sense pin for the A group; connect to any CsA + slider/wheel, or leave open if unused.
25 SNSA2 bidirectional Sense pin for the A group; connect to CsA2, or leave open if unused.
26 SNSKA2 bidirectional Sense pin for the A group; connect to any CsA + slider/wheel, or leave open if unused.
27 SNSA3 bidirectional Sense pin for the A group; connect to CsA3, or leave open if unused.
28 SNSKA3 bidirectional Sense pin for the A group; connect to any CsA + slider/wheel, or leave open if unused.
29 RESET input Reset, active low; connect to Vdd via a resistor.
30 SNSB1 bidirectional Sense pin for the B group; connect to CsB1, or leave open if unused.
31 SNSKB1 bidirectional Sense pin for the B group; connect to any CsB + key, or leave open if unused.
32 SNSB2 bidirectional Sense pin for the B group; connect to CsB2, or leave open if unused.
33 EP passive Exposed pad (from the footprint; not named in the datasheet pin table).

Key specifications

Parameter Value
Manufacturer Microchip Tech
Package VQFN-32-EP(5x5)
Category Embedded Processors & Controllers
Pins 33

Electrical characteristics

Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).

Parameter Symbol Min Typ Max Unit Conditions Page
Supply voltage (absolute maximum) VDD -0.3 6 V 30
Max continuous pin current, any control or drive pin -20 20 mA 30
Voltage forced onto any pin -0.3 V Printed maximum is (Vdd + 0.3) V 30
Operating temperature -40 85 °C 30
Storage temperature -50 125 °C 30
Supply voltage (recommended operating) VDD 2 5.5 V 30
Short-term supply ripple + noise -20 20 mV/s 30
Long-term supply stability -100 100 mV 30
Cs range, keys 1 100 nF 30
Cs range, slider/wheel 4.7 220 nF 30
Cx range 0 50 pF 30
Low input logic level Vil 0 0.3 × Vdd Vdd = 5.0V, Cs keys = 4.7 nF, Cs slider/wheel = 15 nF 31
High input logic level Vhl 0.7 × Vdd Vdd = 5.0V, Cs keys = 4.7 nF, Cs slider/wheel = 15 nF 31
Low output voltage Vol 0.5 V 7 mA sink; Vdd = 5.0V, Cs keys = 4.7 nF, Cs slider/wheel = 15 nF 31
High output voltage Voh -0.5 V 2.5 mA source; min printed as Vdd, 0.5 31
Input leakage current Iil -1 1 µA Vdd = 5.0V, Cs keys = 4.7 nF, Cs slider/wheel = 15 nF 31
External reset low pulse width Trst 2 µs Vdd = 5.0V, Cs keys = 4.7 nF, Cs slider/wheel = 15 nF 31
Start-up to SPI time Tsu 50 60 ms From cold start; Vdd = 5.0V, Cs keys = 4.7 nF, Cs slider/wheel = 15 nF 31
Recalibration time Trc 300 ms Depends on ground loading of electrodes and Cs selection 31
Burst center frequency Fc 100 kHz Spread spectrum disabled 31
Burst center frequency Fc 80 kHz Spread spectrum enabled 31
Burst modulation, percent Fm 15 % Total deviation 31
Sample pulse duration Tpc 2.66 µs Spread spectrum disabled 31
Sample pulse duration Tpc 5.85 µs Spread spectrum enabled 31
Acquire burst duration Tbd 20 ms Spread spectrum disabled (total for all 3 acquire burst groups) 31
Acquire burst duration Tbd 25 ms Spread spectrum enabled (total for all 3 acquire burst groups) 31
Response time, Free Run mode, DI 6 samples Tdf6 120 ms Free Run mode, DI 6 samples; spread spectrum disabled 31
Response time, Free Run mode, DI 2 samples Tdf2 40 ms Free Run mode, DI 2 samples; spread spectrum disabled 31
Response time, LP mode Tdl 280 ms LP Mode 2, DI = six counts 31
Release time, all modes Tdr 40 ms End of touch 31
Acquisition resolution Ar 14 bits Vdd = 5.0V, Cs keys = 4.7 nF, Cs slider/wheel = 15 nF 31

Materials and finish

As the datasheet states them (page.json metadata.appearance; the 3D model's colours follow it).

Part Material Colour / plating Datasheet says Page
housing PPS The Cs capacitors can be virtually any plastic film or low to medium-K ceramic capacitor. Acceptable capacitor types for most uses include PPS film, polypropylene film, and NP0 and X7R ceramics. Lower 9
contacts gold AT42QT2100-MUR 32-pin 5 × 5 mm MLF RoHS compliant IC AT42QT2100-AU 32-pin 7 × 7 mm TQFP RoHS compliant IC 40

CAD (KiCad official)

  • Symbol: AT42QT2100-MUR
  • Footprint: Package_DFN_QFN:QFN-32-1EP_5x5mm_P0.5mm_EP3.3x3.3mm
  • 3D model: VQFN-32-EP(5x5) (KiCad packages3D, STEP)
  • 3D model files: at42qt2100-mur-etched.step / at42qt2100-mur-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); at42qt2100-mur.step / at42qt2100-mur.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: Microchip Tech datasheet (44 pp, sha256 1b9e3b9c9558e201, retrieved 2026-11-05, tier: manufacturer)
  • Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-haiku-5-5 (text), consensus claude-sonnet-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF