component

AT32F437VMT7

Public Made by Adom

by adom

ARTERY Microcontrollers (MCU/MPU/SOC), LQFP-100(14x14). Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.

componentembedded processors & controllersat32f437vmt7factory-2.0.0extractor-text
Overview Files Discover Packages Releases Dependencies Issues Breadcrumbs Pull Requests Activity
main
Download ZIP Propose a change
Generated by kicad-footprint-generator · KiCad file format 20260206
Name Last commit message Last updated
docs Publish 0.1.0 · Ray 9d ago
viewers at32f437vmt7: viewers · Ray 9d ago
at32f437vmt7-etched.glb Publish 0.1.0 · Ray 9d ago
at32f437vmt7-etched.step at32f437vmt7: factory component page (tier=lcsc) · Ray 9d ago
at32f437vmt7-hero.glb at32f437vmt7: hero GLB from the etched model (keeps the MPN mark) · Ray 9d ago
at32f437vmt7-hero.overlay.json Publish 0.1.0 · Ray 9d ago
at32f437vmt7.glb Publish 0.1.0 · Ray 9d ago
at32f437vmt7.kicad_mod Publish 0.1.0 · Ray 9d ago
at32f437vmt7.kicad_sym Publish 0.1.0 · Ray 9d ago
at32f437vmt7.lbr Publish 0.1.0 · Ray 9d ago
at32f437vmt7.step Publish 0.1.0 · Ray 9d ago
package.json Publish 0.1.0 · Ray 9d ago
page.json Set visibility: public · Ray 9d ago
README.md Publish 0.1.0 · Ray 9d ago

AT32F437VMT7

ARTERY · Microcontrollers (MCU/MPU/SOC) · LQFP-100(14x14)

AT32F437VMT7 from ARTERY, in a LQFP-100(14x14). Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 PE2 bidirectional 5 V-tolerant (FT) GPIO; multiplexed functions include TMR3_EXT, SPI4_SCK, I2S4_CK, TMR20_CH1, QSPI1_IO2, XMC_SDNCAS, EMAC_MII_TXD3 and XMC_A23.
2 PE3 bidirectional 5 V-tolerant (FT) GPIO; functions include TMR3_CH1, TMR20_CH2, XMC_A19 and DVP_D9.
3 PE4 bidirectional 5 V-tolerant (FT) GPIO; functions include CLKOUT1, TMR3_CH2, SPI4_CS, I2S4_WS, TMR20_CH1C, XMC_A20 and DVP_D4.
4 PE5 bidirectional 5 V-tolerant (FT) GPIO; functions include TMR3_CH3, TMR9_CH1, SPI4_MISO, TMR20_CH2C, XMC_A21 and DVP_D6.
5 PE6 bidirectional 5 V-tolerant (FT) GPIO; functions include TMR3_CH4, TMR9_CH2, SPI4_MOSI, I2S4_SD, TMR20_CH3C, XMC_SDNRAS, XMC_A22 and DVP_D7.
6 VBAT power_in Battery supply for the VBAT domain (LEXT, ERTC and backup registers) with a range of 1.62 to 3.6 V; it supplies that domain from VDD when no battery is present.
7 PC13 bidirectional 5 V-tolerant (FT) GPIO on the battery domain, powered through a power switch that limits it to 3 mA as an output so it cannot drive LEDs; alternate functions include ERTC_AF1 and WKUP2.
8 PC14 / LEXT_IN bidirectional Standard-level (TC) GPIO on the battery domain that doubles as the LEXT_IN 32.768 kHz oscillator input; power-switched and limited to 3 mA as an output.
9 PC15 / LEXT_OUT bidirectional Standard-level (TC) GPIO on the battery domain that doubles as the LEXT_OUT 32.768 kHz oscillator output; power-switched and limited to 3 mA as an output.
10 VSS power_in Digital ground.
11 VDD power_in Digital supply for the GPIO pins and internal LDO, specified at 2.6 to 3.6 V.
12 PH0 / HEXT_IN bidirectional Standard-level (TC) GPIO with alternate function I2C1_SDA, and additional function HEXT_IN as the 4 to 25 MHz high-speed crystal oscillator input.
13 PH1 / HEXT_OUT bidirectional Standard-level (TC) GPIO with alternate function I2C1_SCL, and additional function HEXT_OUT as the 4 to 25 MHz high-speed crystal oscillator output.
14 NRST bidirectional Reset pin with built-in weak pull-up (R type) that acts as the active-low device reset input and internal reset output; the external reset network must keep it below VIL(NRST) max of 0.8 V to reset the MCU.
15 PC0 bidirectional 5 V-tolerant analog-capable GPIO (FTa, only 5 V tolerant in input modes, analog-mode input must stay below VDD+0.3 V); alternate functions include I2C3_SCL, UART7_TX, SDIO2_D0 and XMC_SDNWE, additional ADC123_IN10 as an ADC fast channel.
16 PC1 bidirectional 5 V-tolerant analog-capable GPIO (FTa, analog-mode input must stay below VDD+0.3 V); alternate functions include I2C3_SDA, SPI3_MOSI, I2S3_SD, SPI2_MOSI, I2S2_SD, UART7_RX, SDIO2_D1 and EMAC_MDC, additional ADC123_IN11 as an ADC fast channel.
17 PC2 bidirectional 5 V-tolerant analog-capable GPIO (FTa, analog-mode input must stay below VDD+0.3 V); alternate functions include TMR20_CH2, SPI2_MISO, I2S2_SDEXT, UART8_TX, SDIO2_D2, EMAC_MII_TXD2, XMC_SDCS0 and XMC_NWE, additional ADC123_IN12 as an ADC fast channel.
18 PC3 bidirectional 5 V-tolerant analog-capable GPIO (FTa, analog-mode input must stay below VDD+0.3 V); alternate functions include SPI2_MOSI, I2S2_SD, UART8_RX, QSPI2_IO1, SDIO2_D3, EMAC_MII_TX_CLK, XMC_SDCKE0 and XMC_A0, additional ADC123_IN13 as an ADC fast channel.
19 NC unconnected Not connected (未连接) on the LQFP100 package.
20 VSSA / VREF- power_in Analog ground and negative reference voltage for the ADC/DAC; VSSA must be connected to VSS.
21 VREF+ power_in Positive reference voltage input for the ADC and DAC; the DAC specifies VREF+ from 2.0 to 3.6 V and it may be internally tied to VDDA depending on package.
22 VDDA power_in Analog supply for the ADC and DAC, 2.6 to 3.6 V, which must be the same as VDD and connected to it.
23 PA0 bidirectional 5 V-tolerant analog-capable GPIO (FTa); alternate functions include TMR2_CH1, TMR2_EXT, TMR5_CH1, TMR8_EXT, I2C2_SCL, USART2_CTS, UART4_TX and EMAC_MII_CRS, additional ADC123_IN0 (ADC fast channel), ERTC_AF2 and WKUP1.
24 PA1 bidirectional 5 V-tolerant analog-capable GPIO (FTa); alternate functions include TMR2_CH2, TMR5_CH2, I2C2_SDA, SPI4_MOSI, I2S4_SD, USART2_RTS_DE, UART4_RX, QSPI1_IO3, EMAC_MII_RX_CLK and EMAC_RMII_REF_CLK, additional ADC123_IN1 (ADC fast channel).
25 PA2 bidirectional 5 V-tolerant analog-capable GPIO (FTa); alternate functions include TMR2_CH3, TMR5_CH3, TMR9_CH1, USART2_TX, SDIO2_CK, EMAC_MDIO and XMC_D4, additional ADC123_IN2.
26 PA3 bidirectional 5 V-tolerant analog-capable GPIO (FTa); alternate functions include TMR2_CH4, TMR5_CH4, TMR9_CH2, I2S2_MCK, USART2_RX, QSPI2_IO3, SDIO2_CMD, EMAC_MII_COL and XMC_D5, additional ADC123_IN3.
27 VSS power_in Digital ground.
28 VDD power_in Digital supply for the GPIO pins and internal LDO, specified at 2.6 to 3.6 V.
29 PA4 bidirectional 5 V-tolerant analog-capable GPIO (FTa); alternate functions include SPI1_CS, I2S1_WS, SPI3_CS, I2S3_WS, USART2_CK, USART6_TX, SDIO2_D4, SDIO2_D0, OTGFS2_SOF, DVP_HSYNC and XMC_D6, additional ADC12_IN4 and DAC1_OUT.
30 PA5 bidirectional 5 V-tolerant analog-capable GPIO (FTa); alternate functions include TMR2_CH1, TMR2_EXT, TMR8_CH1C, SPI1_SCK, I2S1_CK, USART6_RX, QSPI2_IO2, SDIO2_D5, SDIO2_D1 and XMC_D7, additional ADC12_IN5 and DAC2_OUT.
31 PA6 bidirectional 5 V-tolerant analog-capable GPIO (FTa); alternate functions include TMR1_BRK, TMR3_CH1, TMR8_BRK, SPI1_MISO, I2S2_MCK, USART3_CTS, TMR13_CH1, QSPI1_IO0, SDIO2_D2, SDIO1_CMD, DVP_PCLK and SDIO2_D6, additional ADC12_IN6.
32 PA7 bidirectional 5 V-tolerant analog-capable GPIO (FTa); alternate functions include TMR1_CH1C, TMR3_CH2, TMR8_CH1C, SPI1_MOSI, I2S1_SD, TMR14_CH1, QSPI1_IO1, EMAC_MII_RX_DV, EMAC_RMII_CRS_DV, XMC_SDNWE, SDIO2_D3 and SDIO2_D7, additional ADC12_IN7.
33 PC4 bidirectional 5 V-tolerant analog-capable GPIO (FTa); alternate functions include TMR9_CH1, I2S1_MCK, USART3_TX, QSPI1_IO2, EMAC_MII_RXD0, EMAC_RMII_RXD0, XMC_SDCS0, SDIO2_CK and XMC_NE4, additional ADC12_IN14.
34 PC5 bidirectional 5 V-tolerant analog-capable GPIO (FTa); alternate functions include TMR9_CH2, I2C1_SMBA, USART3_RX, QSPI1_IO3, EMAC_MII_RXD1, EMAC_RMII_RXD1, XMC_SDCKE0, SDIO2_CMD and XMC_NOE, additional ADC12_IN15.
35 PB0 bidirectional 5 V-tolerant analog-capable GPIO (FTa); alternate functions include TMR1_CH2C, TMR3_CH3, TMR8_CH2C, I2S1_MCK, USART2_RX, SPI3_MOSI, I2S3_SD, USART3_CK, QSPI2_IO0, QSPI1_IO0, EMAC_MII_RXD2 and SDIO1_D1, additional ADC12_IN8.
36 PB1 bidirectional 5 V-tolerant analog-capable GPIO (FTa); alternate functions include TMR1_CH3C, TMR3_CH4, TMR8_CH3C, SPI2_SCK, I2S2_CK, USART3_RTS_DE, QSPI1_SCK, QSPI2_SCK, EMAC_MII_RXD3 and SDIO1_D2, additional ADC12_IN9.
37 PB2 / BOOT1 bidirectional 5 V-tolerant (FT) GPIO that also serves as the BOOT1 boot-mode select pin; alternate functions include TMR2_CH4, TMR20_CH1, I2C3_SMBA, SPI3_MOSI, I2S3_SD, QSPI1_SCK and SDIO1_CK.
38 PE7 bidirectional 5 V-tolerant (FT) GPIO; functions include TMR1_EXT, UART7_RX, QSPI2_IO0 and XMC_D4.
39 PE8 bidirectional 5 V-tolerant (FT) GPIO; functions include TMR1_CH1C, UART4_TX, UART7_TX, QSPI2_IO1 and XMC_D5.
40 PE9 bidirectional 5 V-tolerant (FT) GPIO; functions include TMR1_CH1, UART4_RX, QSPI2_IO2 and XMC_D6.
41 PE10 bidirectional 5 V-tolerant (FT) GPIO; functions include TMR1_CH2C, UART5_TX, QSPI2_IO3 and XMC_D7.
42 PE11 bidirectional 5 V-tolerant (FT) GPIO; functions include TMR1_CH2, SPI4_CS, I2S4_WS, UART5_RX and XMC_D8.
43 PE12 bidirectional 5 V-tolerant (FT) GPIO; functions include TMR1_CH3C, SPI1_CS, I2S1_WS, SPI4_SCK, I2S4_CK and XMC_D9.
44 PE13 bidirectional 5 V-tolerant (FT) GPIO; functions include TMR1_CH3, SPI1_SCK, I2S1_CK, SPI4_MISO and XMC_D10.
45 PE14 bidirectional 5 V-tolerant (FT) GPIO; functions include TMR1_CH4, SPI1_MISO, SPI4_MOSI, I2S4_SD and XMC_D11.
46 PE15 bidirectional 5 V-tolerant (FT) GPIO; functions include TMR1_BRK, SPI1_MOSI, I2S1_SD and XMC_D12.
47 PB10 bidirectional 5 V-tolerant GPIO (FTf, also rated for 20 mA sink); functions include TMR2_CH3, I2C2_SCL, SPI2_SCK, I2S2_CK, I2S3_MCK, USART3_TX, QSPI1_CS, QSPI1_IO1, EMAC_MII_RX_ER, SDIO1_D7 and XMC_NOE.
48 PB11 bidirectional 5 V-tolerant (FT) GPIO; functions include TMR2_CH4, TMR5_CH4, I2C2_SDA, USART3_RX, QSPI1_IO0, EMAC_MII_TX_EN and EMAC_RMII_TX_EN.
49 PH3 bidirectional 5 V-tolerant (FT) GPIO; functions include TMR5_CH2, I2C2_SDA, UART4_TX and QSPI1_IO1.
50 VDD power_in Digital supply for the GPIO pins and internal LDO, specified at 2.6 to 3.6 V.
51 PB12 bidirectional 5 V-tolerant (FT) GPIO; functions include TMR1_BRK, TMR5_CH1, I2C2_SMBA, SPI2_CS, I2S2_WS, SPI4_CS, I2S4_WS, SPI3_SCK, I2S3_CK, USART3_CK, CAN2_RX, EMAC_MII_TXD0, OTGFS2_ID and XMC_D13.
52 PB13 bidirectional 5 V-tolerant (FT) GPIO; functions include TMR1_CH1C, I2C3_SMBA, SPI2_SCK, I2S2_CK, SPI4_SCK, I2S4_CK, I2C3_SCL, USART3_CTS, CAN2_TX, EMAC_MII_TXD1 and OTGFS2_VBUS.
53 PB14 bidirectional Standard-level (TC) GPIO, not 5 V tolerant; functions include TMR1_CH2C, TMR8_CH2C, I2C3_SDA, SPI2_MISO, I2S2_SDEXT, USART3_RTS_DE, TMR12_CH1, OTGFS2_D-, SDIO1_D6 and XMC_D0.
54 PB15 bidirectional Standard-level (TC) GPIO; functions include ERTC_REFIN, TMR1_CH3C, TMR8_CH3C, I2C3_SCL, SPI2_MOSI, I2S2_SD, TMR12_CH2, OTGFS2_D+ and SDIO1_CK.
55 PD8 bidirectional 5 V-tolerant (FT) GPIO; functions include USART3_TX, EMAC_MII_RX_DV, EMAC_RMII_CRS_DV and XMC_D13.
56 PD9 bidirectional 5 V-tolerant (FT) GPIO; functions include USART3_RX, EMAC_MII_RXD0, MAC_RMII_RXD0 (as printed in the datasheet) and XMC_D14.
57 PD10 bidirectional 5 V-tolerant (FT) GPIO; functions include USART3_CK, EMAC_MII_RXD1, EMAC_RMII_RXD1 and XMC_D15.
58 PD11 bidirectional 5 V-tolerant (FT) GPIO; functions include I2C2_SMBA, USART3_CTS, QSPI1_IO0, XMC_A14, XMC_SDBA0, EMAC_MII_RXD2 and XMC_A16_CLE.
59 PD12 bidirectional 5 V-tolerant GPIO (FTf, also rated for 20 mA sink); functions include TMR4_CH1, I2C2_SCL, USART3_RTS_DE, QSPI1_IO1, XMC_A15, XMC_SDBA1, EMAC_MII_RXD3 and XMC_A17_ALE.
60 PD13 bidirectional 5 V-tolerant GPIO (FTf, also rated for 20 mA sink); functions include TMR4_CH2, I2C2_SDA, UART8_TX, QSPI1_IO3, XMC_SDCLK and XMC_A18.
61 PD14 bidirectional 5 V-tolerant GPIO (FTf, also rated for 20 mA sink); functions include TMR4_CH3, I2C3_SCL, UART8_RX and XMC_D0.
62 PD15 bidirectional 5 V-tolerant GPIO (FTf, also rated for 20 mA sink); functions include TMR4_CH4, I2C3_SDA and XMC_D1.
63 PC6 bidirectional 5 V-tolerant (FT) GPIO; functions include TMR3_CH1, TMR8_CH1, I2C1_SCL, I2S2_MCK, USART6_TX, XMC_A0, SDIO1_D6, DVP_D0 and XMC_D1.
64 PC7 bidirectional 5 V-tolerant (FT) GPIO; functions include TMR3_CH2, TMR8_CH2, I2C1_SDA, SPI2_SCK, I2S2_CK, I2S3_MCK, USART6_RX, XMC_A1, SDIO1_D7 and DVP_D1.
65 PC8 bidirectional 5 V-tolerant (FT) GPIO; functions include TMR3_CH3, TMR8_CH3, I2S4_MCK, TMR20_CH3, UART8_TX, USART6_CK, QSPI1_IO2, XMC_A2, SDIO1_D0 and DVP_D2.
66 PC9 bidirectional 5 V-tolerant (FT) GPIO; functions include CLKOUT2, TMR3_CH4, TMR8_CH4, I2C3_SDA, UART8_RX, QSPI1_IO0, XMC_A3, OTGFS2_OE, SDIO1_D1 and DVP_D3.
67 PA8 bidirectional 5 V-tolerant (FT) GPIO; functions include CLKOUT1, TMR1_CH1, I2C3_SCL, USART1_CK, USART2_TX, OTGFS1_SOF, SDIO1_D1 and XMC_A4.
68 PA9 bidirectional 5 V-tolerant (FT) GPIO; functions include TMR1_CH2, I2C3_SMBA, SPI2_SCK, I2S2_CK, USART1_TX, I2C1_SCL, OTGFS1_VBUS, SDIO1_D2 and DVP_D0.
69 PA10 bidirectional 5 V-tolerant (FT) GPIO; functions include TMR1_CH3, SPI2_MOSI, I2S2_SD, I2S4_MCK, USART1_RX, I2C1_SDA, OTGFS1_ID and DVP_D1.
70 PA11 bidirectional Standard-level (TC) GPIO, not 5 V tolerant; functions include TMR1_CH4, I2C2_SCL, SPI2_CS, I2S2_WS, SPI4_MISO, USART1_CTS, USART6_TX, CAN1_RX, OTGFS1_D- and DVP_D2.
71 PA12 bidirectional Standard-level (TC) GPIO, not 5 V tolerant; functions include TMR1_EXT, I2C2_SDA, SPI2_MISO, USART1_RTS_DE, USART6_RX, CAN1_TX, OTGFS1_D+ and DVP_D3.
72 PA13 bidirectional 5 V-tolerant (FT) GPIO whose reset function is JTMS/SWDIO; other functions include IR_OUT, SPI3_MISO and OTGFS1_OE.
73 PH2 bidirectional 5 V-tolerant (FT) GPIO; functions include TMR5_CH1, I2C2_SCL, UART4_RX and QSPI1_IO0.
74 VSS power_in Digital ground.
75 VDD power_in Digital supply for the GPIO pins and internal LDO, specified at 2.6 to 3.6 V.
76 PA14 bidirectional 5 V-tolerant (FT) GPIO whose reset function is JTCK/SWCLK; other functions include SPI3_MOSI, I2S3_SD and USART2_TX.
77 PA15 bidirectional 5 V-tolerant (FT) GPIO whose reset function is JTDI; other functions include TMR2_CH1, TMR2_EXT, SPI1_CS, I2S1_WS, SPI3_CS, I2S3_WS, USART1_TX, USART2_RX, QSPI2_IO1, QSPI1_IO2, XMC_NE2 and XMC_NCE3.
78 PC10 bidirectional 5 V-tolerant (FT) GPIO; functions include TMR5_CH2, SPI3_SCK, I2S3_CK, USART3_TX, UART4_TX, QSPI1_IO1, SDIO1_D2 and DVP_D8.
79 PC11 bidirectional 5 V-tolerant (FT) GPIO; functions include TMR5_CH3, I2S3_SDEXT, SPI3_MISO, USART3_RX, UART4_RX, QSPI1_CS, SDIO1_D3, DVP_D4 and XMC_D2.
80 PC12 bidirectional 5 V-tolerant (FT) GPIO; functions include TMR11_CH1, I2C2_SDA, SPI3_MOSI, I2S3_SD, USART3_CK, UART5_TX, SDIO1_CK, DVP_D9 and XMC_D3.
81 PD0 bidirectional 5 V-tolerant (FT) GPIO; functions include SPI4_MISO, SPI3_MOSI, I2S3_SD, SPI2_CS, I2S2_WS, CAN1_RX, XMC_A5 and XMC_D2.
82 PD1 bidirectional 5 V-tolerant (FT) GPIO; functions include SPI2_SCK, I2S2_CK, SPI2_CS, I2S2_WS, CAN1_TX, XMC_A6 and XMC_D3.
83 PD2 bidirectional 5 V-tolerant (FT) GPIO; functions include TMR3_EXT, USART3_RTS_DE, UART5_RX, XMC_A7, SDIO1_CMD, DVP_D11 and XMC_NWE.
84 PD3 bidirectional 5 V-tolerant (FT) GPIO; functions include SPI2_SCK, I2S2_CK, SPI2_MISO, USART2_CTS, QSPI1_SCK, XMC_A8, XMC_CLK and DVP_D5.
85 PD4 bidirectional 5 V-tolerant (FT) GPIO; functions include SPI2_MOSI, I2S2_SD, USART2_RTS_DE, XMC_A9 and XMC_NOE.
86 PD5 bidirectional 5 V-tolerant (FT) GPIO; functions include USART2_TX, XMC_A10 and XMC_NWE.
87 PD6 bidirectional 5 V-tolerant (FT) GPIO; functions include SPI3_MOSI, I2S3_SD, USART2_RX, XMC_A11, XMC_NWAIT and DVP_D10.
88 PD7 bidirectional 5 V-tolerant (FT) GPIO; functions include USART2_CK, XMC_A12, XMC_NE1 and XMC_NCE2.
89 PB3 / JTDO bidirectional 5 V-tolerant GPIO (FTf, also rated for 20 mA sink) whose reset function is JTDO; other functions include TMR2_CH2, I2C2_SDA, SPI1_SCK, I2S1_CK, SPI3_SCK, I2S3_CK, USART1_RX, UART7_RX, QSPI1_IO3, DVP_D4 and SWO.
90 PB4 / NJTRST bidirectional 5 V-tolerant (FT) GPIO whose reset function is NJTRST; other functions include TMR3_CH1, I2C3_SDA, SPI1_MISO, SPI3_MISO, I2S3_SDEXT, UART7_TX, SDIO1_D0 and DVP_D5.
91 PB5 bidirectional 5 V-tolerant (FT) GPIO; functions include TMR3_CH2, I2C1_SMBA, SPI1_MOSI, I2S1_SD, SPI3_MOSI, I2S3_SD, USART1_CK, UART5_RX, CAN2_RX, EMAC_PPS_OUT, XMC_SDCKE1, DVP_D10 and SDIO1_D3.
92 PB6 bidirectional 5 V-tolerant (FT) GPIO; functions include TMR4_CH1, I2C1_SCL, I2S1_MCK, SPI4_CS, I2S4_WS, USART1_TX, UART5_TX, CAN2_TX, QSPI1_CS, XMC_SDCS1, DVP_D5 and SDIO1_D0.
93 PB7 bidirectional 5 V-tolerant (FT) GPIO; functions include TMR4_CH2, TMR8_BRK, I2C1_SDA, SPI4_SCK, I2S4_CK, USART1_RX, QSPI2_IO1, XMC_NADV, DVP_VSYNC and SDIO1_D0.
94 BOOT0 input Dedicated BOOT0 boot-mode input with a built-in weak pull-down that cannot be disabled.
95 PB8 bidirectional 5 V-tolerant (FT) GPIO; functions include TMR2_CH1, TMR2_EXT, TMR4_CH3, TMR10_CH1, I2C1_SCL, SPI4_MISO, UART5_RX, CAN1_RX, QSPI2_CS, EMAC_MII_TXD3, SDIO1_D4 and DVP_D6.
96 PB9 bidirectional 5 V-tolerant GPIO (FTf, also rated for 20 mA sink); functions include IR_OUT, TMR2_CH2, TMR4_CH4, TMR11_CH1, I2C1_SDA, SPI2_CS/I2S2_WS, SPI4_MOSI, I2S4_SD, I2C2_SDA, UART5_TX, CAN1_TX, QSPI1_CS, SDIO1_D5 and DVP_D7.
97 PE0 bidirectional 5 V-tolerant (FT) GPIO; functions include TMR4_EXT, TMR20_EXT, UART8_RX, XMC_LB, XMC_SDDQML and DVP_D2.
98 PE1 bidirectional 5 V-tolerant (FT) GPIO; functions include TMR1_CH2C, TMR20_CH4, UART8_TX, XMC_UB, XMC_SDDQMH and DVP_D3.
99 VSS power_in Digital ground.
100 VDD power_in Digital supply for the GPIO pins and internal LDO, specified at 2.6 to 3.6 V.

Key specifications

Parameter Value
Manufacturer ARTERY
Package LQFP-100(14x14)
Category Embedded Processors & Controllers
Pins 100

Electrical characteristics

Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).

Parameter Symbol Min Typ Max Unit Conditions Page
External main supply voltage (VDDx-VSS) VDDx-VSS -0.3 4 V 47
Input voltage on FTa pin, input floating/pull-up/pull-down mode VIN -0.3 6 V FTa pin, input floating/pull-up/pull-down mode; min printed as VSS-0.3 47
Input voltage on TC pin VIN -0.3 4 V TC pin; min printed as VSS-0.3 47
Voltage difference between supply pins /ΔVDDx/ 50 mV 47
Voltage difference between ground pins /VSSx-VSS/ 50 mV 47
External main supply current (incl. VDDA and VDD) IVDD 250 mA 47
Total current through VSS ground line (outflow) IVSS 250 mA 47
Output sink current on any GPIO and control pin IIO 25 mA 47
Output current on any GPIO and control pin IIO -25 mA 47
Storage temperature range TSTG -60 150 °C 47
Maximum junction temperature TJ 125 °C 47
SD/MMC clock frequency in data transfer mode fPP 0 48 MHz 94
Clock low time tW(CKL) 32 ns 94
Clock high time tW(CKH) 30 ns 94
Clock rise time tr 4 ns 94
Clock fall time tf 5 ns 94
Clock setup time (CMD, D input) tISU 2 ns CMD、D输入（参照CK） 94
Clock hold time (CMD, D input) tIH 0 ns CMD、D输入（参照CK） 94
Output valid time (MMC and SD high-speed mode) tOV 6 ns MMC和SD高速模式CMD、D输出（参照CK） 94
Output hold time (MMC and SD high-speed mode) tOH 0 ns MMC和SD高速模式CMD、D输出（参照CK） 94
Output valid default time (SD default mode) tOVD 7 ns SD默认模式CMD、D输出（参照CK） 94
Output hold default time (SD default mode) tOHD 0.5 ns SD默认模式CMD、D输出（参照CK） 94
OTGFS transceiver startup time tSTARTUP 1 μs 95
OTGFS operating voltage VDD 3 3.6 V 95
Differential input sensitivity VDI 0.2 V I（OTGFS_D+/D-） 95
Differential common-mode range VCM 0.8 2.5 V 包含VDI范围 95
Single-ended receiver threshold VSE 1.3 2 V 95
Static output low level VOL 0.3 V 1.24 kΩ的RL接至3.6 V 95
Static output high level VOH 2.8 3.6 V 15 kΩ的RL接至VSS 95
OTGFS_D+ internal pull-up resistor RPU 0.97 1.24 1.58 kΩ VIN = VSS 95
OTGFS_D+/D- internal pull-down resistor RPD 15 19 25 kΩ VIN = VDD 95
Output rise time tr 4 20 ns CL ≤ 50 pF 95
Output fall time tf 4 20 ns CL ≤ 50 pF 95
Rise/fall time matching (tr/tf) trfm 90 110 % 95
Output signal crossover voltage VCRS 1.3 2 V 95
EMAC operating voltage VDD 3 3.6 V 96
MDC period (SMI) tMDC 509 510 511 ns 1.96 MHz, fAHB = 200 MHz 96
MDIO write data valid time td(MDIO) 13.5 14.5 15.5 ns 96
MDIO read data setup time tsu(MDIO) 35 ns 96
MDIO read data hold time th(MDIO) 0 ns 96
RMII receive data setup time tsu(RXD) 4 ns 96
RMII receive data hold time tih(RXD) 2 ns 96
RMII carrier setup time tsu(DV) 4 ns 96
RMII carrier hold time tih(DV) 2 ns 96
RMII transmit enable valid delay td(TXEN) 8 10 16 ns 96
RMII transmit data valid delay td(TXD) 7 10 16 ns 96

CAD (KiCad official)

  • Symbol: AT32F437VMT7
  • Footprint: Package_QFP:LQFP-100_14x14mm_P0.5mm
  • 3D model: LQFP-100(14x14) (KiCad packages3D, STEP)
  • 3D model files: at32f437vmt7-etched.step / at32f437vmt7-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); at32f437vmt7.step / at32f437vmt7.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: ARTERY datasheet (118 pp, sha256 1dc0c659f12e7670, retrieved 2026-10-18, tier: lcsc)
  • Datasheet language: Chinese. Pin names, descriptions, and specs on this page were extracted and translated to English by ds2sf; the linked PDF is the manufacturer original.
  • Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-haiku-5-5 (text), consensus claude-sonnet-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF