component

AT32F437RMT7

Public Made by Adom

by adom

ARTERY Microcontroller Units (MCUs/MPUs/SOCs), LQFP-64(10x10). Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.

componentsingle chip microcomputer-microcontrollerat32f437rmt7factory-2.0.0extractor-text

Verified AT32F437RMT7

by Ray · last 13 Nov 2026 · 1 record · files match
SymbolFootprint3D modelPins

Verification log 1 record

13 Nov 2026RayPublished by the parts factory: tier lcsc, 64 pinsfiles match
SymbolFootprint3D modelPinsfor all variants
  • ✓component-page-verify: PASS
  • •array (skip): not an array of element pairs
  • ✓cad_props: Datasheet, MPN and distributor properties match page.json
  • ✓component: AT32F437RMT7 · LQFP-64(10x10) · 64 pins
  • ✓copper: 64 copper pads, none touching another net
  • ✓datasheet: all 64 pin names found in the 118-page datasheet
  • •distributor (warn): no ['digikey', 'mouser'] number
  • ✓family: LQFP-64_10x10mm_P0.5mm
  • ✓files: 7 declared files present
  • ✓hero: docs/hero.png 4000x2500
  • ✓lbr: OK: /tmp/cpv-hdy1wvqd/x.lbr is a valid EAGLE .lbr with complete deviceset
  • ✓license: CC-BY-SA-4.0
  • ✓models_3d: 2 records
  • ✓package_fit: height and body within the datasheet's package drawing (datasheet p.110)
  • ✓pads: 64 pins = 64 pads
  • ✓pose: 2 STEP(s) Z-up, seated, centred
  • ✓symbol: 64 pins agree
  • ✓symbol_text: no pin names collide
  • ✓viewers: viewers/footprint.html 74 kB, viewers/symbol.html 41 kB
  • ✓visibility: public, source open
Evidencedatasheet
Verified files✓ at32f437rmt7.kicad_sym✓ at32f437rmt7.kicad_mod✓ at32f437rmt7.step
Spot something wrong? Report it as an issue Propose a fix Records are signed by members of adom.
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Generated by kicad-footprint-generator · KiCad file format 20260206
Name Last commit message Last updated
docs Publish 0.1.0 · Ray
viewers at32f437rmt7: viewers rendered from the public page · Ray
at32f437rmt7-etched.glb at32f437rmt7: factory component page (tier=lcsc) · Ray
at32f437rmt7-etched.step at32f437rmt7: factory component page (tier=lcsc) · Ray
at32f437rmt7-hero.glb at32f437rmt7: hero GLB from the etched model (keeps the MPN mark) · Ray
at32f437rmt7-hero.overlay.json at32f437rmt7: hero GLB from the etched model (keeps the MPN mark) · Ray
at32f437rmt7.glb Publish 0.1.0 · Ray
at32f437rmt7.kicad_mod Publish 0.1.0 · Ray
at32f437rmt7.kicad_sym Publish 0.1.0 · Ray
at32f437rmt7.lbr Publish 0.1.0 · Ray
at32f437rmt7.step Publish 0.1.0 · Ray
package.json Publish 0.1.0 · Ray
page.json Set visibility: public · Ray
README.md Publish 0.1.0 · Ray
verification.json Verified: Published by the parts factory: tier lcsc, 64 pins · Ray

AT32F437RMT7

ARTERY · Microcontroller Units (MCUs/MPUs/SOCs) · LQFP-64(10x10)

AT32F437RMT7 from ARTERY, in a LQFP-64(10x10). Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model). Symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 VBAT power_in Battery supply input for the VBAT domain (ERTC, LEXT and BPR), specified at 1.62 to 3.6 V.
2 PC13 bidirectional Backup-domain FT GPIO powered through a power switch limited to 3 mA, so it cannot source LED current; additional functions ERTC_AF1 and WKUP2.
3 PC14 bidirectional Backup-domain TC standard-level GPIO shared with LEXT_IN, powered through the same 3 mA power switch limit.
4 PC15 bidirectional Backup-domain TC standard-level GPIO shared with LEXT_OUT, powered through the same 3 mA power switch limit.
5 PH0 bidirectional Standard-level GPIO shared with HEXT_IN, the 4 to 25 MHz high-speed external oscillator input, and I2C1_SDA.
6 PH1 bidirectional Standard-level GPIO shared with HEXT_OUT, the high-speed external oscillator output, and I2C1_SCL.
7 NRST bidirectional Active-low device reset input and internal reset output with a built-in weak pull-up (30 to 50 kΩ); input pulses shorter than 33.3 µs are filtered.
8 PC0 bidirectional 5 V tolerant GPIO with analog function (FTa) and ADC123_IN10 fast-channel input; in analog mode the input must stay below VDD+0.3 V.
9 PC1 bidirectional 5 V tolerant GPIO with analog function (FTa) and ADC123_IN11 fast-channel input; in analog mode the input must stay below VDD+0.3 V.
10 PC2 bidirectional 5 V tolerant GPIO with analog function (FTa) and ADC123_IN12 fast-channel input; in analog mode the input must stay below VDD+0.3 V.
11 PC3 bidirectional 5 V tolerant GPIO with analog function (FTa) and ADC123_IN13 fast-channel input; in analog mode the input must stay below VDD+0.3 V.
12 VSSA/VREF- power_in Analog ground and negative reference voltage, which must be connected to VSS.
13 VDDA/VREF+ power_in Analog supply and positive reference voltage; VDDA must be the same as VDD (2.6 to 3.6 V).
14 PA0 bidirectional 5 V tolerant GPIO with analog function (FTa) and ADC123_IN0 fast-channel input, also WKUP1.
15 PA1 bidirectional 5 V tolerant GPIO with analog function (FTa) and ADC123_IN1 fast-channel input.
16 PA2 bidirectional 5 V tolerant GPIO with analog function (FTa) and ADC123_IN2 input; also USART2_TX and SDIO2_CK.
17 PA3 bidirectional 5 V tolerant GPIO with analog function (FTa) and ADC123_IN3 input; also I2S2_MCK and USART2_RX.
18 VSS power_in Digital ground.
19 VDD power_in Digital supply voltage, 2.6 to 3.6 V.
20 PA4 bidirectional 5 V tolerant GPIO with analog function (FTa) shared with ADC12_IN4 and DAC1_OUT.
21 PA5 bidirectional 5 V tolerant GPIO with analog function (FTa) shared with ADC12_IN5 and DAC2_OUT.
22 PA6 bidirectional 5 V tolerant GPIO with analog function (FTa) shared with ADC12_IN6; also TMR3_CH1, SPI1_MISO and QSPI1_IO0.
23 PA7 bidirectional 5 V tolerant GPIO with analog function (FTa) shared with ADC12_IN7; also TMR3_CH2, SPI1_MOSI and EMAC_MII_RX_DV.
24 PC4 bidirectional 5 V tolerant GPIO with analog function (FTa) shared with ADC12_IN14; also USART3_TX and XMC_SDCS0.
25 PC5 bidirectional 5 V tolerant GPIO with analog function (FTa) shared with ADC12_IN15; also USART3_RX and XMC_NOE.
26 PB0 bidirectional 5 V tolerant GPIO with analog function (FTa) shared with ADC12_IN8; also TMR3_CH3, USART2_RX and QSPI1_IO0.
27 PB1 bidirectional 5 V tolerant GPIO with analog function (FTa) shared with ADC12_IN9; also TMR3_CH4, SPI2_SCK and QSPI1_SCK.
28 PB2/BOOT1 bidirectional 5 V tolerant GPIO that also serves as the BOOT1 boot-mode configuration pin; also TMR2_CH4, TMR20_CH1 and SDIO1_CK.
29 PB10 bidirectional 5 V tolerant GPIO with 20 mA sink capability (FTf); also TMR2_CH3, I2C2_SCL, USART3_TX and XMC_NOE.
30 PB11 bidirectional 5 V tolerant GPIO (FT); also TMR2_CH4, I2C2_SDA, USART3_RX and EMAC_MII_TX_EN.
31 PH3 bidirectional 5 V tolerant GPIO (FT); also TMR5_CH2, I2C2_SDA, UART4_TX and QSPI1_IO1.
32 VDD power_in Digital supply voltage, 2.6 to 3.6 V.
33 PB12 bidirectional 5 V tolerant GPIO (FT); also TMR1_BRK, SPI2_CS, CAN2_RX, OTGFS2_ID and XMC_D13.
34 PB13 bidirectional 5 V tolerant GPIO (FT); also TMR1_CH1C, SPI2_SCK, CAN2_TX and OTGFS2_VBUS.
35 PB14 bidirectional Standard-level GPIO (TC, not 5 V tolerant); also TMR1_CH2C, SPI2_MISO, OTGFS2_D- and XMC_D0.
36 PB15 bidirectional Standard-level GPIO (TC, not 5 V tolerant); also ERTC_REFIN, TMR1_CH3C, SPI2_MOSI and OTGFS2_D+.
37 PC6 bidirectional 5 V tolerant GPIO (FT); also TMR3_CH1, TMR8_CH1, I2C1_SCL, USART6_TX and DVP_D0.
38 PC7 bidirectional 5 V tolerant GPIO (FT); also TMR3_CH2, TMR8_CH2, I2C1_SDA, USART6_RX and DVP_D1.
39 PC8 bidirectional 5 V tolerant GPIO (FT); also TMR3_CH3, TMR8_CH3, UART8_TX, USART6_CK and QSPI1_IO2.
40 PC9 bidirectional 5 V tolerant GPIO (FT); also CLKOUT2, TMR3_CH4, I2C3_SDA, UART8_RX and OTGFS2_OE.
41 PA8 bidirectional 5 V tolerant GPIO (FT); also CLKOUT1, TMR1_CH1, I2C3_SCL, USART1_CK and OTGFS1_SOF.
42 PA9 bidirectional 5 V tolerant GPIO (FT); also TMR1_CH2, USART1_TX, I2C1_SCL, OTGFS1_VBUS and DVP_D0.
43 PA10 bidirectional 5 V tolerant GPIO (FT); also TMR1_CH3, USART1_RX, I2C1_SDA, OTGFS1_ID and DVP_D1.
44 PA11 bidirectional Standard-level GPIO (TC, not 5 V tolerant); also TMR1_CH4, I2C2_SCL, USART1_CTS, CAN1_RX and OTGFS1_D-.
45 PA12 bidirectional Standard-level GPIO (TC, not 5 V tolerant); also TMR1_EXT, I2C2_SDA, USART1_RTS_DE, CAN1_TX and OTGFS1_D+.
46 PA13 bidirectional 5 V tolerant GPIO (FT) that is the JTMS/SWDIO serial-wire debug data pin after reset; also IR_OUT and OTGFS1_OE.
47 PH2 bidirectional 5 V tolerant GPIO (FT); also TMR5_CH1, I2C2_SCL, UART4_RX and QSPI1_IO0.
48 VDD power_in Digital supply voltage, 2.6 to 3.6 V.
49 PA14 bidirectional 5 V tolerant GPIO (FT) that is the JTCK/SWCLK serial-wire debug clock pin after reset; also SPI3_MOSI, I2S3_SD and USART2_TX.
50 PA15 bidirectional 5 V tolerant GPIO (FT) that is the JTDI debug input pin after reset; also TMR2_CH1, SPI1_CS, USART1_TX and USART2_RX.
51 PC10 bidirectional 5 V tolerant GPIO (FT); also TMR5_CH2, SPI3_SCK, I2S3_CK, USART3_TX, UART4_TX and SDIO1_D2.
52 PC11 bidirectional 5 V tolerant GPIO (FT); also TMR5_CH3, SPI3_MISO, USART3_RX, UART4_RX, SDIO1_D3 and XMC_D2.
53 PC12 bidirectional 5 V tolerant GPIO (FT); also TMR11_CH1, I2C2_SDA, SPI3_MOSI, USART3_CK, UART5_TX and XMC_D3.
54 PD2 bidirectional 5 V tolerant GPIO (FT); also TMR3_EXT, USART3_RTS_DE, UART5_RX, SDIO1_CMD, DVP_D11 and XMC_NWE.
55 PB3 bidirectional 5 V tolerant GPIO with 20 mA sink capability (FTf) that is the JTDO/SWO trace output pin after reset; also TMR2_CH2 and SPI1_SCK.
56 PB4 bidirectional 5 V tolerant GPIO (FT) that is the NJTRST JTAG reset pin after reset; also TMR3_CH1, SPI1_MISO and SDIO1_D0.
57 PB5 bidirectional 5 V tolerant GPIO (FT); also TMR3_CH2, I2C1_SMBA, SPI1_MOSI, USART1_CK, CAN2_RX and SDIO1_D3.
58 PB6 bidirectional 5 V tolerant GPIO (FT); also TMR4_CH1, I2C1_SCL, USART1_TX, CAN2_TX, QSPI1_CS and SDIO1_D0.
59 PB7 bidirectional 5 V tolerant GPIO (FT); also TMR4_CH2, TMR8_BRK, I2C1_SDA, USART1_RX and QSPI2_IO1.
60 BOOT0 input Dedicated BOOT0 boot-mode pin with a built-in weak pull-down that cannot be disabled.
61 PB8 bidirectional 5 V tolerant GPIO (FT); also TMR2_CH1, TMR4_CH3, TMR10_CH1, I2C1_SCL, CAN1_RX and SDIO1_D4.
62 PB9 bidirectional 5 V tolerant GPIO with 20 mA sink capability (FTf); also IR_OUT, TMR2_CH2, TMR4_CH4, I2C1_SDA, CAN1_TX and SDIO1_D5.
63 VSS power_in Digital ground.
64 VDD power_in Digital supply voltage, 2.6 to 3.6 V.

Key specifications

Parameter Value
Manufacturer ARTERY
Package LQFP-64(10x10)
Category Single Chip Microcomputer/Microcontroller
Pins 64

Electrical characteristics

Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).

Parameter Symbol Min Typ Max Unit Conditions Page
External main supply voltage VDDx-VSS VDDx-VSS -0.3 4 V 47
Input voltage on FTa pin, input floating / pull-up / pull-down mode VIN -0.3 6 V FTa引脚，输入浮空、输入上拉或输入下拉模式 47
Voltage difference between supply pins /ΔVDDx/ 50 mV 47
Voltage difference between ground pins /VSSx-VSS/ 50 mV 47
Total current into supply pins (VDDA and VDD) IVDD 250 mA 47
Total current out of VSS ground line IVSS 250 mA 47
Output sink current on any GPIO and control pin IIO 25 mA 47
Output source current on any GPIO and control pin IIO -25 mA 47
Storage temperature range TSTG -60 150 °C 47
Maximum junction temperature TJ 125 °C 47
Supply voltage range (power supply feature) 2.6 3.6 V 1
Operating temperature range -40 105 °C 1
48 MHz HICK frequency accuracy -1 1 % 25 °C 1
48 MHz HICK frequency accuracy -2.5 2.5 % -40 °C至+105 °C 1
Data transfer mode clock frequency fPP 0 48 MHz 94
Clock low time tW(CKL) 32 ns 94
Clock high time tW(CKH) 30 ns 94
Clock rise time tr 4 ns 94
Clock fall time tf 5 ns 94
Clock setup time for CMD/D input (ref CK) tISU 2 ns 94
Clock hold time for CMD/D input (ref CK) tIH 0 ns 94
Output valid time CMD/D output, MMC and SD high-speed mode tOV 6 ns 94
Output hold time CMD/D output, MMC and SD high-speed mode tOH 0 ns 94
Output valid time CMD/D output, SD default mode tOVD 7 ns 94
Output hold time CMD/D output, SD default mode tOHD 0.5 ns 94
OTGFS transceiver startup time tSTARTUP 1 μs 95
OTGFS operating voltage VDD 3 3.6 V 95
Differential input sensitivity VDI 0.2 V 95
Differential common-mode range VCM 0.8 2.5 V 包含VDI范围 95
Single-ended receiver threshold VSE 1.3 2 V 95
Static output low level VOL 0.3 V 1.24 kΩ的RL接至3.6 V 95
Static output high level VOH 2.8 3.6 V 15 kΩ的RL接至VSS 95
OTGFS_D+ internal pull-up resistor RPU 0.97 1.24 1.58 kΩ VIN = VSS 95
OTGFS_D+/D- internal pull-down resistor RPD 15 19 25 kΩ VIN = VDD 95
Rise time (10% to 90%) tr 4 20 ns CL ≤ 50 pF 95
Fall time (10% to 90%) tf 4 20 ns CL ≤ 50 pF 95
Rise/fall time matching tr/tf trfm 90 110 % 95
Output signal crossover voltage VCRS 1.3 2 V 95
EMAC Ethernet operating voltage VDD 3 3.6 V 96
MDC period (SMI) tMDC 509 510 511 ns 1.96 MHz，fAHB = 200 MHz 96
MDIO write data valid time td(MDIO) 13.5 14.5 15.5 ns 96
MDIO read data setup time tsu(MDIO) 35 ns 96
MDIO read data hold time th(MDIO) 0 ns 96
RMII receive data setup time tsu(RXD) 4 ns 96
RMII receive data hold time tih(RXD) 2 ns 96
RMII carrier (DV) setup time tsu(DV) 4 ns 96
RMII carrier (DV) hold time tih(DV) 2 ns 96
RMII transmit enable valid delay td(TXEN) 8 10 16 ns 96
RMII transmit data valid delay td(TXD) 7 10 16 ns 96

CAD (KiCad official)

  • Symbol: AT32F437RMT7
  • Footprint: Package_QFP:LQFP-64_10x10mm_P0.5mm
  • 3D model: LQFP-64(10x10) (KiCad packages3D, STEP)
  • 3D model files: at32f437rmt7-etched.step / at32f437rmt7-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); at32f437rmt7.step / at32f437rmt7.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: ARTERY datasheet (118 pp, sha256 1dc0c659f12e7670, retrieved 2026-11-13, tier: lcsc)
  • Datasheet language: Chinese. Pin names, descriptions, and specs on this page were extracted and translated to English by ds2sf; the linked PDF is the manufacturer original.
  • Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-haiku-5-5 (text), consensus claude-sonnet-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF