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AT32F437RGT7

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ARTERY Microcontroller Units (MCUs/MPUs/SOCs), LQFP-64(10x10). Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.

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AT32F437RGT7

ARTERY · Microcontroller Units (MCUs/MPUs/SOCs) · LQFP-64(10x10)

AT32F437RGT7 from ARTERY, in a LQFP-64(10x10). Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 VBAT power_in Battery supply (1.62-3.6 V) for the VBAT domain (ERTC, LEXT, BPR) when VDD is absent.
2 PC13 bidirectional FT I/O powered through a switch limited to 3 mA, so not usable as a current source when output; additional functions ERTC_AF1 / WKUP2.
3 PC14 bidirectional TC I/O (PC14) with LEXT_IN 32 kHz oscillator input; 3 mA output-drive limit.
4 PC15 bidirectional TC I/O (PC15) with LEXT_OUT 32 kHz oscillator output; 3 mA output-drive limit.
5 PH0 bidirectional TC I/O (PH0) with HEXT_IN 4-25 MHz oscillator input; alternate function I2C1_SDA.
6 PH1 bidirectional TC I/O (PH1) with HEXT_OUT oscillator output; alternate function I2C1_SCL.
7 NRST bidirectional Active-low device reset input / internal reset output with built-in weak pull-up.
8 PC0 bidirectional FTa I/O; I2C3_SCL, UART7_TX, SDIO2_D0, XMC_SDNWE; analog ADC123_IN10.
9 PC1 bidirectional FTa I/O; I2C3_SDA, SPI3_MOSI/I2S3_SD, SPI2_MOSI/I2S2_SD, UART7_RX, SDIO2_D1, EMAC_MDC; analog ADC123_IN11.
10 PC2 bidirectional FTa I/O; TMR20_CH2, SPI2_MISO, UART8_TX, SDIO2_D2, EMAC_MII_TXD2, XMC_SDCS0, XMC_NWE; analog ADC123_IN12.
11 PC3 bidirectional FTa I/O; SPI2_MOSI/I2S2_SD, UART8_RX, QSPI2_IO1, SDIO2_D3, EMAC_MII_TX_CLK, XMC_SDCKE0, XMC_A0; analog ADC123_IN13.
12 VSSA/VREF- power_in Analog ground / negative reference voltage.
13 VDDA/VREF+ power_in Analog supply (2.6-3.6 V, must equal VDD) / positive reference voltage.
14 PA0 bidirectional FTa I/O; TMR2_CH1/EXT, TMR5_CH1, TMR8_EXT, I2C2_SCL, USART2_CTS, UART4_TX, EMAC_MII_CRS; analog ADC123_IN0, ERTC_AF2, WKUP1.
15 PA1 bidirectional FTa I/O; TMR2_CH2, TMR5_CH2, I2C2_SDA, SPI4_MOSI, USART2_RTS_DE, UART4_RX, QSPI1_IO3, EMAC clock functions; analog ADC123_IN1.
16 PA2 bidirectional FTa I/O; TMR2_CH3, TMR5_CH3, TMR9_CH1, USART2_TX, SDIO2_CK, EMAC_MDIO, XMC_D4; analog ADC123_IN2.
17 PA3 bidirectional FTa I/O; TMR2_CH4, TMR5_CH4, TMR9_CH2, I2S2_MCK, USART2_RX, QSPI2_IO3, SDIO2_CMD, EMAC_MII_COL, XMC_D5; analog ADC123_IN3.
18 VSS power_in Digital ground.
19 VDD power_in Digital supply (2.6-3.6 V).
20 PA4 bidirectional FTa I/O; SPI1_CS/I2S1_WS, SPI3_CS/I2S3_WS, USART2_CK, USART6_TX, SDIO2, OTGFS2_SOF, DVP_HSYNC, XMC_D6; analog ADC12_IN4 / DAC1_OUT.
21 PA5 bidirectional FTa I/O; TMR2_CH1/EXT, TMR8_CH1C, SPI1_SCK/I2S1_CK, USART6_RX, QSPI2_IO2, SDIO2, XMC_D7; analog ADC12_IN5 / DAC2_OUT.
22 PA6 bidirectional FTa I/O; TMR1_BRK, TMR3_CH1, TMR8_BRK, SPI1_MISO, USART3_CTS, TMR13_CH1, QSPI1_IO0, SDIO, DVP_PCLK; analog ADC12_IN6.
23 PA7 bidirectional FTa I/O; TMR1_CH1C, TMR3_CH2, TMR8_CH1C, SPI1_MOSI/I2S1_SD, TMR14_CH1, QSPI1_IO1, EMAC RX_DV, XMC_SDNWE, SDIO2; analog ADC12_IN7.
24 PC4 bidirectional FTa I/O; TMR9_CH1, I2S1_MCK, USART3_TX, QSPI1_IO2, EMAC_RXD0, XMC_SDCS0, SDIO2_CK, XMC_NE4; analog ADC12_IN14.
25 PC5 bidirectional FTa I/O; TMR9_CH2, I2C1_SMBA, USART3_RX, QSPI1_IO3, EMAC_RXD1, XMC_SDCKE0, SDIO2_CMD, XMC_NOE; analog ADC12_IN15.
26 PB0 bidirectional FTa I/O; TMR1_CH2C, TMR3_CH3, TMR8_CH2C, I2S1_MCK, USART2_RX, SPI3_MOSI, USART3_CK, QSPI, EMAC_MII_RXD2, SDIO1_D1; analog ADC12_IN8.
27 PB1 bidirectional FTa I/O; TMR1_CH3C, TMR3_CH4, TMR8_CH3C, SPI2_SCK/I2S2_CK, USART3_RTS_DE, QSPI1/2_SCK, EMAC_MII_RXD3, SDIO1_D2; analog ADC12_IN9.
28 PB2/BOOT1 bidirectional FT I/O (PB2 after reset) also BOOT1; TMR2_CH4, TMR20_CH1, I2C3_SMBA, SPI3_MOSI/I2S3_SD, QSPI1_SCK, SDIO1_CK.
29 PB10 bidirectional FTf I/O (20 mA sink); TMR2_CH3, I2C2_SCL, SPI2_SCK/I2S2_CK, I2S3_MCK, USART3_TX, QSPI1, EMAC_MII_RX_ER, SDIO1_D7, XMC_NOE.
30 PB11 bidirectional FT I/O; TMR2_CH4, TMR5_CH4, I2C2_SDA, USART3_RX, QSPI1_IO0, EMAC_MII_TX_EN / EMAC_RMII_TX_EN.
31 PH3 bidirectional FT I/O; TMR5_CH2, I2C2_SDA, UART4_TX, QSPI1_IO1.
32 VDD power_in Digital supply (2.6-3.6 V).
33 PB12 bidirectional FT I/O; TMR1_BRK, TMR5_CH1, I2C2_SMBA, SPI2_CS/I2S2_WS, SPI4_CS, SPI3_SCK, USART3_CK, CAN2_RX, EMAC_TXD0, OTGFS2_ID, XMC_D13.
34 PB13 bidirectional FT I/O; TMR1_CH1C, I2C3_SMBA/SCL, SPI2_SCK, SPI4_SCK, USART3_CTS, CAN2_TX, EMAC_TXD1, OTGFS2_VBUS.
35 PB14 bidirectional TC I/O; TMR1_CH2C, TMR8_CH2C, I2C3_SDA, SPI2_MISO, USART3_RTS_DE, TMR12_CH1, OTGFS2_D-, SDIO1_D6, XMC_D0.
36 PB15 bidirectional TC I/O; ERTC_REFIN, TMR1_CH3C, TMR8_CH3C, I2C3_SCL, SPI2_MOSI/I2S2_SD, TMR12_CH2, OTGFS2_D+, SDIO1_CK.
37 PC6 bidirectional FT I/O; TMR3_CH1, TMR8_CH1, I2C1_SCL, I2S2_MCK, USART6_TX, XMC_A0, SDIO1_D6, DVP_D0, XMC_D1.
38 PC7 bidirectional FT I/O; TMR3_CH2, TMR8_CH2, I2C1_SDA, SPI2_SCK, I2S3_MCK, USART6_RX, XMC_A1, SDIO1_D7, DVP_D1.
39 PC8 bidirectional FT I/O; TMR3_CH3, TMR8_CH3, I2S4_MCK, TMR20_CH3, UART8_TX, USART6_CK, QSPI1_IO2, XMC_A2, SDIO1_D0, DVP_D2.
40 PC9 bidirectional FT I/O; CLKOUT2, TMR3_CH4, TMR8_CH4, I2C3_SDA, UART8_RX, QSPI1_IO0, XMC_A3, OTGFS2_OE, SDIO1_D1, DVP_D3.
41 PA8 bidirectional FT I/O; CLKOUT1, TMR1_CH1, I2C3_SCL, USART1_CK, USART2_TX, OTGFS1_SOF, SDIO1_D1, XMC_A4.
42 PA9 bidirectional FT I/O; TMR1_CH2, I2C3_SMBA, SPI2_SCK, USART1_TX, I2C1_SCL, OTGFS1_VBUS, SDIO1_D2, DVP_D0; bootloader USART1_TX.
43 PA10 bidirectional FT I/O; TMR1_CH3, SPI2_MOSI, I2S4_MCK, USART1_RX, I2C1_SDA, OTGFS1_ID, DVP_D1; bootloader USART1_RX.
44 PA11 bidirectional TC I/O; TMR1_CH4, I2C2_SCL, SPI2_CS, SPI4_MISO, USART1_CTS, USART6_TX, CAN1_RX, OTGFS1_D-, DVP_D2.
45 PA12 bidirectional TC I/O; TMR1_EXT, I2C2_SDA, SPI2_MISO, USART1_RTS_DE, USART6_RX, CAN1_TX, OTGFS1_D+, DVP_D3.
46 PA13 bidirectional FT I/O, JTMS/SWDIO after reset; also IR_OUT, SPI3_MISO, OTGFS1_OE.
47 PH2 bidirectional FT I/O; TMR5_CH1, I2C2_SCL, UART4_RX, QSPI1_IO0.
48 VDD power_in Digital supply (2.6-3.6 V).
49 PA14 bidirectional FT I/O, JTCK/SWCLK after reset; also SPI3_MOSI/I2S3_SD, USART2_TX.
50 PA15 bidirectional FT I/O, JTDI after reset; TMR2_CH1, SPI1_CS, SPI3_CS, USART1_TX, USART2_RX, QSPI, XMC_NE2/NCE3.
51 PC10 bidirectional FT I/O; TMR5_CH2, SPI3_SCK, USART3_TX, UART4_TX, QSPI1_IO1, SDIO1_D2, DVP_D8.
52 PC11 bidirectional FT I/O; TMR5_CH3, I2S3_SDEXT, SPI3_MISO, USART3_RX, UART4_RX, QSPI1_CS, SDIO1_D3, DVP_D4, XMC_D2.
53 PC12 bidirectional FT I/O; TMR11_CH1, I2C2_SDA, SPI3_MOSI, USART3_CK, UART5_TX, SDIO1_CK, DVP_D9, XMC_D3.
54 PD2 bidirectional FT I/O; TMR3_EXT, USART3_RTS_DE, UART5_RX, XMC_A7, SDIO1_CMD, DVP_D11, XMC_NWE.
55 PB3 bidirectional FTf I/O, JTDO after reset; TMR2_CH2, I2C2_SDA, SPI1_SCK, SPI3_SCK, USART1_RX, UART7_RX, QSPI1_IO3, DVP_D4, SWO.
56 PB4 bidirectional FT I/O, NJTRST after reset; TMR3_CH1, I2C3_SDA, SPI1_MISO, SPI3_MISO, UART7_TX, SDIO1_D0, DVP_D5.
57 PB5 bidirectional FT I/O; TMR3_CH2, I2C1_SMBA, SPI1_MOSI, SPI3_MOSI, USART1_CK, UART5_RX, CAN2_RX, EMAC_PPS_OUT, XMC_SDCKE1, DVP_D10, SDIO1_D3.
58 PB6 bidirectional FT I/O; TMR4_CH1, I2C1_SCL, I2S1_MCK, SPI4_CS, USART1_TX, UART5_TX, CAN2_TX, QSPI1_CS, XMC_SDCS1, DVP_D5, SDIO1_D0.
59 PB7 bidirectional FT I/O; TMR4_CH2, TMR8_BRK, I2C1_SDA, SPI4_SCK, USART1_RX, QSPI2_IO1, XMC_NADV, DVP_VSYNC, SDIO1_D0.
60 BOOT0 input Dedicated boot mode selection input with built-in non-disableable weak pull-down.
61 PB8 bidirectional FT I/O; TMR2_CH1, TMR4_CH3, TMR10_CH1, I2C1_SCL, SPI4_MISO, UART5_RX, CAN1_RX, QSPI2_CS, EMAC_MII_TXD3, SDIO1_D4, DVP_D6.
62 PB9 bidirectional FTf I/O (20 mA sink); IR_OUT, TMR2_CH2, TMR4_CH4, TMR11_CH1, I2C1_SDA, SPI2_CS, SPI4_MOSI, UART5_TX, CAN1_TX, QSPI1_CS, SDIO1_D5, DVP_D7.
63 VSS power_in Digital ground.
64 VDD power_in Digital supply (2.6-3.6 V).

Key specifications

Parameter Value
Manufacturer ARTERY
Package LQFP-64(10x10)
Category Single Chip Microcomputer/Microcontroller
Pins 64

Electrical characteristics

Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).

Parameter Symbol Min Typ Max Unit Conditions Page
External main supply voltage VDDx-VSS -0.3 4 V 47
Input voltage on FT, FTf pins; on FTa pins in input floating/pull-up/pull-down mode VIN 6 V minimum printed as VSS-0.3 47
Input voltage on TC pins; on FTa pins in analog mode VIN 4 V minimum printed as VSS-0.3 47
Voltage difference between different supply pins /ΔVDDx/ 50 mV 47
Voltage difference between different ground pins /VSSx-VSS/ 50 mV 47
Total current into VDD/VDDA power lines (source) IVDD 250 mA 47
Total current out of VSS ground lines (sink) IVSS 250 mA 47
Output sink current on any GPIO and control pin IIO 25 mA 47
Output current on any GPIO and control pin IIO -25 mA 47
Storage temperature range TSTG -60 150 °C 47
Maximum junction temperature TJ 125 °C 47
SDIO clock frequency in data transfer mode fPP 0 48 MHz 94
SDIO clock low time tW(CKL) 32 ns 94
SDIO clock high time tW(CKH) 30 ns 94
SDIO clock rise time tr 4 ns 94
SDIO clock fall time tf 5 ns 94
SDIO input setup time tISU 2 ns CMD, D inputs (referenced to CK) 94
SDIO input hold time tIH 0 ns CMD, D inputs (referenced to CK) 94
SDIO output valid time tOV 6 ns MMC and SD high-speed mode, CMD, D outputs (referenced to CK) 94
SDIO output hold time tOH 0 ns MMC and SD high-speed mode, CMD, D outputs (referenced to CK) 94
SDIO output valid default time tOVD 7 ns SD default mode, CMD, D outputs (referenced to CK) 94
SDIO output hold default time tOHD 0.5 ns SD default mode, CMD, D outputs (referenced to CK) 94
OTGFS operating voltage VDD 3 3.6 V min 3.0; USB function guaranteed from 2.7 V per footnote 95
OTGFS differential input sensitivity VDI 0.2 V I(OTGFS_D+/D-) 95
OTGFS differential common mode range VCM 0.8 2.5 V Includes VDI range 95
OTGFS single-ended receiver threshold VSE 1.3 2 V 95
OTGFS static output low level VOL 0.3 V RL of 1.24 kΩ to 3.6 V 95
OTGFS static output high level VOH 2.8 3.6 V RL of 15 kΩ to VSS 95
OTGFS_D+ internal pull-up resistance RPU 0.97 1.24 1.58 kΩ VIN = VSS 95
OTGFS_D+/D- internal pull-down resistance RPD 15 19 25 kΩ VIN = VDD 95
OTGFS rise time tr 4 20 ns CL ≤ 50 pF 95
OTGFS fall time tf 4 20 ns CL ≤ 50 pF 95
OTGFS rise/fall time matching trfm 90 110 % tr/tf 95
OTGFS output signal crossover voltage VCRS 1.3 2 V 95

CAD (KiCad official)

  • Symbol: AT32F437RGT7
  • Footprint: Package_QFP:LQFP-64_10x10mm_P0.5mm
  • 3D model: LQFP-64(10x10) (KiCad packages3D, STEP)
  • 3D model files: at32f437rgt7-etched.step / at32f437rgt7-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); at32f437rgt7.step / at32f437rgt7.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: ARTERY datasheet (118 pp, sha256 1dc0c659f12e7670, retrieved 2026-10-22, tier: lcsc)
  • Datasheet language: Chinese. Pin names, descriptions, and specs on this page were extracted and translated to English by ds2sf; the linked PDF is the manufacturer original.
  • Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-sonnet-5-5 (text), consensus claude-sonnet-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF