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AT32F435RMT7

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ARTERY Microcontroller Units (MCUs/MPUs/SOCs), LQFP-64(10x10). Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.

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3D Model

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Symbol & Footprint

Schematic Symbol

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PCB Footprint

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Datasheet

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Contents

README

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AT32F435RMT7

ARTERY · Microcontroller Units (MCUs/MPUs/SOCs) · LQFP-64(10x10)

AT32F435RMT7 from ARTERY, in a LQFP-64(10x10). Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 VBAT power_in Battery supply (1.62-3.6 V) for the ERTC, LEXT and battery-powered registers when VDD is absent.
2 PC13 bidirectional FT GPIO powered via the backup power switch (max 3 mA, cannot source current as output); ERTC_AF1 / WKUP2.
3 PC14 bidirectional TC GPIO powered via the backup switch (max 3 mA); LEXT_IN 32 kHz crystal input.
4 PC15 bidirectional TC GPIO powered via the backup switch (max 3 mA); LEXT_OUT 32 kHz crystal output.
5 PH0 bidirectional TC GPIO with I2C1_SDA; additional function HEXT_IN (4-25 MHz crystal input).
6 PH1 bidirectional TC GPIO with I2C1_SCL; additional function HEXT_OUT (4-25 MHz crystal output).
7 NRST bidirectional Active-low device reset input / internal reset output with built-in weak pull-up.
8 PC0 bidirectional FTa GPIO with I2C3_SCL, UART7_TX, SDIO2_D0, XMC_SDNWE; ADC123_IN10.
9 PC1 bidirectional FTa GPIO with I2C3_SDA, SPI3/SPI2 MOSI, UART7_RX, SDIO2_D1, EMAC_MDC; ADC123_IN11.
10 PC2 bidirectional FTa GPIO with TMR20_CH2, SPI2_MISO, UART8_TX, SDIO2_D2, XMC_SDCS0/NWE; ADC123_IN12.
11 PC3 bidirectional FTa GPIO with SPI2_MOSI, UART8_RX, QSPI2_IO1, SDIO2_D3, XMC_SDCKE0/A0; ADC123_IN13.
12 VSSA/VREF- power_in Analog ground / negative reference voltage.
13 VDDA/VREF+ power_in Analog supply (2.6-3.6 V, must equal VDD) / positive reference voltage.
14 PA0 bidirectional FTa GPIO with TMR2_CH1, TMR5_CH1, USART2_CTS, UART4_TX; ADC123_IN0, ERTC_AF2, WKUP1.
15 PA1 bidirectional FTa GPIO with TMR2_CH2, TMR5_CH2, SPI4_MOSI, USART2_RTS_DE, UART4_RX; ADC123_IN1.
16 PA2 bidirectional FTa GPIO with TMR2_CH3, TMR5_CH3, USART2_TX, SDIO2_CK, EMAC_MDIO; ADC123_IN2.
17 PA3 bidirectional FTa GPIO with TMR2_CH4, TMR5_CH4, USART2_RX, QSPI2_IO3, SDIO2_CMD; ADC123_IN3.
18 VSS power_in Digital ground.
19 VDD power_in Digital supply (2.6-3.6 V).
20 PA4 bidirectional FTa GPIO with SPI1_CS/I2S1_WS, SPI3_CS, USART2_CK, DVP_HSYNC; ADC12_IN4, DAC1_OUT.
21 PA5 bidirectional FTa GPIO with TMR2_CH1, SPI1_SCK/I2S1_CK, USART6_RX, QSPI2_IO2; ADC12_IN5, DAC2_OUT.
22 PA6 bidirectional FTa GPIO with TMR1_BRK, TMR3_CH1, SPI1_MISO, USART3_CTS, QSPI1_IO0, DVP_PCLK; ADC12_IN6.
23 PA7 bidirectional FTa GPIO with TMR1_CH1C, TMR3_CH2, SPI1_MOSI, EMAC_MII_RX_DV, XMC_SDNWE; ADC12_IN7.
24 PC4 bidirectional FTa GPIO with I2S1_MCK, USART3_TX, QSPI1_IO2, EMAC_MII_RXD0, XMC_SDCS0/NE4; ADC12_IN14.
25 PC5 bidirectional FTa GPIO with I2C1_SMBA, USART3_RX, QSPI1_IO3, EMAC_MII_RXD1, XMC_NOE; ADC12_IN15.
26 PB0 bidirectional FTa GPIO with TMR1_CH2C, TMR3_CH3, USART2_RX, SPI3_MOSI, QSPI2_IO0, SDIO1_D1; ADC12_IN8.
27 PB1 bidirectional FTa GPIO with TMR1_CH3C, TMR3_CH4, SPI2_SCK, USART3_RTS_DE, QSPI1_SCK, SDIO1_D2; ADC12_IN9.
28 PB2 / BOOT1 bidirectional FT GPIO, BOOT1 boot-mode select after reset; TMR2_CH4, I2C3_SMBA, SPI3_MOSI, QSPI1_SCK, SDIO1_CK.
29 PB10 bidirectional FTf GPIO (20 mA sink) with TMR2_CH3, I2C2_SCL, SPI2_SCK, USART3_TX, QSPI1_CS, SDIO1_D7.
30 PB11 bidirectional FT GPIO with TMR2_CH4, I2C2_SDA, USART3_RX, QSPI1_IO0, EMAC_MII_TX_EN.
31 PH3 bidirectional FT GPIO with TMR5_CH2, I2C2_SDA, UART4_TX, QSPI1_IO1.
32 VDD power_in Digital supply (2.6-3.6 V).
33 PB12 bidirectional FT GPIO with TMR1_BRK, SPI2_CS, SPI3_SCK, USART3_CK, CAN2_RX, OTGFS2_ID, XMC_D13.
34 PB13 bidirectional FT GPIO with TMR1_CH1C, SPI2_SCK, I2C3_SCL, USART3_CTS, CAN2_TX, OTGFS2_VBUS.
35 PB14 bidirectional TC GPIO with TMR1_CH2C, SPI2_MISO, USART3_RTS_DE, OTGFS2_D-, SDIO1_D6.
36 PB15 bidirectional TC GPIO with ERTC_REFIN, TMR1_CH3C, SPI2_MOSI, OTGFS2_D+, SDIO1_CK.
37 PC6 bidirectional FT GPIO with TMR3_CH1, TMR8_CH1, I2C1_SCL, USART6_TX, SDIO1_D6, DVP_D0, XMC_D1.
38 PC7 bidirectional FT GPIO with TMR3_CH2, TMR8_CH2, I2C1_SDA, USART6_RX, SDIO1_D7, DVP_D1.
39 PC8 bidirectional FT GPIO with TMR3_CH3, TMR8_CH3, UART8_TX, USART6_CK, QSPI1_IO2, SDIO1_D0, DVP_D2.
40 PC9 bidirectional FT GPIO with CLKOUT2, TMR3_CH4, TMR8_CH4, UART8_RX, QSPI1_IO0, OTGFS2_OE, SDIO1_D1.
41 PA8 bidirectional FT GPIO with CLKOUT1, TMR1_CH1, I2C3_SCL, USART1_CK, OTGFS1_SOF, SDIO1_D1.
42 PA9 bidirectional FT GPIO with TMR1_CH2, USART1_TX, I2C1_SCL, OTGFS1_VBUS, SDIO1_D2, DVP_D0; bootloader USART1_TX.
43 PA10 bidirectional FT GPIO with TMR1_CH3, USART1_RX, I2C1_SDA, OTGFS1_ID, DVP_D1; bootloader USART1_RX.
44 PA11 bidirectional TC GPIO with TMR1_CH4, USART1_CTS, CAN1_RX, OTGFS1_D- (USB data minus).
45 PA12 bidirectional TC GPIO with TMR1_EXT, USART1_RTS_DE, CAN1_TX, OTGFS1_D+ (USB data plus).
46 PA13 bidirectional FT GPIO, reset function JTMS/SWDIO debug data; also IR_OUT, SPI3_MISO, OTGFS1_OE.
47 PH2 bidirectional FT GPIO with TMR5_CH1, I2C2_SCL, UART4_RX, QSPI1_IO0.
48 VDD power_in Digital supply (2.6-3.6 V).
49 PA14 bidirectional FT GPIO, reset function JTCK/SWCLK debug clock; also SPI3_MOSI, USART2_TX.
50 PA15 bidirectional FT GPIO, reset function JTDI; also TMR2_CH1, SPI1_CS, SPI3_CS, USART1_TX, USART2_RX, XMC_NE2.
51 PC10 bidirectional FT GPIO with TMR5_CH2, SPI3_SCK, USART3_TX, UART4_TX, SDIO1_D2, DVP_D8.
52 PC11 bidirectional FT GPIO with TMR5_CH3, SPI3_MISO, USART3_RX, UART4_RX, SDIO1_D3, DVP_D4, XMC_D2.
53 PC12 bidirectional FT GPIO with TMR11_CH1, SPI3_MOSI, USART3_CK, UART5_TX, SDIO1_CK, DVP_D9, XMC_D3.
54 PD2 bidirectional FT GPIO with TMR3_EXT, USART3_RTS_DE, UART5_RX, SDIO1_CMD, DVP_D11, XMC_NWE.
55 PB3 bidirectional FTf GPIO, reset function JTDO; also TMR2_CH2, SPI1_SCK, SPI3_SCK, USART1_RX, UART7_RX, SWO.
56 PB4 bidirectional FT GPIO, reset function NJTRST; also TMR3_CH1, SPI1_MISO, SPI3_MISO, UART7_TX, SDIO1_D0.
57 PB5 bidirectional FT GPIO with TMR3_CH2, SPI1_MOSI, SPI3_MOSI, USART1_CK, UART5_RX, CAN2_RX, SDIO1_D3.
58 PB6 bidirectional FT GPIO with TMR4_CH1, I2C1_SCL, USART1_TX, UART5_TX, CAN2_TX, QSPI1_CS, SDIO1_D0.
59 PB7 bidirectional FT GPIO with TMR4_CH2, TMR8_BRK, I2C1_SDA, USART1_RX, QSPI2_IO1, DVP_VSYNC.
60 BOOT0 input Dedicated boot-mode select input with built-in non-disableable weak pull-down.
61 PB8 bidirectional FT GPIO with TMR2_CH1, TMR4_CH3, I2C1_SCL, UART5_RX, CAN1_RX, QSPI2_CS, SDIO1_D4, DVP_D6.
62 PB9 bidirectional FTf GPIO (20 mA sink) with IR_OUT, TMR4_CH4, I2C1_SDA, UART5_TX, CAN1_TX, SDIO1_D5, DVP_D7.
63 VSS power_in Digital ground.
64 VDD power_in Digital supply (2.6-3.6 V).

Key specifications

Parameter Value
Manufacturer ARTERY
Package LQFP-64(10x10)
Category Single Chip Microcomputer/Microcontroller
Pins 64

Electrical characteristics

Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).

Parameter Symbol Min Typ Max Unit Conditions Page
External main supply voltage VDDx-VSS -0.3 4 V 47
Input voltage on FT, FTf pins and on FTa pins (input floating, pull-up or pull-down) VIN -0.3 6 V Printed as VSS-0.3 to 6.0 47
Input voltage on TC pins and on FTa pins in analog mode VIN -0.3 4 V Printed as VSS-0.3 to 4.0 47
Voltage difference between different supply pins /ΔVDDx/ 50 mV 47
Voltage difference between different ground pins /VSSx-VSS/ 50 mV 47
Total current into VDD/VDDA power lines (source) IVDD 250 mA 47
Total current out of VSS ground lines (sink) IVSS 250 mA 47
Output sink current on any GPIO and control pin IIO 25 mA 47
Output current on any GPIO and control pin IIO -25 mA 47
Storage temperature range TSTG -60 150 °C Printed as -60 ~ +150 47
Maximum junction temperature TJ 125 °C 47
SD/MMC clock frequency in data transfer mode fPP 0 48 MHz 94
Clock low time tW(CKL) 32 ns 94
Clock high time tW(CKH) 30 ns 94
Clock rise time tr 4 ns 94
Clock fall time tf 5 ns 94
Input setup time (CMD, D inputs relative to CK) tISU 2 ns 94
Input hold time (CMD, D inputs relative to CK) tIH 0 ns 94
Output valid time in MMC and SD high speed mode tOV 6 ns 94
Output hold time in MMC and SD high speed mode tOH 0 ns 94
Output valid default time in SD default mode tOVD 7 ns 94
Output hold default time in SD default mode tOHD 0.5 ns 94
OTGFS transceiver startup time tSTARTUP 1 μs 95
OTGFS operating voltage VDD 3 3.6 V 95
Differential input sensitivity VDI 0.2 V I(OTGFS_D+/D-) 95
Differential common mode range VCM 0.8 2.5 V Includes VDI range 95
Single-ended receiver threshold VSE 1.3 2 V 95
Static output low level VOL 0.3 V RL of 1.24 kΩ to 3.6 V 95
Static output high level VOH 2.8 3.6 V RL of 15 kΩ to VSS 95
OTGFS_D+ internal pull-up resistance RPU 0.97 1.24 1.58 kΩ VIN = VSS 95
OTGFS_D+/D- internal pull-down resistance RPD 15 19 25 kΩ VIN = VDD 95
OTGFS rise time tr 4 20 ns CL ≤ 50 pF 95
OTGFS fall time tf 4 20 ns CL ≤ 50 pF 95
Rise/fall time matching trfm 90 110 % tr/tf 95
Output signal crossover voltage VCRS 1.3 2 V 95

CAD (KiCad official)

  • Symbol: AT32F435RMT7
  • Footprint: Package_QFP:LQFP-64_10x10mm_P0.5mm
  • 3D model: LQFP-64(10x10) (KiCad packages3D, STEP)
  • 3D model files: at32f435rmt7-etched.step / at32f435rmt7-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); at32f435rmt7.step / at32f435rmt7.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: ARTERY datasheet (118 pp, sha256 1dc0c659f12e7670, retrieved 2026-10-23, tier: lcsc)
  • Datasheet language: Chinese. Pin names, descriptions, and specs on this page were extracted and translated to English by ds2sf; the linked PDF is the manufacturer original.
  • Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-sonnet-5-5 (text), consensus claude-sonnet-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF