AT32F435RGT7

ARTERY · Microcontrollers (MCU/MPU/SOC) · LQFP-64(10x10)

AT32F435RGT7 from ARTERY, in a LQFP-64(10x10). Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin	Name	Type	Function
1	VBAT	power_in	Battery supply for the VBAT domain (LEXT, ERTC and BPR) with a 1.62 to 3.6 V operating range; it powers that domain when VDD is absent.
2	PC13	bidirectional	5 V tolerant (FT) GPIO with ERTC_AF1 and WKUP2 functions; it is powered through a power switch limited to 3 mA, so it cannot source current such as driving an LED when used as output.
3	PC14 / LEXT_IN	bidirectional	Standard-level (TC, not 5 V tolerant) GPIO that doubles as the LEXT_IN 32.768 kHz oscillator input; it is limited to 3 mA when used as output via the power switch.
4	PC15 / LEXT_OUT	bidirectional	Standard-level (TC, not 5 V tolerant) GPIO that doubles as the LEXT_OUT 32.768 kHz oscillator output; it is limited to 3 mA when used as output via the power switch.
5	PH0 / HEXT_IN	bidirectional	Standard-level (TC, not 5 V tolerant) GPIO that doubles as the HEXT_IN 4 to 25 MHz crystal oscillator input, with I2C1_SDA as alternate function.
6	PH1 / HEXT_OUT	bidirectional	Standard-level (TC, not 5 V tolerant) GPIO that doubles as the HEXT_OUT 4 to 25 MHz crystal oscillator output, with I2C1_SCL as alternate function.
7	NRST	bidirectional	Active-low device reset input and internal reset output with built-in weak pull-up (RPU 30 to 50 kΩ); VIL max 0.8 V and VIH min 2 V.
8	PC0	bidirectional	5 V tolerant GPIO with analog function (FTa, not 5 V tolerant in analog mode, input must stay below VDD+0.3 V); alternate functions include I2C3_SCL, UART7_TX, SDIO2_D0, XMC_SDNWE and ADC123_IN10 (fast channel).
9	PC1	bidirectional	5 V tolerant GPIO with analog function (FTa, not 5 V tolerant in analog mode, input must stay below VDD+0.3 V); alternate functions include I2C3_SDA, SPI2_MOSI, I2S2_SD, UART7_RX, EMAC_MDC and ADC123_IN11 (fast channel).
10	PC2	bidirectional	5 V tolerant GPIO with analog function (FTa, not 5 V tolerant in analog mode, input must stay below VDD+0.3 V); alternate functions include TMR20_CH2, SPI2_MISO, UART8_TX, SDIO2_D2, XMC_SDCS0 and ADC123_IN12 (fast channel).
11	PC3	bidirectional	5 V tolerant GPIO with analog function (FTa, not 5 V tolerant in analog mode, input must stay below VDD+0.3 V); alternate functions include SPI2_MOSI, I2S2_SD, UART8_RX, QSPI2_IO1, SDIO2_D3 and ADC123_IN13 (fast channel).
12	VSSA/VREF-	power_in	Analog ground and negative reference voltage for the ADC and DAC; it must be connected to VSS.
13	VDDA/VREF+	power_in	Combined analog supply and positive reference on this package; VDDA must equal VDD (2.6 to 3.6 V) and VREF+ is 2.0 to 3.6 V for the DAC.
14	PA0	bidirectional	5 V tolerant GPIO with analog function (FTa, not 5 V tolerant in analog mode); alternate functions include TMR2_CH1, USART2_CTS, UART4_TX, ADC123_IN0 (fast channel), ERTC_AF2 and WKUP1.
15	PA1	bidirectional	5 V tolerant GPIO with analog function (FTa, not 5 V tolerant in analog mode); alternate functions include TMR2_CH2, I2C2_SDA, USART2_RTS_DE, UART4_RX, EMAC_RMII_REF_CLK and ADC123_IN1 (fast channel).
16	PA2	bidirectional	5 V tolerant GPIO with analog function (FTa, not 5 V tolerant in analog mode); alternate functions include TMR2_CH3, TMR9_CH1, USART2_TX, SDIO2_CK, EMAC_MDIO, XMC_D4 and ADC123_IN2.
17	PA3	bidirectional	5 V tolerant GPIO with analog function (FTa, not 5 V tolerant in analog mode); alternate functions include TMR2_CH4, TMR9_CH2, I2S2_MCK, USART2_RX, SDIO2_CMD, XMC_D5 and ADC123_IN3.
18	VSS	power_in	Digital ground.
19	VDD	power_in	Digital supply voltage, 2.6 to 3.6 V (3.0 to 3.6 V required when LDO is 1.3 V and ERTC is accessed).
20	PA4	bidirectional	5 V tolerant GPIO with analog function (FTa, not 5 V tolerant in analog mode); alternate functions include SPI1_CS, I2S1_WS, USART2_CK, SDIO2_D4, DVP_HSYNC, XMC_D6, ADC12_IN4 and DAC1_OUT.
21	PA5	bidirectional	5 V tolerant GPIO with analog function (FTa, not 5 V tolerant in analog mode); alternate functions include TMR2_CH1, SPI1_SCK, I2S1_CK, USART6_RX, XMC_D7, ADC12_IN5 and DAC2_OUT.
22	PA6	bidirectional	5 V tolerant GPIO with analog function (FTa, not 5 V tolerant in analog mode); alternate functions include TMR1_BRK, TMR3_CH1, SPI1_MISO, I2S2_MCK, USART3_CTS, SDIO1_CMD, DVP_PCLK and ADC12_IN6.
23	PA7	bidirectional	5 V tolerant GPIO with analog function (FTa, not 5 V tolerant in analog mode); alternate functions include TMR1_CH1C, TMR3_CH2, SPI1_MOSI, I2S1_SD, EMAC_RMII_CRS_DV, XMC_SDNWE, SDIO2_D3 and ADC12_IN7.
24	PC4	bidirectional	5 V tolerant GPIO with analog function (FTa, not 5 V tolerant in analog mode); alternate functions include TMR9_CH1, I2S1_MCK, USART3_TX, EMAC_RMII_RXD0, XMC_SDCS0, SDIO2_CK, XMC_NE4 and ADC12_IN14.
25	PC5	bidirectional	5 V tolerant GPIO with analog function (FTa, not 5 V tolerant in analog mode); alternate functions include TMR9_CH2, I2C1_SMBA, USART3_RX, EMAC_RMII_RXD1, XMC_SDCKE0, SDIO2_CMD, XMC_NOE and ADC12_IN15.
26	PB0	bidirectional	5 V tolerant GPIO with analog function (FTa, not 5 V tolerant in analog mode); alternate functions include TMR1_CH2C, TMR3_CH3, I2S1_MCK, USART2_RX, SPI3_MOSI, QSPI2_IO0, EMAC_MII_RXD2, SDIO1_D1 and ADC12_IN8.
27	PB1	bidirectional	5 V tolerant GPIO with analog function (FTa, not 5 V tolerant in analog mode); alternate functions include TMR1_CH3C, TMR3_CH4, SPI2_SCK, I2S2_CK, USART3_RTS_DE, QSPI1_SCK, EMAC_MII_RXD3, SDIO1_D2 and ADC12_IN9.
28	PB2 / BOOT1	bidirectional	5 V tolerant GPIO (FT) whose reset function is PB2; alternate functions include TMR2_CH4, TMR20_CH1, SPI3_MOSI, QSPI1_SCK and SDIO1_CK.
29	PB10	bidirectional	5 V tolerant GPIO with 20 mA sink capability (FTf); alternate functions include TMR2_CH3, I2C2_SCL, SPI2_SCK, I2S3_MCK, USART3_TX, QSPI1_CS, EMAC_MII_RX_ER, SDIO1_D7 and XMC_NOE.
30	PB11	bidirectional	5 V tolerant GPIO (FT); alternate functions include TMR2_CH4, TMR5_CH4, I2C2_SDA, USART3_RX, QSPI1_IO0, EMAC_MII_TX_EN and EMAC_RMII_TX_EN.
31	PH3	bidirectional	5 V tolerant GPIO (FT); alternate functions include TMR5_CH2, I2C2_SDA, UART4_TX and QSPI1_IO1.
32	VDD	power_in	Digital supply voltage, 2.6 to 3.6 V.
33	PB12	bidirectional	5 V tolerant GPIO (FT); alternate functions include TMR1_BRK, TMR5_CH1, I2C2_SMBA, SPI2_CS, I2S2_WS, SPI4_CS, CAN2_RX, EMAC_RMII_TXD0, OTGFS2_ID and XMC_D13.
34	PB13	bidirectional	5 V tolerant GPIO (FT); alternate functions include TMR1_CH1C, I2C3_SMBA, SPI2_SCK, I2S2_CK, SPI4_SCK, I2C3_SCL, USART3_CTS, CAN2_TX, EMAC_RMII_TXD1 and OTGFS2_VBUS.
35	PB14	bidirectional	Standard-level (TC, not 5 V tolerant) GPIO; alternate functions include TMR1_CH2C, TMR8_CH2C, I2C3_SDA, SPI2_MISO, USART3_RTS_DE, TMR12_CH1, OTGFS2_D-, SDIO1_D6 and XMC_D0.
36	PB15	bidirectional	Standard-level (TC, not 5 V tolerant) GPIO; alternate functions include ERTC_REFIN, TMR1_CH3C, TMR8_CH3C, I2C3_SCL, SPI2_MOSI, I2S2_SD, TMR12_CH2, OTGFS2_D+ and SDIO1_CK.
37	PC6	bidirectional	5 V tolerant GPIO (FT); alternate functions include TMR3_CH1, TMR8_CH1, I2C1_SCL, I2S2_MCK, USART6_TX, XMC_A0, SDIO1_D6 and DVP_D0.
38	PC7	bidirectional	5 V tolerant GPIO (FT); alternate functions include TMR3_CH2, TMR8_CH2, I2C1_SDA, SPI2_SCK, I2S2_CK, I2S3_MCK, USART6_RX, XMC_A1, SDIO1_D7 and DVP_D1.
39	PC8	bidirectional	5 V tolerant GPIO (FT); alternate functions include TMR3_CH3, TMR8_CH3, I2S4_MCK, TMR20_CH3, UART8_TX, USART6_CK, QSPI1_IO2, XMC_A2, SDIO1_D0 and DVP_D2.
40	PC9	bidirectional	5 V tolerant GPIO (FT); alternate functions include CLKOUT2, TMR3_CH4, TMR8_CH4, I2C3_SDA, UART8_RX, QSPI1_IO0, XMC_A3, OTGFS2_OE, SDIO1_D1 and DVP_D3.
41	PA8	bidirectional	5 V tolerant GPIO (FT); alternate functions include CLKOUT1, TMR1_CH1, I2C3_SCL, USART1_CK, USART2_TX, OTGFS1_SOF, SDIO1_D1 and XMC_A4.
42	PA9	bidirectional	5 V tolerant GPIO (FT); alternate functions include TMR1_CH2, I2C3_SMBA, SPI2_SCK, I2S2_CK, USART1_TX, I2C1_SCL, OTGFS1_VBUS, SDIO1_D2 and DVP_D0.
43	PA10	bidirectional	5 V tolerant GPIO (FT); alternate functions include TMR1_CH3, SPI2_MOSI, I2S2_SD, I2S4_MCK, USART1_RX, I2C1_SDA, OTGFS1_ID and DVP_D1.
44	PA11	bidirectional	Standard-level (TC, not 5 V tolerant) GPIO; alternate functions include TMR1_CH4, I2C2_SCL, SPI2_CS, I2S2_WS, SPI4_MISO, USART1_CTS, USART6_TX, CAN1_RX, OTGFS1_D- and DVP_D2.
45	PA12	bidirectional	Standard-level (TC, not 5 V tolerant) GPIO; alternate functions include TMR1_EXT, I2C2_SDA, SPI2_MISO, USART1_RTS_DE, USART6_RX, CAN1_TX, OTGFS1_D+ and DVP_D3.
46	PA13	bidirectional	5 V tolerant GPIO (FT) that is the JTMS/SWDIO serial-wire debug data pin after reset; alternate functions include IR_OUT, SPI3_MISO and OTGFS1_OE.
47	PH2	bidirectional	5 V tolerant GPIO (FT); alternate functions include TMR5_CH1, I2C2_SCL, UART4_RX and QSPI1_IO0.
48	VDD	power_in	Digital supply voltage, 2.6 to 3.6 V.
49	PA14	bidirectional	5 V tolerant GPIO (FT) that is the JTCK/SWCLK serial-wire debug clock pin after reset; alternate functions include SPI3_MOSI, I2S3_SD and USART2_TX.
50	PA15	bidirectional	5 V tolerant GPIO (FT) that is the JTDI debug input pin after reset; alternate functions include TMR2_CH1, SPI1_CS, I2S1_WS, SPI3_CS, USART1_TX, USART2_RX, QSPI2_IO1 and XMC_NE2.
51	PC10	bidirectional	5 V tolerant GPIO (FT); alternate functions include TMR5_CH2, SPI3_SCK, I2S3_CK, USART3_TX, UART4_TX, QSPI1_IO1, SDIO1_D2 and DVP_D8.
52	PC11	bidirectional	5 V tolerant GPIO (FT); alternate functions include TMR5_CH3, SPI3_MISO, USART3_RX, UART4_RX, QSPI1_CS, SDIO1_D3, DVP_D4 and XMC_D2.
53	PC12	bidirectional	5 V tolerant GPIO (FT); alternate functions include TMR11_CH1, I2C2_SDA, SPI3_MOSI, I2S3_SD, USART3_CK, UART5_TX, SDIO1_CK, DVP_D9 and XMC_D3.
54	PD2	bidirectional	5 V tolerant GPIO (FT); alternate functions include TMR3_EXT, USART3_RTS_DE, UART5_RX, XMC_A7, SDIO1_CMD, DVP_D11 and XMC_NWE.
55	PB3	bidirectional	5 V tolerant GPIO with 20 mA sink capability (FTf) that is the JTDO/SWO trace pin after reset; alternate functions include TMR2_CH2, SPI1_SCK, I2S1_CK, SPI3_SCK, USART1_RX, QSPI1_IO3 and DVP_D4.
56	PB4	bidirectional	5 V tolerant GPIO (FT) that is the NJTRST JTAG reset pin after reset; alternate functions include TMR3_CH1, SPI1_MISO, SPI3_MISO, UART7_TX, SDIO1_D0 and DVP_D5.
57	PB5	bidirectional	5 V tolerant GPIO (FT); alternate functions include TMR3_CH2, I2C1_SMBA, SPI1_MOSI, I2S1_SD, SPI3_MOSI, USART1_CK, UART5_RX, CAN2_RX, EMAC_PPS_OUT, XMC_SDCKE1, DVP_D10 and SDIO1_D3.
58	PB6	bidirectional	5 V tolerant GPIO (FT); alternate functions include TMR4_CH1, I2C1_SCL, I2S1_MCK, SPI4_CS, USART1_TX, UART5_TX, CAN2_TX, QSPI1_CS, XMC_SDCS1, DVP_D5 and SDIO1_D0.
59	PB7	bidirectional	5 V tolerant GPIO (FT); alternate functions include TMR4_CH2, TMR8_BRK, I2C1_SDA, SPI4_SCK, I2S4_CK, USART1_RX, QSPI2_IO1, XMC_NADV, DVP_VSYNC and SDIO1_D0.
60	BOOT0	input	Dedicated boot-mode pin with a built-in weak pull-down (RPD 60 to 100 kΩ) that cannot be disabled.
61	PB8	bidirectional	5 V tolerant GPIO (FT); alternate functions include TMR2_CH1, TMR4_CH3, TMR10_CH1, I2C1_SCL, SPI4_MISO, UART5_RX, CAN1_RX, QSPI2_CS, EMAC_MII_TXD3, SDIO1_D4 and DVP_D6.
62	PB9	bidirectional	5 V tolerant GPIO with 20 mA sink capability (FTf); alternate functions include IR_OUT, TMR2_CH2, TMR4_CH4, TMR11_CH1, I2C1_SDA, SPI2_CS/I2S2_WS, SPI4_MOSI, UART5_TX, CAN1_TX, QSPI1_CS, SDIO1_D5 and DVP_D7.
63	VSS	power_in	Digital ground.
64	VDD	power_in	Digital supply voltage, 2.6 to 3.6 V.

Key specifications

Parameter	Value
Manufacturer	ARTERY
Package	LQFP-64(10x10)
Category	Embedded Processors & Controllers
Pins	64

Electrical characteristics

Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).

Parameter	Symbol	Min	Typ	Max	Unit	Conditions	Page
VDDx-VSS external main supply voltage	VDDx-VSS	-0.3		4	V		47
Input voltage on FTa pin, input floating / pull-up / pull-down mode	VIN	-0.3		6	V	FTa pin set to input floating, input pull-up or pull-down mode; min printed as VSS-0.3	47
Input voltage on TC pin	VIN	-0.3		4	V	TC pin; min printed as VSS-0.3	47
Voltage difference between supply pins	/ΔVDDx/			50	mV		47
Voltage difference between ground pins	/VSSx-VSS/			50	mV		47
Total current into VDD power lines (incl. VDDA and VDD)	IVDD			250	mA	external main supply current including VDDA and VDD	47
Total current out of VSS ground lines	IVSS			250	mA	total current flowing out of VSS ground line	47
Output sink current on any GPIO and control pin	IIO			25	mA	any GPIO and control pin, sink	47
Output current on any GPIO and control pin (source)	IIO	-25			mA	any GPIO and control pin, source; value printed as -25	47
Storage temperature range	TSTG	-60		150	°C		47
Maximum junction temperature	TJ			125	°C		47
SD/MMC data transfer mode clock frequency	fPP	0		48	MHz	data transfer mode	94
Clock low time	tW(CKL)	32			ns		94
Clock high time	tW(CKH)	30			ns		94
Clock rise time	tr			4	ns		94
Clock fall time	tf			5	ns		94
CMD, D input setup time to CK	tISU	2			ns	CMD, D input relative to CK	94
CMD, D input hold time from CK	tIH	0			ns	CMD, D input relative to CK	94
CMD, D output valid time (MMC and SD high-speed mode)	tOV			6	ns	MMC and SD high-speed mode, CMD, D output relative to CK	94
CMD, D output hold time (MMC and SD high-speed mode)	tOH	0			ns	MMC and SD high-speed mode, CMD, D output relative to CK	94
CMD, D output valid default time (SD default mode)	tOVD			7	ns	SD default mode, CMD, D output relative to CK	94
CMD, D output hold default time (SD default mode)	tOHD	0.5			ns	SD default mode, CMD, D output relative to CK	94
OTGFS transceiver startup time	tSTARTUP			1	μs	design guaranteed, not production tested	95
OTGFS operating voltage	VDD	3		3.6	V		95
Differential input sensitivity on OTGFS_D+/D-	VDI	0.2			V		95
Differential common-mode range	VCM	0.8		2.5	V	includes VDI range	95
Single-ended receiver threshold	VSE		1.3	2	V		95
Static output low level	VOL			0.3	V	RL of 1.24 kΩ connected to 3.6 V	95
Static output high level	VOH	2.8		3.6	V	RL of 15 kΩ connected to VSS	95
OTGFS_D+ internal pull-up resistor	RPU	0.97	1.24	1.58	kΩ	VIN = VSS	95
OTGFS_D+/D- internal pull-down resistor	RPD	15	19	25	kΩ	VIN = VDD	95
OTGFS data rise time	tr	4		20	ns	CL ≤ 50 pF	95
OTGFS data fall time	tf	4		20	ns	CL ≤ 50 pF	95
OTGFS rise/fall time matching (tr/tf)	trfm	90		110	%		95
OTGFS output signal crossover voltage	VCRS	1.3		2	V		95
Supply voltage range (features summary)		2.6		3.6	V	power supply, per features summary (not a table)	1
Operating temperature range		-40		105	°C	temperature range, per features summary	1

CAD (KiCad official)

Symbol: AT32F435RGT7
Footprint: Package_QFP:LQFP-64_10x10mm_P0.5mm
3D model: LQFP-64(10x10) (KiCad packages3D, STEP)
3D model files: at32f435rgt7-etched.step / at32f435rgt7-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); at32f435rgt7.step / at32f435rgt7.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

Datasheet: ARTERY datasheet (118 pp, sha256 1dc0c659f12e7670, retrieved 2026-10-19, tier: lcsc)
Datasheet language: Chinese. Pin names, descriptions, and specs on this page were extracted and translated to English by ds2sf; the linked PDF is the manufacturer original.
Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-haiku-5-5 (text), consensus claude-sonnet-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF

# AT32F435RGT7

**ARTERY** · Microcontrollers (MCU/MPU/SOC) · LQFP-64(10x10)

AT32F435RGT7 from ARTERY, in a LQFP-64(10x10). Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

## Pinout

| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | VBAT | power_in | Battery supply for the VBAT domain (LEXT, ERTC and BPR) with a 1.62 to 3.6 V operating range; it powers that domain when VDD is absent. |
| 2 | PC13 | bidirectional | 5 V tolerant (FT) GPIO with ERTC_AF1 and WKUP2 functions; it is powered through a power switch limited to 3 mA, so it cannot source current such as driving an LED when used as output. |
| 3 | PC14 / LEXT_IN | bidirectional | Standard-level (TC, not 5 V tolerant) GPIO that doubles as the LEXT_IN 32.768 kHz oscillator input; it is limited to 3 mA when used as output via the power switch. |
| 4 | PC15 / LEXT_OUT | bidirectional | Standard-level (TC, not 5 V tolerant) GPIO that doubles as the LEXT_OUT 32.768 kHz oscillator output; it is limited to 3 mA when used as output via the power switch. |
| 5 | PH0 / HEXT_IN | bidirectional | Standard-level (TC, not 5 V tolerant) GPIO that doubles as the HEXT_IN 4 to 25 MHz crystal oscillator input, with I2C1_SDA as alternate function. |
| 6 | PH1 / HEXT_OUT | bidirectional | Standard-level (TC, not 5 V tolerant) GPIO that doubles as the HEXT_OUT 4 to 25 MHz crystal oscillator output, with I2C1_SCL as alternate function. |
| 7 | NRST | bidirectional | Active-low device reset input and internal reset output with built-in weak pull-up (RPU 30 to 50 kΩ); VIL max 0.8 V and VIH min 2 V. |
| 8 | PC0 | bidirectional | 5 V tolerant GPIO with analog function (FTa, not 5 V tolerant in analog mode, input must stay below VDD+0.3 V); alternate functions include I2C3_SCL, UART7_TX, SDIO2_D0, XMC_SDNWE and ADC123_IN10 (fast channel). |
| 9 | PC1 | bidirectional | 5 V tolerant GPIO with analog function (FTa, not 5 V tolerant in analog mode, input must stay below VDD+0.3 V); alternate functions include I2C3_SDA, SPI2_MOSI, I2S2_SD, UART7_RX, EMAC_MDC and ADC123_IN11 (fast channel). |
| 10 | PC2 | bidirectional | 5 V tolerant GPIO with analog function (FTa, not 5 V tolerant in analog mode, input must stay below VDD+0.3 V); alternate functions include TMR20_CH2, SPI2_MISO, UART8_TX, SDIO2_D2, XMC_SDCS0 and ADC123_IN12 (fast channel). |
| 11 | PC3 | bidirectional | 5 V tolerant GPIO with analog function (FTa, not 5 V tolerant in analog mode, input must stay below VDD+0.3 V); alternate functions include SPI2_MOSI, I2S2_SD, UART8_RX, QSPI2_IO1, SDIO2_D3 and ADC123_IN13 (fast channel). |
| 12 | VSSA/VREF- | power_in | Analog ground and negative reference voltage for the ADC and DAC; it must be connected to VSS. |
| 13 | VDDA/VREF+ | power_in | Combined analog supply and positive reference on this package; VDDA must equal VDD (2.6 to 3.6 V) and VREF+ is 2.0 to 3.6 V for the DAC. |
| 14 | PA0 | bidirectional | 5 V tolerant GPIO with analog function (FTa, not 5 V tolerant in analog mode); alternate functions include TMR2_CH1, USART2_CTS, UART4_TX, ADC123_IN0 (fast channel), ERTC_AF2 and WKUP1. |
| 15 | PA1 | bidirectional | 5 V tolerant GPIO with analog function (FTa, not 5 V tolerant in analog mode); alternate functions include TMR2_CH2, I2C2_SDA, USART2_RTS_DE, UART4_RX, EMAC_RMII_REF_CLK and ADC123_IN1 (fast channel). |
| 16 | PA2 | bidirectional | 5 V tolerant GPIO with analog function (FTa, not 5 V tolerant in analog mode); alternate functions include TMR2_CH3, TMR9_CH1, USART2_TX, SDIO2_CK, EMAC_MDIO, XMC_D4 and ADC123_IN2. |
| 17 | PA3 | bidirectional | 5 V tolerant GPIO with analog function (FTa, not 5 V tolerant in analog mode); alternate functions include TMR2_CH4, TMR9_CH2, I2S2_MCK, USART2_RX, SDIO2_CMD, XMC_D5 and ADC123_IN3. |
| 18 | VSS | power_in | Digital ground. |
| 19 | VDD | power_in | Digital supply voltage, 2.6 to 3.6 V (3.0 to 3.6 V required when LDO is 1.3 V and ERTC is accessed). |
| 20 | PA4 | bidirectional | 5 V tolerant GPIO with analog function (FTa, not 5 V tolerant in analog mode); alternate functions include SPI1_CS, I2S1_WS, USART2_CK, SDIO2_D4, DVP_HSYNC, XMC_D6, ADC12_IN4 and DAC1_OUT. |
| 21 | PA5 | bidirectional | 5 V tolerant GPIO with analog function (FTa, not 5 V tolerant in analog mode); alternate functions include TMR2_CH1, SPI1_SCK, I2S1_CK, USART6_RX, XMC_D7, ADC12_IN5 and DAC2_OUT. |
| 22 | PA6 | bidirectional | 5 V tolerant GPIO with analog function (FTa, not 5 V tolerant in analog mode); alternate functions include TMR1_BRK, TMR3_CH1, SPI1_MISO, I2S2_MCK, USART3_CTS, SDIO1_CMD, DVP_PCLK and ADC12_IN6. |
| 23 | PA7 | bidirectional | 5 V tolerant GPIO with analog function (FTa, not 5 V tolerant in analog mode); alternate functions include TMR1_CH1C, TMR3_CH2, SPI1_MOSI, I2S1_SD, EMAC_RMII_CRS_DV, XMC_SDNWE, SDIO2_D3 and ADC12_IN7. |
| 24 | PC4 | bidirectional | 5 V tolerant GPIO with analog function (FTa, not 5 V tolerant in analog mode); alternate functions include TMR9_CH1, I2S1_MCK, USART3_TX, EMAC_RMII_RXD0, XMC_SDCS0, SDIO2_CK, XMC_NE4 and ADC12_IN14. |
| 25 | PC5 | bidirectional | 5 V tolerant GPIO with analog function (FTa, not 5 V tolerant in analog mode); alternate functions include TMR9_CH2, I2C1_SMBA, USART3_RX, EMAC_RMII_RXD1, XMC_SDCKE0, SDIO2_CMD, XMC_NOE and ADC12_IN15. |
| 26 | PB0 | bidirectional | 5 V tolerant GPIO with analog function (FTa, not 5 V tolerant in analog mode); alternate functions include TMR1_CH2C, TMR3_CH3, I2S1_MCK, USART2_RX, SPI3_MOSI, QSPI2_IO0, EMAC_MII_RXD2, SDIO1_D1 and ADC12_IN8. |
| 27 | PB1 | bidirectional | 5 V tolerant GPIO with analog function (FTa, not 5 V tolerant in analog mode); alternate functions include TMR1_CH3C, TMR3_CH4, SPI2_SCK, I2S2_CK, USART3_RTS_DE, QSPI1_SCK, EMAC_MII_RXD3, SDIO1_D2 and ADC12_IN9. |
| 28 | PB2 / BOOT1 | bidirectional | 5 V tolerant GPIO (FT) whose reset function is PB2; alternate functions include TMR2_CH4, TMR20_CH1, SPI3_MOSI, QSPI1_SCK and SDIO1_CK. |
| 29 | PB10 | bidirectional | 5 V tolerant GPIO with 20 mA sink capability (FTf); alternate functions include TMR2_CH3, I2C2_SCL, SPI2_SCK, I2S3_MCK, USART3_TX, QSPI1_CS, EMAC_MII_RX_ER, SDIO1_D7 and XMC_NOE. |
| 30 | PB11 | bidirectional | 5 V tolerant GPIO (FT); alternate functions include TMR2_CH4, TMR5_CH4, I2C2_SDA, USART3_RX, QSPI1_IO0, EMAC_MII_TX_EN and EMAC_RMII_TX_EN. |
| 31 | PH3 | bidirectional | 5 V tolerant GPIO (FT); alternate functions include TMR5_CH2, I2C2_SDA, UART4_TX and QSPI1_IO1. |
| 32 | VDD | power_in | Digital supply voltage, 2.6 to 3.6 V. |
| 33 | PB12 | bidirectional | 5 V tolerant GPIO (FT); alternate functions include TMR1_BRK, TMR5_CH1, I2C2_SMBA, SPI2_CS, I2S2_WS, SPI4_CS, CAN2_RX, EMAC_RMII_TXD0, OTGFS2_ID and XMC_D13. |
| 34 | PB13 | bidirectional | 5 V tolerant GPIO (FT); alternate functions include TMR1_CH1C, I2C3_SMBA, SPI2_SCK, I2S2_CK, SPI4_SCK, I2C3_SCL, USART3_CTS, CAN2_TX, EMAC_RMII_TXD1 and OTGFS2_VBUS. |
| 35 | PB14 | bidirectional | Standard-level (TC, not 5 V tolerant) GPIO; alternate functions include TMR1_CH2C, TMR8_CH2C, I2C3_SDA, SPI2_MISO, USART3_RTS_DE, TMR12_CH1, OTGFS2_D-, SDIO1_D6 and XMC_D0. |
| 36 | PB15 | bidirectional | Standard-level (TC, not 5 V tolerant) GPIO; alternate functions include ERTC_REFIN, TMR1_CH3C, TMR8_CH3C, I2C3_SCL, SPI2_MOSI, I2S2_SD, TMR12_CH2, OTGFS2_D+ and SDIO1_CK. |
| 37 | PC6 | bidirectional | 5 V tolerant GPIO (FT); alternate functions include TMR3_CH1, TMR8_CH1, I2C1_SCL, I2S2_MCK, USART6_TX, XMC_A0, SDIO1_D6 and DVP_D0. |
| 38 | PC7 | bidirectional | 5 V tolerant GPIO (FT); alternate functions include TMR3_CH2, TMR8_CH2, I2C1_SDA, SPI2_SCK, I2S2_CK, I2S3_MCK, USART6_RX, XMC_A1, SDIO1_D7 and DVP_D1. |
| 39 | PC8 | bidirectional | 5 V tolerant GPIO (FT); alternate functions include TMR3_CH3, TMR8_CH3, I2S4_MCK, TMR20_CH3, UART8_TX, USART6_CK, QSPI1_IO2, XMC_A2, SDIO1_D0 and DVP_D2. |
| 40 | PC9 | bidirectional | 5 V tolerant GPIO (FT); alternate functions include CLKOUT2, TMR3_CH4, TMR8_CH4, I2C3_SDA, UART8_RX, QSPI1_IO0, XMC_A3, OTGFS2_OE, SDIO1_D1 and DVP_D3. |
| 41 | PA8 | bidirectional | 5 V tolerant GPIO (FT); alternate functions include CLKOUT1, TMR1_CH1, I2C3_SCL, USART1_CK, USART2_TX, OTGFS1_SOF, SDIO1_D1 and XMC_A4. |
| 42 | PA9 | bidirectional | 5 V tolerant GPIO (FT); alternate functions include TMR1_CH2, I2C3_SMBA, SPI2_SCK, I2S2_CK, USART1_TX, I2C1_SCL, OTGFS1_VBUS, SDIO1_D2 and DVP_D0. |
| 43 | PA10 | bidirectional | 5 V tolerant GPIO (FT); alternate functions include TMR1_CH3, SPI2_MOSI, I2S2_SD, I2S4_MCK, USART1_RX, I2C1_SDA, OTGFS1_ID and DVP_D1. |
| 44 | PA11 | bidirectional | Standard-level (TC, not 5 V tolerant) GPIO; alternate functions include TMR1_CH4, I2C2_SCL, SPI2_CS, I2S2_WS, SPI4_MISO, USART1_CTS, USART6_TX, CAN1_RX, OTGFS1_D- and DVP_D2. |
| 45 | PA12 | bidirectional | Standard-level (TC, not 5 V tolerant) GPIO; alternate functions include TMR1_EXT, I2C2_SDA, SPI2_MISO, USART1_RTS_DE, USART6_RX, CAN1_TX, OTGFS1_D+ and DVP_D3. |
| 46 | PA13 | bidirectional | 5 V tolerant GPIO (FT) that is the JTMS/SWDIO serial-wire debug data pin after reset; alternate functions include IR_OUT, SPI3_MISO and OTGFS1_OE. |
| 47 | PH2 | bidirectional | 5 V tolerant GPIO (FT); alternate functions include TMR5_CH1, I2C2_SCL, UART4_RX and QSPI1_IO0. |
| 48 | VDD | power_in | Digital supply voltage, 2.6 to 3.6 V. |
| 49 | PA14 | bidirectional | 5 V tolerant GPIO (FT) that is the JTCK/SWCLK serial-wire debug clock pin after reset; alternate functions include SPI3_MOSI, I2S3_SD and USART2_TX. |
| 50 | PA15 | bidirectional | 5 V tolerant GPIO (FT) that is the JTDI debug input pin after reset; alternate functions include TMR2_CH1, SPI1_CS, I2S1_WS, SPI3_CS, USART1_TX, USART2_RX, QSPI2_IO1 and XMC_NE2. |
| 51 | PC10 | bidirectional | 5 V tolerant GPIO (FT); alternate functions include TMR5_CH2, SPI3_SCK, I2S3_CK, USART3_TX, UART4_TX, QSPI1_IO1, SDIO1_D2 and DVP_D8. |
| 52 | PC11 | bidirectional | 5 V tolerant GPIO (FT); alternate functions include TMR5_CH3, SPI3_MISO, USART3_RX, UART4_RX, QSPI1_CS, SDIO1_D3, DVP_D4 and XMC_D2. |
| 53 | PC12 | bidirectional | 5 V tolerant GPIO (FT); alternate functions include TMR11_CH1, I2C2_SDA, SPI3_MOSI, I2S3_SD, USART3_CK, UART5_TX, SDIO1_CK, DVP_D9 and XMC_D3. |
| 54 | PD2 | bidirectional | 5 V tolerant GPIO (FT); alternate functions include TMR3_EXT, USART3_RTS_DE, UART5_RX, XMC_A7, SDIO1_CMD, DVP_D11 and XMC_NWE. |
| 55 | PB3 | bidirectional | 5 V tolerant GPIO with 20 mA sink capability (FTf) that is the JTDO/SWO trace pin after reset; alternate functions include TMR2_CH2, SPI1_SCK, I2S1_CK, SPI3_SCK, USART1_RX, QSPI1_IO3 and DVP_D4. |
| 56 | PB4 | bidirectional | 5 V tolerant GPIO (FT) that is the NJTRST JTAG reset pin after reset; alternate functions include TMR3_CH1, SPI1_MISO, SPI3_MISO, UART7_TX, SDIO1_D0 and DVP_D5. |
| 57 | PB5 | bidirectional | 5 V tolerant GPIO (FT); alternate functions include TMR3_CH2, I2C1_SMBA, SPI1_MOSI, I2S1_SD, SPI3_MOSI, USART1_CK, UART5_RX, CAN2_RX, EMAC_PPS_OUT, XMC_SDCKE1, DVP_D10 and SDIO1_D3. |
| 58 | PB6 | bidirectional | 5 V tolerant GPIO (FT); alternate functions include TMR4_CH1, I2C1_SCL, I2S1_MCK, SPI4_CS, USART1_TX, UART5_TX, CAN2_TX, QSPI1_CS, XMC_SDCS1, DVP_D5 and SDIO1_D0. |
| 59 | PB7 | bidirectional | 5 V tolerant GPIO (FT); alternate functions include TMR4_CH2, TMR8_BRK, I2C1_SDA, SPI4_SCK, I2S4_CK, USART1_RX, QSPI2_IO1, XMC_NADV, DVP_VSYNC and SDIO1_D0. |
| 60 | BOOT0 | input | Dedicated boot-mode pin with a built-in weak pull-down (RPD 60 to 100 kΩ) that cannot be disabled. |
| 61 | PB8 | bidirectional | 5 V tolerant GPIO (FT); alternate functions include TMR2_CH1, TMR4_CH3, TMR10_CH1, I2C1_SCL, SPI4_MISO, UART5_RX, CAN1_RX, QSPI2_CS, EMAC_MII_TXD3, SDIO1_D4 and DVP_D6. |
| 62 | PB9 | bidirectional | 5 V tolerant GPIO with 20 mA sink capability (FTf); alternate functions include IR_OUT, TMR2_CH2, TMR4_CH4, TMR11_CH1, I2C1_SDA, SPI2_CS/I2S2_WS, SPI4_MOSI, UART5_TX, CAN1_TX, QSPI1_CS, SDIO1_D5 and DVP_D7. |
| 63 | VSS | power_in | Digital ground. |
| 64 | VDD | power_in | Digital supply voltage, 2.6 to 3.6 V. |

## Key specifications

| Parameter | Value |
|---|---|
| Manufacturer | ARTERY |
| Package | LQFP-64(10x10) |
| Category | Embedded Processors & Controllers |
| Pins | 64 |

## Electrical characteristics

Limits as printed in the datasheet (page.json `metadata.characteristics` carries them as data).

| Parameter | Symbol | Min | Typ | Max | Unit | Conditions | Page |
|---|---|---|---|---|---|---|---|
| VDDx-VSS external main supply voltage | VDDx-VSS | -0.3 |  | 4 | V |  | 47 |
| Input voltage on FTa pin, input floating / pull-up / pull-down mode | VIN | -0.3 |  | 6 | V | FTa pin set to input floating, input pull-up or pull-down mode; min printed as VSS-0.3 | 47 |
| Input voltage on TC pin | VIN | -0.3 |  | 4 | V | TC pin; min printed as VSS-0.3 | 47 |
| Voltage difference between supply pins | /ΔVDDx/ |  |  | 50 | mV |  | 47 |
| Voltage difference between ground pins | /VSSx-VSS/ |  |  | 50 | mV |  | 47 |
| Total current into VDD power lines (incl. VDDA and VDD) | IVDD |  |  | 250 | mA | external main supply current including VDDA and VDD | 47 |
| Total current out of VSS ground lines | IVSS |  |  | 250 | mA | total current flowing out of VSS ground line | 47 |
| Output sink current on any GPIO and control pin | IIO |  |  | 25 | mA | any GPIO and control pin, sink | 47 |
| Output current on any GPIO and control pin (source) | IIO | -25 |  |  | mA | any GPIO and control pin, source; value printed as -25 | 47 |
| Storage temperature range | TSTG | -60 |  | 150 | °C |  | 47 |
| Maximum junction temperature | TJ |  |  | 125 | °C |  | 47 |
| SD/MMC data transfer mode clock frequency | fPP | 0 |  | 48 | MHz | data transfer mode | 94 |
| Clock low time | tW(CKL) | 32 |  |  | ns |  | 94 |
| Clock high time | tW(CKH) | 30 |  |  | ns |  | 94 |
| Clock rise time | tr |  |  | 4 | ns |  | 94 |
| Clock fall time | tf |  |  | 5 | ns |  | 94 |
| CMD, D input setup time to CK | tISU | 2 |  |  | ns | CMD, D input relative to CK | 94 |
| CMD, D input hold time from CK | tIH | 0 |  |  | ns | CMD, D input relative to CK | 94 |
| CMD, D output valid time (MMC and SD high-speed mode) | tOV |  |  | 6 | ns | MMC and SD high-speed mode, CMD, D output relative to CK | 94 |
| CMD, D output hold time (MMC and SD high-speed mode) | tOH | 0 |  |  | ns | MMC and SD high-speed mode, CMD, D output relative to CK | 94 |
| CMD, D output valid default time (SD default mode) | tOVD |  |  | 7 | ns | SD default mode, CMD, D output relative to CK | 94 |
| CMD, D output hold default time (SD default mode) | tOHD | 0.5 |  |  | ns | SD default mode, CMD, D output relative to CK | 94 |
| OTGFS transceiver startup time | tSTARTUP |  |  | 1 | μs | design guaranteed, not production tested | 95 |
| OTGFS operating voltage | VDD | 3 |  | 3.6 | V |  | 95 |
| Differential input sensitivity on OTGFS_D+/D- | VDI | 0.2 |  |  | V |  | 95 |
| Differential common-mode range | VCM | 0.8 |  | 2.5 | V | includes VDI range | 95 |
| Single-ended receiver threshold | VSE |  | 1.3 | 2 | V |  | 95 |
| Static output low level | VOL |  |  | 0.3 | V | RL of 1.24 kΩ connected to 3.6 V | 95 |
| Static output high level | VOH | 2.8 |  | 3.6 | V | RL of 15 kΩ connected to VSS | 95 |
| OTGFS_D+ internal pull-up resistor | RPU | 0.97 | 1.24 | 1.58 | kΩ | VIN = VSS | 95 |
| OTGFS_D+/D- internal pull-down resistor | RPD | 15 | 19 | 25 | kΩ | VIN = VDD | 95 |
| OTGFS data rise time | tr | 4 |  | 20 | ns | CL ≤ 50 pF | 95 |
| OTGFS data fall time | tf | 4 |  | 20 | ns | CL ≤ 50 pF | 95 |
| OTGFS rise/fall time matching (tr/tf) | trfm | 90 |  | 110 | % |  | 95 |
| OTGFS output signal crossover voltage | VCRS | 1.3 |  | 2 | V |  | 95 |
| Supply voltage range (features summary) |  | 2.6 |  | 3.6 | V | power supply, per features summary (not a table) | 1 |
| Operating temperature range |  | -40 |  | 105 | °C | temperature range, per features summary | 1 |

## CAD (KiCad official)

- Symbol: `AT32F435RGT7`
- Footprint: `Package_QFP:LQFP-64_10x10mm_P0.5mm`
- 3D model: LQFP-64(10x10) (KiCad packages3D, STEP)
- 3D model files: `at32f435rgt7-etched.step` / `at32f435rgt7-etched.glb` carry the MPN laser-etched on the die in a toggleable `Adom.LaserEtch` group (Fusion-ready); `at32f435rgt7.step` / `at32f435rgt7.glb` are the bare package body.

## Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

- **Datasheet:** [ARTERY datasheet](https://jlcpcb.com/api/file/downloadByFileSystemAccessId/8589835286583939072) (118 pp, sha256 `1dc0c659f12e7670`, retrieved 2026-10-19, tier: lcsc)
- **Datasheet language:** Chinese. Pin names, descriptions, and specs on this page were extracted and translated to English by ds2sf; the linked PDF is the manufacturer original.
- **Extractor:** parts-factory `2.0.0` / `extract_pins 0.3`, primary `claude-haiku-5-5` (text), consensus `claude-sonnet-5-5` (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
- **CAD:** KiCad official libraries (CC-BY-SA 4.0).

[Datasheet PDF](docs/at32f435rgt7-datasheet.pdf)