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AT32F435CGU7

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ARTERY Microcontrollers (MCU/MPU/SOC), QFN-48(6x6). Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.

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AT32F435CGU7

ARTERY · Microcontrollers (MCU/MPU/SOC) · QFN-48(6x6)

AT32F435CGU7 from ARTERY, in a QFN-48(6x6). Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 VBAT power_in Battery supply for the backup domain (ERTC, LEXT, BPR), specified at 1.62 V to 3.6 V, and it supplies these blocks when VDD is absent.
2 PC13 bidirectional 5 V tolerant FT GPIO that is limited to 3 mA through the power switch, so it must not be used as a current source such as an LED driver; also ERTC_AF1 and WKUP2.
3 PC14/LEXT_IN bidirectional Standard-level TC GPIO that is limited to 3 mA through the power switch and also serves as the 32.768 kHz LEXT oscillator input.
4 PC15/LEXT_OUT bidirectional Standard-level TC GPIO that is limited to 3 mA through the power switch and also serves as the 32.768 kHz LEXT oscillator output.
5 PH0/HEXT_IN bidirectional Standard-level TC GPIO (alternate I2C1_SDA) that also serves as the 4 to 25 MHz HEXT crystal oscillator input.
6 PH1/HEXT_OUT bidirectional Standard-level TC GPIO (alternate I2C1_SCL) that also serves as the 4 to 25 MHz HEXT crystal oscillator output.
7 NRST bidirectional Active-low bidirectional device reset input and internal reset output with a built-in pull-up of 30 to 50 kOhm (40 kOhm typical), VIL max 0.8 V and VIH min 2 V.
8 VSSA/VREF- power_in Analog ground and negative reference voltage, which must be connected to VSS.
9 VDDA/VREF+ power_in Analog supply for ADC and DAC (2.6 V to 3.6 V, must equal VDD) that also acts as the positive reference voltage on this package.
10 PA0 bidirectional 5 V tolerant FTa GPIO with ADC123_IN0 (fast channel) and WKUP1; in analog mode the input must stay below VDD + 0.3 V and 5 V tolerance is lost.
11 PA1 bidirectional 5 V tolerant FTa GPIO with ADC123_IN1 (fast channel) and EMAC/RMII reference clock alternate functions; in analog mode the input must stay below VDD + 0.3 V.
12 PA2 bidirectional 5 V tolerant FTa GPIO with ADC123_IN2 and USART2_TX alternate function; in analog mode the input must stay below VDD + 0.3 V.
13 PA3 bidirectional 5 V tolerant FTa GPIO with ADC123_IN3 and USART2_RX alternate function; in analog mode the input must stay below VDD + 0.3 V.
14 PA4 bidirectional 5 V tolerant FTa GPIO with ADC12_IN4 and DAC1_OUT; in analog mode the input must stay below VDD + 0.3 V.
15 PA5 bidirectional 5 V tolerant FTa GPIO with ADC12_IN5 and DAC2_OUT; in analog mode the input must stay below VDD + 0.3 V.
16 PA6 bidirectional 5 V tolerant FTa GPIO with ADC12_IN6; in analog mode the input must stay below VDD + 0.3 V.
17 PA7 bidirectional 5 V tolerant FTa GPIO with ADC12_IN7; in analog mode the input must stay below VDD + 0.3 V.
18 PB0 bidirectional 5 V tolerant FTa GPIO with ADC12_IN8; in analog mode the input must stay below VDD + 0.3 V.
19 PB1 bidirectional 5 V tolerant FTa GPIO with ADC12_IN9; in analog mode the input must stay below VDD + 0.3 V.
20 PB2/BOOT1 bidirectional 5 V tolerant FT GPIO, labeled BOOT1 in the pin definition table, with reset-time function PB2.
21 PB10 bidirectional 5 V tolerant FTf GPIO with 20 mA sink capability, with I2C2_SCL and USART3_TX alternate functions.
22 PB11 bidirectional 5 V tolerant FT GPIO with I2C2_SDA and USART3_RX alternate functions.
23 PH3 bidirectional 5 V tolerant FT GPIO with TMR5_CH2, I2C2_SDA and UART4_TX alternate functions.
24 VDD power_in Digital supply of 2.6 V to 3.6 V (3.0 V to 3.6 V when the LDO is at 1.3 V and ERTC access is needed).
25 PB12 bidirectional 5 V tolerant FT GPIO with OTGFS2_ID and XMC_D13 alternate functions.
26 PB13 bidirectional 5 V tolerant FT GPIO with OTGFS2_VBUS and CAN2_TX alternate functions.
27 PB14 bidirectional Standard-level TC GPIO with OTGFS2_D- alternate function.
28 PB15 bidirectional Standard-level TC GPIO with OTGFS2_D+ and ERTC_REFIN alternate functions.
29 PA8 bidirectional 5 V tolerant FT GPIO with CLKOUT1 and USART1_CK alternate functions.
30 PA9 bidirectional 5 V tolerant FT GPIO with USART1_TX and OTGFS1_VBUS alternate functions; also the bootloader USART1 TX pin.
31 PA10 bidirectional 5 V tolerant FT GPIO with USART1_RX and OTGFS1_ID alternate functions; also the bootloader USART1 RX pin.
32 PA11 bidirectional Standard-level TC GPIO with OTGFS1_D- alternate function.
33 PA12 bidirectional Standard-level TC GPIO with OTGFS1_D+ alternate function.
34 PA13/JTMS/SWDIO bidirectional 5 V tolerant FT GPIO that carries the JTMS/SWDIO serial-wire debug function after reset.
35 PH2 bidirectional 5 V tolerant FT GPIO with TMR5_CH1, I2C2_SCL and UART4_RX alternate functions.
36 VDD power_in Digital supply of 2.6 V to 3.6 V (3.0 V to 3.6 V when the LDO is at 1.3 V and ERTC access is needed).
37 PA14/JTCK/SWCLK bidirectional 5 V tolerant FT GPIO that carries the JTCK/SWCLK serial-wire debug clock function after reset.
38 PA15/JTDI bidirectional 5 V tolerant FT GPIO that carries the JTDI debug function after reset.
39 PB3/JTDO bidirectional 5 V tolerant FTf GPIO with 20 mA sink capability that carries the JTDO function after reset and also SWO.
40 PB4/NJTRST bidirectional 5 V tolerant FT GPIO that carries the NJTRST debug reset function after reset.
41 PB5 bidirectional 5 V tolerant FT GPIO with TMR3_CH2, I2C1_SMBA and CAN2_RX alternate functions.
42 PB6 bidirectional 5 V tolerant FT GPIO with TMR4_CH1, I2C1_SCL and CAN2_TX alternate functions.
43 PB7 bidirectional 5 V tolerant FT GPIO with TMR4_CH2, I2C1_SDA and USART1_RX alternate functions.
44 BOOT0 input Dedicated BOOT0 boot-mode input with a built-in weak pull-down that cannot be disabled.
45 PB8 bidirectional 5 V tolerant FT GPIO with TMR2_CH1, I2C1_SCL and CAN1_RX alternate functions.
46 PB9 bidirectional 5 V tolerant FTf GPIO with 20 mA sink capability and with I2C1_SDA and CAN1_TX alternate functions.
47 VSS power_in Digital ground.
48 VDD power_in Digital supply of 2.6 V to 3.6 V (3.0 V to 3.6 V when the LDO is at 1.3 V and ERTC access is needed).
49 EPAD power_in Exposed pad on the underside of the QFN48 package, specified in the pin table as digital ground.

Key specifications

Parameter Value
Manufacturer ARTERY
Package QFN-48(6x6)
Category Embedded Processors & Controllers
Pins 49

Electrical characteristics

Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).

Parameter Symbol Min Typ Max Unit Conditions Page
External main supply voltage VDDx-VSS VDDx-VSS -0.3 4 V 47
Input voltage on FTa pin, input floating / pull-up / pull-down mode VIN 6 V Pin set to input floating, input pull-up or pull-down mode; minimum printed as VSS-0.3 47
Input voltage on TC pin VIN 4 V Minimum printed as VSS-0.3 47
Voltage difference between different supply pins /ΔVDDx/ 50 mV 47
Voltage difference between different ground pins /VSSx-VSS/ 50 mV 47
Total current through VDDA and VDD supply pins IVDD 250 mA 47
Total current through VSS ground line (outflow) IVSS 250 mA 47
Output sink current on any GPIO and control pin IIO 25 mA 47
Output current on any GPIO and control pin -25 mA 47
Storage temperature range TSTG -60 150 °C 47
Maximum junction temperature TJ 125 °C 47
SD/MMC clock frequency in data transfer mode fPP 0 48 MHz 94
SD/MMC clock low time tW(CKL) 32 ns 94
SD/MMC clock high time tW(CKH) 30 ns 94
SD/MMC clock rise time tr 4 ns 94
SD/MMC clock fall time tf 5 ns 94
CMD, D input clock setup time (referenced to CK) tISU 2 ns 94
CMD, D input clock hold time (referenced to CK) tIH 0 ns 94
CMD, D output valid time (referenced to CK) tOV 6 ns MMC and SD high-speed mode 94
CMD, D output hold time (referenced to CK) tOH 0 ns MMC and SD high-speed mode 94
CMD, D output valid default time (referenced to CK) tOVD 7 ns SD default mode 94
CMD, D output hold default time (referenced to CK) tOHD 0.5 ns SD default mode 94
OTGFS transceiver startup time tSTARTUP 1 μs 95
OTGFS operating voltage VDD 3 3.6 V 95
Differential input sensitivity I(OTGFS_D+/D-) VDI 0.2 V 95
Differential common-mode range VCM 0.8 2.5 V Includes VDI range 95
Single-ended receiver threshold VSE 1.3 2 V 95
Static output low level VOL 0.3 V RL of 1.24 kΩ to 3.6 V 95
Static output high level VOH 2.8 3.6 V RL of 15 kΩ to VSS 95
OTGFS_D+ internal pull-up resistance RPU 0.97 1.24 1.58 kΩ VIN = VSS 95
OTGFS_D+/D- internal pull-down resistance RPD 15 19 25 kΩ VIN = VDD 95
Data signal rise time tr 4 20 ns CL ≤ 50 pF 95
Data signal fall time tf 4 20 ns CL ≤ 50 pF 95
Rise/fall time matching tr/tf trfm 90 110 % 95
Output signal crossover voltage VCRS 1.3 2 V 95

CAD (KiCad official)

  • Symbol: AT32F435CGU7
  • Footprint: Package_DFN_QFN:QFN-48-1EP_6x6mm_P0.4mm_EP4.4x4.4mm
  • 3D model: QFN-48(6x6), generated from the KiCad footprint (body from the F.Fab outline, terminals on the pads, 0.9 mm nominal QFN height). Neither the vendor nor KiCad ships a 3D model for this package, so the dimensions are nominal, not the manufacturer's CAD (STEP)
  • 3D model files: at32f435cgu7-etched.step / at32f435cgu7-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); at32f435cgu7.step / at32f435cgu7.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: ARTERY datasheet (118 pp, sha256 1dc0c659f12e7670, retrieved 2026-10-17, tier: lcsc)
  • Datasheet language: Chinese. Pin names, descriptions, and specs on this page were extracted and translated to English by ds2sf; the linked PDF is the manufacturer original.
  • Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-haiku-5-5 (text), consensus claude-sonnet-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF