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Contents

Pinout
Key specifications
Electrical characteristics
CAD (KiCad official)
Provenance

README

markdown

AT32F435CGT7

ARTERY · Microcontrollers (MCU/MPU/SOC) · LQFP-48(7x7)

AT32F435CGT7 from ARTERY, in a LQFP-48(7x7). Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin	Name	Type	Function
1	VBAT	power_in	Battery supply for the VBAT domain (ERTC, LEXT and BPR) when VDD is absent, with a range of 1.62-3.6 V.
2	PC13	bidirectional	FT GPIO (5 V tolerant) also carrying ERTC_AF1 and WKUP2 wake-up; it is powered through a power switch limited to 3 mA, so it cannot source current such as driving an LED.
3	PC14/LEXT_IN	bidirectional	TC GPIO (standard level, not 5 V tolerant) that doubles as the LEXT 32.768 kHz oscillator input; it is powered through a power switch limited to 3 mA.
4	PC15/LEXT_OUT	bidirectional	TC GPIO (standard level, not 5 V tolerant) that doubles as the LEXT 32.768 kHz oscillator output; it is powered through a power switch limited to 3 mA.
5	PH0/HEXT_IN	bidirectional	TC GPIO (standard level) that doubles as the HEXT 4-25 MHz crystal oscillator input, with I2C1_SDA as an alternate function.
6	PH1/HEXT_OUT	bidirectional	TC GPIO (standard level) that doubles as the HEXT 4-25 MHz crystal oscillator output, with I2C1_SCL as an alternate function.
7	NRST	bidirectional	Active-low device reset input and internal reset output with a built-in weak pull-up (30-50 kΩ), VIL max 0.8 V, and a recommended 0.1 µF protection network.
8	VSSA/VREF-	power_in	Analog ground and negative reference voltage for the ADC and DAC, which must be connected to VSS.
9	VDDA/VREF+	power_in	Analog supply for the ADC and DAC and positive reference voltage, which must be the same as VDD (2.6-3.6 V).
10	PA0	bidirectional	FTa GPIO (5 V tolerant as input, but must stay below VDD+0.3 V in analog mode) that serves as fast ADC channel ADC123_IN0, WKUP1 wake-up and TMR2_CH1/USART2_CTS.
11	PA1	bidirectional	FTa GPIO (5 V tolerant as input, but must stay below VDD+0.3 V in analog mode) that serves as fast ADC channel ADC123_IN1, with TMR2_CH2 and USART2_RTS_DE as alternate functions.
12	PA2	bidirectional	FTa GPIO (5 V tolerant as input, but must stay below VDD+0.3 V in analog mode) that serves as ADC123_IN2, with USART2_TX and TMR2_CH3 as alternate functions.
13	PA3	bidirectional	FTa GPIO (5 V tolerant as input, but must stay below VDD+0.3 V in analog mode) that serves as ADC123_IN3, with USART2_RX and I2S2_MCK as alternate functions.
14	PA4	bidirectional	FTa GPIO (5 V tolerant as input, but must stay below VDD+0.3 V in analog mode) that serves as ADC12_IN4 and DAC1_OUT, with SPI1_CS and USART2_CK as alternate functions.
15	PA5	bidirectional	FTa GPIO (5 V tolerant as input, but must stay below VDD+0.3 V in analog mode) that serves as ADC12_IN5 and DAC2_OUT, with SPI1_SCK and TMR2_CH1 as alternate functions.
16	PA6	bidirectional	FTa GPIO (5 V tolerant as input, but must stay below VDD+0.3 V in analog mode) that serves as ADC12_IN6, with SPI1_MISO and TMR3_CH1 as alternate functions.
17	PA7	bidirectional	FTa GPIO (5 V tolerant as input, but must stay below VDD+0.3 V in analog mode) that serves as ADC12_IN7, with SPI1_MOSI and TMR3_CH2 as alternate functions.
18	PB0	bidirectional	FTa GPIO (5 V tolerant as input, but must stay below VDD+0.3 V in analog mode) that serves as ADC12_IN8, with TMR1_CH2C and USART3_CK as alternate functions.
19	PB1	bidirectional	FTa GPIO (5 V tolerant as input, but must stay below VDD+0.3 V in analog mode) that serves as ADC12_IN9, with TMR1_CH3C and SPI2_SCK as alternate functions.
20	PB2/BOOT1	bidirectional	FT GPIO (5 V tolerant) that is also labelled BOOT1 in the start-up pin setting, with TMR2_CH4 and SPI3_MOSI as alternate functions.
21	PB10	bidirectional	FTf GPIO (5 V tolerant with 20 mA sink capability) with TMR2_CH3, I2C2_SCL and USART3_TX as alternate functions.
22	PB11	bidirectional	FT GPIO (5 V tolerant) with TMR2_CH4, I2C2_SDA, USART3_RX and EMAC_MII_TX_EN as alternate functions.
23	PH3	bidirectional	FT GPIO (5 V tolerant) with TMR5_CH2, I2C2_SDA and UART4_TX as alternate functions.
24	VDD	power_in	Digital supply (2.6-3.6 V) for the GPIO pins and the internal LDO.
25	PB12	bidirectional	FT GPIO (5 V tolerant) with TMR1_BRK, SPI2_CS, USART3_CK, CAN2_RX and OTGFS2_ID as alternate functions.
26	PB13	bidirectional	FT GPIO (5 V tolerant) with TMR1_CH1C, SPI2_SCK, USART3_CTS, CAN2_TX and OTGFS2_VBUS as alternate functions.
27	PB14	bidirectional	TC GPIO (standard level, not 5 V tolerant) with TMR1_CH2C, SPI2_MISO, USART3_RTS_DE and OTGFS2_D- as alternate functions.
28	PB15	bidirectional	TC GPIO (standard level, not 5 V tolerant) with ERTC_REFIN, TMR1_CH3C, SPI2_MOSI and OTGFS2_D+ as alternate functions.
29	PA8	bidirectional	FT GPIO (5 V tolerant) with CLKOUT1, TMR1_CH1, I2C3_SCL, USART1_CK, USART2_TX and OTGFS1_SOF as alternate functions.
30	PA9	bidirectional	FT GPIO (5 V tolerant) with TMR1_CH2, USART1_TX, I2C1_SCL and OTGFS1_VBUS as alternate functions.
31	PA10	bidirectional	FT GPIO (5 V tolerant) with TMR1_CH3, USART1_RX, I2C1_SDA and OTGFS1_ID as alternate functions.
32	PA11	bidirectional	TC GPIO (standard level, not 5 V tolerant) with TMR1_CH4, USART1_CTS, CAN1_RX and OTGFS1_D- as alternate functions.
33	PA12	bidirectional	TC GPIO (standard level, not 5 V tolerant) with TMR1_EXT, USART1_RTS_DE, CAN1_TX and OTGFS1_D+ as alternate functions.
34	PA13	bidirectional	FT GPIO (5 V tolerant) that is the JTMS/SWDIO debug pin, with IR_OUT and SPI3_MISO as alternate functions.
35	PH2	bidirectional	FT GPIO (5 V tolerant) with TMR5_CH1, I2C2_SCL, UART4_RX and QSPI1_IO0 as alternate functions.
36	VDD	power_in	Digital supply (2.6-3.6 V) for the GPIO pins and the internal LDO.
37	PA14	bidirectional	FT GPIO (5 V tolerant) that is the JTCK/SWCLK debug pin, with SPI3_MOSI, I2S3_SD and USART2_TX as alternate functions.
38	PA15	bidirectional	FT GPIO (5 V tolerant) that is the JTDI debug pin, with TMR2_CH1, SPI1_CS, USART1_TX and USART2_RX as alternate functions.
39	PB3	bidirectional	FTf GPIO (5 V tolerant with 20 mA sink capability) that is the JTDO/SWO debug pin, with TMR2_CH2, SPI1_SCK and USART1_RX as alternate functions.
40	PB4	bidirectional	FT GPIO (5 V tolerant) that is the NJTRST debug pin, with TMR3_CH1, SPI1_MISO and SPI3_MISO as alternate functions.
41	PB5	bidirectional	FT GPIO (5 V tolerant) with TMR3_CH2, I2C1_SMBA, SPI1_MOSI, USART1_CK and CAN2_RX as alternate functions.
42	PB6	bidirectional	FT GPIO (5 V tolerant) with TMR4_CH1, I2C1_SCL, USART1_TX, CAN2_TX and QSPI1_CS as alternate functions.
43	PB7	bidirectional	FT GPIO (5 V tolerant) with TMR4_CH2, TMR8_BRK, I2C1_SDA and USART1_RX as alternate functions.
44	BOOT0	input	Dedicated BOOT0 boot-mode input with a built-in weak pull-down that cannot be disabled.
45	PB8	bidirectional	FT GPIO (5 V tolerant) with TMR2_CH1, TMR4_CH3, I2C1_SCL, SPI4_MISO and CAN1_RX as alternate functions.
46	PB9	bidirectional	FTf GPIO (5 V tolerant with 20 mA sink capability) with IR_OUT, TMR2_CH2, I2C1_SDA, SPI2_CS and CAN1_TX as alternate functions.
47	VSS	power_in	Digital ground.
48	VDD	power_in	Digital supply (2.6-3.6 V) for the GPIO pins and the internal LDO.

Key specifications

Parameter	Value
Manufacturer	ARTERY
Package	LQFP-48(7x7)
Category	Embedded Processors & Controllers
Pins	48

Electrical characteristics

Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).

Parameter	Symbol	Min	Typ	Max	Unit	Conditions	Page
External main supply voltage (VDDx-VSS)	VDDx-VSS	-0.3		4	V		47
Input voltage on FTa pin, input floating/pull-up/pull-down mode	VIN			6	V	FTa pin, set to input floating, input pull-up or pull-down mode; printed minimum is VSS-0.3	47
Input voltage on TC pin	VIN			4	V	TC pin; printed minimum is VSS-0.3	47
Voltage difference between supply pins	/ΔVDDx/			50	mV		47
Voltage difference between ground pins	/VSSx-VSS/			50	mV		47
Total current into VDD (including VDDA and VDD)	IVDD			250	mA		47
Total current out of VSS ground line	IVSS			250	mA	outflow current	47
Output sink current, any GPIO and control pin	IIO			25	mA		47
Output current, any GPIO and control pin	IIO	-25			mA		47
Storage temperature range	TSTG	-60		150	°C		47
Maximum junction temperature	TJ			125	°C		47
Supply voltage (power supply range, feature list)	VDD	2.6		3.6	V		1
Operating temperature range		-40		105	°C		1
48 MHz HICK internal clock accuracy		-1		1	%	25 °C	1
48 MHz HICK internal clock accuracy over temperature		-2.5		2.5	%	-40 °C to +105 °C	1
Clock frequency in data transfer mode	fPP	0		48	MHz		94
Clock low time	tW(CKL)	32			ns		94
Clock high time	tW(CKH)	30			ns		94
Clock rise time	tr			4	ns		94
Clock fall time	tf			5	ns		94
Clock setup time, CMD and D inputs	tISU	2			ns	CMD、D输入（参照CK）	94
Clock hold time, CMD and D inputs	tIH	0			ns	CMD、D输入（参照CK）	94
Output valid time, MMC and SD high-speed mode	tOV			6	ns	在MMC和SD高速模式CMD、D输出（参照CK）	94
Output hold time, MMC and SD high-speed mode	tOH	0			ns	在MMC和SD高速模式CMD、D输出（参照CK）	94
Output valid default time, SD default mode	tOVD			7	ns	在SD默认模式CMD、D输出（参照CK）	94
Output hold default time, SD default mode	tOHD	0.5			ns	在SD默认模式CMD、D输出（参照CK）	94
OTGFS transceiver startup time	tSTARTUP			1	μs		95
OTGFS operating voltage	VDD	3		3.6	V		95
Differential input sensitivity, I(OTGFS_D+/D-)	VDI	0.2			V		95
Differential common-mode range	VCM	0.8		2.5	V	includes VDI range	95
Single-ended receiver threshold	VSE	1.3		2	V		95
Static output low level	VOL			0.3	V	1.24 kΩ的RL接至3.6 V	95
Static output high level	VOH	2.8		3.6	V	15 kΩ的RL接至VSS	95
OTGFS_D+ internal pull-up resistor	RPU	0.97	1.24	1.58	kΩ	VIN = VSS	95
OTGFS_D+/D- internal pull-down resistor	RPD	15	19	25	kΩ	VIN = VDD	95
Rise time	tr	4		20	ns	CL ≤ 50 pF	95
Fall time	tf	4		20	ns	CL ≤ 50 pF	95
Rise/fall time matching (tr/tf)	trfm	90		110	%		95
Output signal crossover voltage	VCRS	1.3		2	V		95

CAD (KiCad official)

Symbol: AT32F435CGT7
Footprint: Package_QFP:LQFP-48_7x7mm_P0.5mm
3D model: LQFP-48(7x7) (KiCad packages3D, STEP)
3D model files: at32f435cgt7-etched.step / at32f435cgt7-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); at32f435cgt7.step / at32f435cgt7.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

Datasheet: ARTERY datasheet (118 pp, sha256 1dc0c659f12e7670, retrieved 2026-10-19, tier: lcsc)
Datasheet language: Chinese. Pin names, descriptions, and specs on this page were extracted and translated to English by ds2sf; the linked PDF is the manufacturer original.
Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-haiku-5-5 (text), consensus claude-sonnet-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF