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AT32F425C8T7

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ARTERY Microcontrollers (MCU/MPU/SOC), LQFP-48(7x7). Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.

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AT32F425C8T7

ARTERY · Microcontrollers (MCU/MPU/SOC) · LQFP-48(7x7)

AT32F425C8T7 from ARTERY, in a LQFP-48(7x7). Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 VDD power_in Digital supply, 2.4 V to 3.6 V, which powers the GPIO pins, ERTC, LEXT, BPR and the internal LDO.
2 PC13 bidirectional 5 V tolerant (FT) general-purpose I/O with alternate functions ERTC_OUT, TAMP1 and WKUP2.
3 PC14 bidirectional Standard-level (TC) general-purpose I/O, not 5 V tolerant, that doubles as the LEXT_IN low-speed crystal input.
4 PC15 bidirectional Standard-level (TC) general-purpose I/O, not 5 V tolerant, that doubles as the LEXT_OUT low-speed crystal output.
5 PF0 bidirectional Standard-level (TC) general-purpose I/O, not 5 V tolerant, with alternate function TMR1_CH1 and additional function HEXT_IN (high-speed crystal input).
6 PF1 bidirectional Standard-level (TC) general-purpose I/O, not 5 V tolerant, with alternate functions TMR1_CH2C, SPI2_CS and I2S2_WS and additional function HEXT_OUT.
7 NRST bidirectional Bidirectional active-low reset pin (device reset input and internal reset output) with a built-in weak pull-up of 30 to 50 kΩ that cannot be disconnected.
8 VSSA power_in Analog ground for the ADC, which must be at the same potential as VSS.
9 VDDA power_in Analog supply for the ADC, 2.4 V to 3.6 V, which must be at the same potential as VDD.
10 PA0 bidirectional 5 V tolerant with analog function (FTa) general-purpose I/O with ADC1_IN0, WKUP1 and USART2/TMR2 alternate functions; in analog mode the input must stay below VDD + 0.3 V.
11 PA1 bidirectional 5 V tolerant with analog function (FTa) general-purpose I/O with ADC1_IN1 and USART2_RTS_DE, TMR2_CH2 and I2C2 alternate functions; in analog mode the input must stay below VDD + 0.3 V.
12 PA2 bidirectional 5 V tolerant with analog function (FTa) general-purpose I/O with ADC1_IN2, WKUP4, TMR15_CH1, USART2_TX and CAN1_RX alternate functions; in analog mode the input must stay below VDD + 0.3 V.
13 PA3 bidirectional 5 V tolerant with analog function (FTa) general-purpose I/O with ADC1_IN3, TMR15_CH2, USART2_RX, CAN1_TX and I2S2_MCK alternate functions; in analog mode the input must stay below VDD + 0.3 V.
14 PA4 bidirectional 5 V tolerant with analog function (FTa) general-purpose I/O with ADC1_IN4 and SPI1_CS, I2S1_WS, USART2_CK and SPI2/SPI3 alternate functions; in analog mode the input must stay below VDD + 0.3 V.
15 PA5 bidirectional 5 V tolerant with analog function (FTa) general-purpose I/O with ADC1_IN5 and SPI1_SCK, I2S1_CK, TMR2_CH1 and USART3 alternate functions; in analog mode the input must stay below VDD + 0.3 V.
16 PA6 bidirectional 5 V tolerant with analog function (FTa) general-purpose I/O with ADC1_IN6 and SPI1_MISO, I2S1_MCK, TMR3_CH1, TMR1_BRK and TMR16_CH1 alternate functions; in analog mode the input must stay below VDD + 0.3 V.
17 PA7 bidirectional 5 V tolerant with analog function (FTa) general-purpose I/O with ADC1_IN7 and SPI1_MOSI, I2S1_SD, TMR3_CH2, TMR1_CH1C and USART3_TX alternate functions; in analog mode the input must stay below VDD + 0.3 V.
18 PB0 bidirectional 5 V tolerant with analog function (FTa) general-purpose I/O with ADC1_IN8 and TMR3_CH3, TMR1_CH2C, USART2_RX, USART3_CK and SPI1_MISO alternate functions; in analog mode the input must stay below VDD + 0.3 V.
19 PB1 bidirectional 5 V tolerant with analog function (FTa) general-purpose I/O with ADC1_IN9 and TMR14_CH1, TMR3_CH4, TMR1_CH3C, USART3_RTS_DE and SPI1_MOSI alternate functions; in analog mode the input must stay below VDD + 0.3 V.
20 PB2 bidirectional 5 V tolerant with analog function (FTa) general-purpose I/O with alternate functions TMR3_EXT, SPI3_MOSI, I2S3_SD and I2C1_SMBA; in analog mode the input must stay below VDD + 0.3 V.
21 PB10 bidirectional 5 V tolerant (FT) general-purpose I/O with alternate functions I2C2_SCL, TMR2_CH3, USART3_TX, SPI2_SCK and I2S2_CK.
22 PB11 bidirectional 5 V tolerant (FT) general-purpose I/O with alternate functions EVENTOUT, I2C2_SDA, TMR2_CH4 and USART3_RX.
23 VSS power_in Digital ground.
24 VDD power_in Digital supply, 2.4 V to 3.6 V.
25 PB12 bidirectional 5 V tolerant (FT) general-purpose I/O with alternate functions SPI2_CS, I2S2_WS, EVENTOUT, TMR1_BRK, USART3_CK, TMR15_BRK, SPI3_CS, I2S3_WS and I2C2_SMBA.
26 PB13 bidirectional 5 V tolerant with 20 mA sink capability (FTf) general-purpose I/O with alternate functions SPI2_SCK, I2S2_CK, TMR15_CH1C, TMR1_CH1C, CLKOUT, USART3_CTS, I2C2_SCL, SPI3_SCK and I2S3_CK.
27 PB14 bidirectional 5 V tolerant with 20 mA sink capability (FTf) general-purpose I/O with alternate functions SPI2_MISO, I2S2_MCK, TMR15_CH1, TMR1_CH2C, USART3_RTS_DE, I2C2_SDA, SPI3_MISO and I2S3_MCK.
28 PB15 bidirectional 5 V tolerant (FT) general-purpose I/O with alternate functions SPI2_MOSI, I2S2_SD, TMR15_CH2, TMR1_CH3C, ERTC_REFIN, SPI3_MOSI and I2S3_SD, and wake-up function WKUP7.
29 PA8 bidirectional 5 V tolerant (FT) general-purpose I/O with alternate functions CLKOUT, USART1_CK, TMR1_CH1, OTGFS1_SOF, USART2_TX, EVENTOUT and I2C2_SCL.
30 PA9 bidirectional 5 V tolerant (FT) general-purpose I/O with alternate functions TMR15_BRK, USART1_TX, TMR1_CH2, OTGFS1_VBUS, I2C1_SCL, CLKOUT, SPI3_SCK and I2S3_CK.
31 PA10 bidirectional 5 V tolerant (FT) general-purpose I/O with alternate functions TMR17_BRK, USART1_RX, TMR1_CH3, OTGFS1_ID, I2C1_SDA, ERTC_REFIN, SPI3_MOSI and I2S3_SD.
32 PA11 bidirectional Standard-level (TC) general-purpose I/O, not 5 V tolerant, with alternate functions EVENTOUT, USART1_CTS, TMR1_CH4, SPI3_CS, CAN1_RX and I2C2_SCL, and OTGFS1_D- when OTGFS1 is enabled.
33 PA12 bidirectional Standard-level (TC) general-purpose I/O, not 5 V tolerant, with alternate functions EVENTOUT, USART1_RTS_DE, TMR1_EXT, CAN1_TX, I2C2_SDA, SPI3_MISO and I2S3_MCK, and OTGFS1_D+ when OTGFS1 is enabled.
34 PA13 bidirectional 5 V tolerant (FT) general-purpose I/O that is configured as the SWDIO debug pin after reset with its internal pull-up enabled; alternate functions include IR_OUT, OTGFS1_OE, SPI3_MISO and I2C1_SDA.
35 PF6 bidirectional 5 V tolerant (FT) general-purpose I/O with alternate functions I2C2_SCL and USART4_RX.
36 PF7 bidirectional 5 V tolerant (FT) general-purpose I/O with alternate functions I2C2_SDA and USART4_TX.
37 PA14 bidirectional 5 V tolerant (FT) general-purpose I/O that is configured as the SWCLK debug pin after reset with its internal pull-down enabled; alternate functions include USART2_TX, SPI3_MOSI, I2S3_SD and SPI2_MOSI.
38 PA15 bidirectional 5 V tolerant (FT) general-purpose I/O with alternate functions SPI1_CS, I2S1_WS, USART2_RX, TMR2_CH1, EVENTOUT, USART4_RTS_DE, OTGFS1_OE, SPI2_CS and SPI3_CS.
39 PB3 bidirectional 5 V tolerant (FT) general-purpose I/O with alternate functions SPI1_SCK, I2S1_CK, EVENTOUT, TMR2_CH2, USART1_RTS_DE, USART2_CTS, SPI2_SCK and SWO.
40 PB4 bidirectional 5 V tolerant (FT) general-purpose I/O with alternate functions SPI1_MISO, I2S1_MCK, TMR3_CH1, EVENTOUT, USART1_CTS, TMR17_BRK, SPI2_MISO and I2C1_SDA.
41 PB5 bidirectional 5 V tolerant (FT) general-purpose I/O with wake-up function WKUP6 and alternate functions SPI1_MOSI, I2S1_SD, TMR3_CH2, TMR16_BRK, I2C1_SMBA, USART1_CK and USART2_RTS_DE.
42 PB6 bidirectional 5 V tolerant (FT) general-purpose I/O with alternate functions USART1_TX, I2C1_SCL, TMR16_CH1C, USART4_CK, I2S1_MCK, SPI3_CS and I2S3_WS.
43 PB7 bidirectional 5 V tolerant (FT) general-purpose I/O with alternate functions USART1_RX, I2C1_SDA, TMR17_CH1C, USART4_CTS, SPI3_SCK and I2S3_CK.
44 BOOT0 input Dedicated boot mode selection pin 0 with a built-in weak pull-down that cannot be disabled.
45 PB8 bidirectional 5 V tolerant with 20 mA sink capability (FTf) general-purpose I/O with alternate functions USART1_TX, I2C1_SCL, TMR16_CH1, EVENTOUT, CAN1_RX, SPI3_MISO and I2S3_MCK.
46 PB9 bidirectional 5 V tolerant with 20 mA sink capability (FTf) general-purpose I/O with alternate functions IR_OUT, I2C1_SDA, TMR17_CH1, EVENTOUT, CAN1_TX, SPI2_CS, I2S2_WS, I2S1_MCK, SPI3_MOSI and I2S3_SD.
47 VSS power_in Digital ground.
48 VDD power_in Digital supply, 2.4 V to 3.6 V.

Key specifications

Parameter Value
Manufacturer ARTERY
Package LQFP-48(7x7)
Category Embedded Processors & Controllers
Pins 48

Electrical characteristics

Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).

Parameter Symbol Min Typ Max Unit Conditions Page
External main supply voltage (VDDx to VSS) VDDx-VSS -0.3 4 V 33
Voltage difference between supply pins /ΔVDDx/ 50 mV 33
Voltage difference between ground pins /VSSx-VSS/ 50 mV 33
Total current through VDDA and VDD supply pins IVDD 150 mA 33
Total current through VSS ground pins (outflow) IVSS 150 mA 33
Output sink current on any GPIO and control pin IIO 25 mA 33
Output source current on any GPIO and control pin IIO -25 mA 33
Storage temperature range TSTG -60 150 °C 33
Maximum junction temperature TJ 125 °C 33
OTGFS transceiver startup time tSTARTUP 1 μs 57
OTGFS operating voltage VDD 3 3.6 V 57
Differential input sensitivity I(OTGFS_D+/D-) VDI 0.2 V 57
Differential common-mode range VCM 0.8 2.5 V 包含VDI范围 57
Single-ended receiver threshold VSE 1.3 2 V 57
Static output low level VOL 0.3 V 1.24 kΩ的RL接至3.6 V 57
Static output high level VOH 2.8 3.6 V 15 kΩ的RL接至VSS 57
OTGFS_D+ internal pull-up resistor RPU 0.97 1.24 1.58 kΩ VIN = VSS 57
OTGFS_D+/D- internal pull-down resistor RPD 15 19 25 kΩ VIN = VDD 57
Rise time (data lines) tr 4 20 ns CL ≤ 50 pF 57
Fall time (data lines) tf 4 20 ns CL ≤ 50 pF 57
Rise/fall time matching tr/tf trfm 90 110 % 57
Output signal crossover voltage VCRS 1.3 2 V 57
ADC supply voltage VDDA 2.4 3.6 V 58
Current on VDDA input pin IDDA 295 355 μA 58
ADC clock frequency fADC 0.6 28 MHz 58
ADC sampling rate fS 0.05 2 MHz 58
External trigger frequency fTRIG 1.65 MHz fADC = 28 MHz 58
External trigger frequency fTRIG 17 1/fADC 58
ADC conversion voltage range VAIN 0 V 58
Internal sample and hold capacitance CADC 8.5 13 pF 58
Trigger conversion latency tlatr 71.4 μs fADC = 28 MHz 58
Trigger conversion latency tlatr 2 1/fADC 58
Sampling time tS 0.053 8.55 μs fADC = 28 MHz 58
Sampling time tS 1.5 239.5 1/fADC 58
Total conversion time (including sampling time) tCONV 0.5 9 μs fADC = 28 MHz 58
Total conversion time (including sampling time) tCONV 14 252 1/fADC 58
Maximum external input impedance for error below 1 LSB RAIN 0.35 kΩ fADC = 14 MHz, TS = 1.5 cycles, tS = 0.11 μs 58
Maximum external input impedance for error below 1 LSB RAIN 3.9 kΩ fADC = 14 MHz, TS = 7.5 cycles, tS = 0.54 μs 58
Maximum external input impedance for error below 1 LSB RAIN 7.4 kΩ fADC = 14 MHz, TS = 13.5 cycles, tS = 0.96 μs 58
Maximum external input impedance for error below 1 LSB RAIN 16.3 kΩ fADC = 14 MHz, TS = 28.5 cycles, tS = 2.04 μs 58
Maximum external input impedance for error below 1 LSB RAIN 24 kΩ fADC = 14 MHz, TS = 41.5 cycles, tS = 2.96 μs 58
Maximum external input impedance for error below 1 LSB RAIN 32.3 kΩ fADC = 14 MHz, TS = 55.5 cycles, tS = 3.96 μs 58
Maximum external input impedance for error below 1 LSB RAIN 41.8 kΩ fADC = 14 MHz, TS = 71.5 cycles, tS = 5.11 μs 58
Maximum external input impedance for error below 1 LSB RAIN 50 kΩ fADC = 14 MHz, TS = 239.5 cycles, tS = 17.11 μs 58

CAD (KiCad official)

  • Symbol: AT32F425C8T7
  • Footprint: Package_QFP:LQFP-48_7x7mm_P0.5mm
  • 3D model: LQFP-48(7x7) (KiCad packages3D, STEP)
  • 3D model files: at32f425c8t7-etched.step / at32f425c8t7-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); at32f425c8t7.step / at32f425c8t7.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: ARTERY datasheet (79 pp, sha256 d7b9e2a417131ac3, retrieved 2026-10-18, tier: lcsc)
  • Datasheet language: Chinese. Pin names, descriptions, and specs on this page were extracted and translated to English by ds2sf; the linked PDF is the manufacturer original.
  • Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-haiku-5-5 (text), consensus claude-sonnet-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF