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AT32F423KCU7-4

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ARTERY(雅特力) Microcontrollers (MCU/MPU/SOC), QFN-32-EP(4x4). Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.

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AT32F423KCU7-4

ARTERY(雅特力) · Microcontrollers (MCU/MPU/SOC) · QFN-32-EP(4x4)

AT32F423KCU7-4 from ARTERY(雅特力), in a QFN-32-EP(4x4). Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 VDD power_in Digital power supply for GPIO, ERTC, LEXT, BPR and the LDO, operating from 2.4 V to 3.6 V.
2 PF0 bidirectional Standard-level (TC) GPIO that doubles as the HEXT crystal input (HEXT_IN, 4-25 MHz) with TMR1_CH1 and I2C1_SDA alternate functions.
3 PF1 bidirectional Standard-level (TC) GPIO that doubles as the HEXT crystal output (HEXT_OUT) with TMR1_CH2C, I2C1_SCL, SPI2_CS and I2S2_WS alternate functions.
4 NRST bidirectional Active-low device reset input and internal reset output with an internal weak pull-up of 30-50 kΩ, and it must be pulled below VIL(NRST) max of 0.8 V to reset the MCU.
5 VDDA power_in Analog power supply for the ADC and DAC, which must be at the same potential as VDD.
6 PA0 bidirectional FTa GPIO (5 V tolerant only in input float/pull modes, not in analog mode where input must stay below VDD+0.3 V) with ADC1_IN0, WKUP1 and TAMP2 functions.
7 PA1 bidirectional FTa GPIO (5 V tolerant only in input modes; analog mode input must stay below VDD+0.3 V) with ADC1_IN1 and TMR2_CH2 / I2C2_SDA alternate functions.
8 PA2 bidirectional FTa GPIO (5 V tolerant only in input modes; analog mode input must stay below VDD+0.3 V) with ADC1_IN2 and USART2_TX / CAN2_RX alternate functions.
9 PA3 bidirectional FTa GPIO (5 V tolerant only in input modes; analog mode input must stay below VDD+0.3 V) with ADC1_IN3 and USART2_RX / CAN2_TX alternate functions.
10 PA4 bidirectional FTa GPIO (5 V tolerant only in input modes; analog mode input must stay below VDD+0.3 V) with ADC1_IN4 / DAC1_OUT and SPI1_CS / OTGFS1_OE alternate functions.
11 PA5 bidirectional FTa GPIO (5 V tolerant only in input modes; analog mode input must stay below VDD+0.3 V) with ADC1_IN5 / DAC2_OUT and SPI1_SCK alternate functions.
12 PA6 bidirectional FTa GPIO (5 V tolerant only in input modes; analog mode input must stay below VDD+0.3 V) with ADC1_IN6 and SPI1_MISO / TMR3_CH1 alternate functions.
13 PA7 bidirectional FTa GPIO (5 V tolerant only in input modes; analog mode input must stay below VDD+0.3 V) with ADC1_IN7 and SPI1_MOSI / TMR3_CH2 alternate functions.
14 PB0 bidirectional FTa GPIO (5 V tolerant only in input modes; analog mode input must stay below VDD+0.3 V) with ADC1_IN8 and SPI1_MISO / TMR1_CH2C alternate functions.
15 PB1 bidirectional FTa GPIO (5 V tolerant only in input modes; analog mode input must stay below VDD+0.3 V) with ADC1_IN9 and SPI1_MOSI / TMR1_CH3C alternate functions.
16 PB2 bidirectional FTa GPIO (5 V tolerant only in input modes; analog mode input must stay below VDD+0.3 V) with ADC1_IN20 and TMR2_CH4 / I2C3_SMBA alternate functions.
17 VDD power_in Digital power supply, operating from 2.4 V to 3.6 V.
18 PA8 bidirectional 5 V tolerant FT GPIO with CLKOUT, TMR1_CH1, I2C3_SCL, USART1_CK and OTGFS1_SOF alternate functions.
19 PA9 bidirectional 5 V tolerant FT GPIO with CLKOUT, TMR1_CH2, USART1_TX, I2C1_SCL and OTGFS1_VBUS alternate functions.
20 PA10 bidirectional 5 V tolerant FT GPIO with ERTC_REFIN, TMR1_CH3, USART1_RX, I2C1_SDA and OTGFS1_ID alternate functions.
21 PA11 bidirectional Standard-level (TC) GPIO with OTGFS1_D- as a dedicated USB function plus USART1_CTS, CAN1_RX and TMR1_CH4 alternate functions.
22 PA12 bidirectional Standard-level (TC) GPIO with OTGFS1_D+ as a dedicated USB function plus USART1_RTS_DE, CAN1_TX and TMR1_EXT alternate functions.
23 PA13 bidirectional 5 V tolerant FT GPIO that is the JTMS/SWDIO serial-wire debug data pin by default, with IR_OUT and OTGFS1_OE alternate functions.
24 PA14 bidirectional 5 V tolerant FT GPIO that is the JTCK/SWCLK serial-wire debug clock pin by default, with USART2_TX, SPI3_MOSI and I2C1_SMBA alternate functions.
25 PA15 bidirectional 5 V tolerant FT GPIO that is the JTDI debug input pin by default, with TMR2_CH1, SPI1_CS, USART1_TX and XMC_NE2 alternate functions.
26 PB3 bidirectional 5 V tolerant FT GPIO that is the JTDO/SWO trace output pin by default, with TMR2_CH2, SPI1_SCK and USART1_RX alternate functions.
27 PB4 bidirectional 5 V tolerant FT GPIO that is the NJTRST debug reset pin by default, with TMR3_CH1, SPI1_MISO and USART1_CTS alternate functions.
28 PB5 bidirectional 5 V tolerant FT GPIO with WKUP6 wake-up function plus TMR3_CH2, SPI1_MOSI, USART1_CK and CAN2_RX alternate functions.
29 PB6 bidirectional 5 V tolerant FT GPIO with TMR4_CH1, I2C1_SCL, USART1_TX and CAN2_TX alternate functions.
30 PB7 bidirectional 5 V tolerant FT GPIO with TMR4_CH2, I2C1_SDA, USART1_RX and XMC_NADV alternate functions.
31 BOOT0 input Dedicated boot mode selection pin 0 with a built-in weak pull-down that cannot be disabled, used together with the user system data nBOOT1 bit to select the boot source.
32 PB8 bidirectional 5 V tolerant FT GPIO with TMR2_CH1, TMR4_CH3, I2C1_SCL, USART1_TX and CAN1_RX alternate functions.
33 EPAD power_in Exposed pad that serves as the digital ground (VSS) and analog ground (VSSA), which must be at the same potential as VSS.

Key specifications

Parameter Value
Manufacturer ARTERY(雅特力)
Package QFN-32-EP(4x4)
Category Embedded Processors & Controllers
Pins 33

Electrical characteristics

Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).

Parameter Symbol Min Typ Max Unit Conditions Page
Power supply voltage (feature summary, power control) 2.4 3.6 V 1
Operating temperature range (feature summary) -40 105 °C 1
CPU maximum operating frequency (feature summary) 150 MHz 1
48 MHz HICK frequency accuracy -1 1 % 25 °C 1
48 MHz HICK frequency accuracy -2.5 2.5 % -40 °C to +105 °C 1
External supply voltage VDDx-VSS -0.3 4 V 35
Input voltage on FTa pin (input floating, pull-up or pull-down mode) VIN 6 V FTa pin set to input floating, input pull-up or input pull-down 35
Input voltage on TC pin VIN 4 V 35
Voltage difference between supply pins /ΔVDDx/ 50 mV 35
Voltage difference between ground pins /VSSx-VSS/ 50 mV 35
Total current through VDD supply line (inflow) IVDD 150 mA 35
Total current through VSS ground line (outflow) IVSS 150 mA 35
Output sink current on any GPIO and control pin IIO 25 mA 35
Output current on any GPIO and control pin (source) IIO -25 mA 35
Storage temperature range TSTG -60 150 °C 35
Maximum junction temperature TJ 125 °C 35
OTGFS transceiver startup time tSTARTUP 1 μs 65
OTGFS operating voltage VDD 3 3.6 V 65
Differential input sensitivity VDI 0.2 V I(OTGFS_D+/D-) 65
Differential common-mode range VCM 0.8 2.5 V includes VDI range 65
Single-ended receiver threshold VSE 1.3 2 V 65
Static output low level VOL 0.3 V RL = 1.24 kΩ to 3.6 V 65
Static output high level VOH 2.8 3.6 V RL = 15 kΩ to VSS 65
OTGFS_D+ internal pull-up resistor RPU 0.97 1.24 1.58 kΩ VIN = VSS 65
OTGFS_D+/D- internal pull-down resistor RPD 15 19 25 kΩ VIN = VDD 65
Rise time tr 4 20 ns CL ≤ 50 pF 65
Fall time tf 4 20 ns CL ≤ 50 pF 65
Rise/fall time matching trfm 90 110 % tr/tf 65
Output signal crossover voltage VCRS 1.3 2 V 65
ADC supply voltage VDDA 2.4 3.6 V 66
ADC positive reference voltage VREF+ 2 V 66
Current on VDDA input pin IDDA 1000 1250 μA fADC = 80 MHz 66
Current on VREF+ input pin IVREF+ 470 510 μA fADC = 80 MHz 66
ADC clock frequency fADC 0.6 80 MHz VREF+ ≥ 3.0 V 66
ADC clock frequency fADC 0.6 30 MHz VREF+ < 3.0 V 66
Sampling rate, 12-bit, fast channel fS 0.04 5.33 MSPS 12-bit resolution, fast channel 66
Sampling rate, 10-bit, fast channel fS 0.047 6.15 MSPS 10-bit resolution, fast channel 66
Sampling rate, 8-bit, fast channel fS 0.055 7.27 MSPS 8-bit resolution, fast channel 66
Sampling rate, 6-bit, fast channel fS 0.067 8.88 MSPS 6-bit resolution, fast channel 66
External trigger frequency fTRIG 4.44 MHz fADC = 80 MHz 66
External trigger frequency fTRIG 18 1/fADC 66
Preemption trigger conversion latency tlat 37.5 ns fADC = 80 MHz 66
Preemption trigger conversion latency tlat 3 1/fADC 66
Regular trigger conversion latency tlatr 25 ns fADC = 80 MHz 66
Regular trigger conversion latency tlatr 2 1/fADC 66
Sampling time tS 0.031 8.006 μs fADC = 80 MHz 66
Sampling time tS 2.5 640.5 1/fADC 66
Total conversion time including sampling tCONV 0.188 8.163 μs fADC = 80 MHz, 12-bit resolution 66
Total conversion time including sampling tCONV 15 653 1/fADC 12-bit resolution 66
Conversion voltage range lower limit VAIN 0 V VREF- internally connected to ground 66

CAD (KiCad official)

  • Symbol: AT32F423KCU7-4
  • Footprint: Package_DFN_QFN:QFN-32-1EP_4x4mm_P0.4mm_EP2.9x2.9mm
  • 3D model: QFN-32-EP(4x4) (KiCad packages3D, STEP)
  • 3D model files: at32f423kcu7-4-etched.step / at32f423kcu7-4-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); at32f423kcu7-4.step / at32f423kcu7-4.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: ARTERY(雅特力) datasheet (89 pp, sha256 6ea9ef1acb32858f, retrieved 2026-10-18, tier: lcsc)
  • Datasheet language: Chinese. Pin names, descriptions, and specs on this page were extracted and translated to English by ds2sf; the linked PDF is the manufacturer original.
  • Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-haiku-5-5 (text), consensus claude-sonnet-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF