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AT32F423CCT7

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ARTERY(雅特力) Microcontrollers (MCU/MPU/SOC), LQFP-48(7x7). Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.

componentembedded processors & controllersat32f423cct7factory-2.0.0extractor-text
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AT32F423CCT7

ARTERY(雅特力) · Microcontrollers (MCU/MPU/SOC) · LQFP-48(7x7)

AT32F423CCT7 from ARTERY(雅特力), in a LQFP-48(7x7). Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 VDD power_in Digital supply pin, operating at 2.4 V to 3.6 V (VDD) and powering GPIO, ERTC, LEXT, BPR and the LDO.
2 PC13 bidirectional GPIO (FT, 5 V tolerant) with ERTC_OUT, TAMP1 and WKUP2 functions, powered through a power switch limited to 3 mA and subject to errata restrictions.
3 PC14 bidirectional GPIO (TC, standard level, not 5 V tolerant) that is also the LEXT_IN low-speed oscillator input, powered through a 3 mA limited power switch.
4 PC15 bidirectional GPIO (TC, standard level, not 5 V tolerant) that is also the LEXT_OUT low-speed oscillator output, powered through a 3 mA limited power switch.
5 PF0 bidirectional GPIO (TC) with TMR1_CH1, I2C1_SDA and the HEXT_IN high-speed crystal input function.
6 PF1 bidirectional GPIO (TC) with TMR1_CH2C, I2C1_SCL, SPI2_CS, I2S2_WS and the HEXT_OUT high-speed crystal output function.
7 NRST bidirectional Active-low device reset I/O with an internal pull-up (RPU 30-50 kΩ), acting as reset input and internal reset output.
8 VSSA power_in Analog ground for the ADC and DAC, which must be at the same potential as VSS.
9 VDDA power_in Analog supply for the ADC and DAC, which must be at the same potential as VDD (2.4 V to 3.6 V).
10 PA0 bidirectional GPIO (FTa, 5 V tolerant when configured as input, not in analog mode) with TMR2_CH1, USART2_RX, ADC1_IN0 (fast channel), TAMP2 and WKUP1.
11 PA1 bidirectional GPIO (FTa, 5 V tolerant when configured as input, not in analog mode) with TMR2_CH2, I2C2_SDA, SPI3_CS, ADC1_IN1 (fast channel) and USART2_RTS_DE.
12 PA2 bidirectional GPIO (FTa, 5 V tolerant when configured as input) with TMR2_CH3, USART2_TX, CAN2_RX, XMC_D4 and ADC1_IN2.
13 PA3 bidirectional GPIO (FTa, 5 V tolerant when configured as input) with TMR2_CH4, I2S2_MCK, USART2_RX, CAN2_TX, XMC_D5 and ADC1_IN3.
14 PA4 bidirectional GPIO (FTa, 5 V tolerant when configured as input) with SPI1_CS, I2S1_WS, USART2_CK, OTGFS1_OE, XMC_D6, and ADC1_IN4 / DAC1_OUT.
15 PA5 bidirectional GPIO (FTa, 5 V tolerant when configured as input) with SPI1_SCK, I2S1_CK, USART3_CK, XMC_D7, and ADC1_IN5 / DAC2_OUT.
16 PA6 bidirectional GPIO (FTa, 5 V tolerant when configured as input) with TMR1_BRK, TMR3_CH1, SPI1_MISO, I2S1_MCK, and ADC1_IN6.
17 PA7 bidirectional GPIO (FTa, 5 V tolerant when configured as input) with TMR1_CH1C, TMR3_CH2, SPI1_MOSI, I2S1_SD, and ADC1_IN7.
18 PB0 bidirectional GPIO (FTa, 5 V tolerant when configured as input) with TMR1_CH2C, TMR3_CH3, SPI1_MISO, USART2_RX, and ADC1_IN8.
19 PB1 bidirectional GPIO (FTa, 5 V tolerant when configured as input) with TMR1_CH3C, TMR3_CH4, SPI1_MOSI, USART2_CK, TMR14_CH1, and ADC1_IN9.
20 PB2 bidirectional GPIO (FTa, 5 V tolerant when configured as input) with TMR2_CH4, TMR3_EXT, I2C3_SMBA, SPI3_MOSI, and ADC1_IN20.
21 PB10 bidirectional GPIO (FTa, 5 V tolerant when configured as input) with TMR2_CH3, I2C2_SCL, SPI2_SCK, USART3_TX, XMC_NOE, and ADC1_IN21.
22 PB11 bidirectional GPIO (FTa, 5 V tolerant when configured as input) with TMR2_CH4, I2C2_SDA, USART3_RX, TMR13_BRK, and ADC1_IN22.
23 PF8 bidirectional GPIO (FT, 5 V tolerant) with TMR2_CH2, I2C2_SDA and USART7_TX.
24 VDD power_in Digital supply pin, operating at 2.4 V to 3.6 V.
25 PB12 bidirectional GPIO (FTa, 5 V tolerant when configured as input) with TMR1_BRK, TMR12_BRK, SPI2_CS, I2S2_WS, CAN2_RX, XMC_D13, and ADC1_IN23.
26 PB13 bidirectional GPIO (FTa, 5 V tolerant when configured as input) with CLKOUT, TMR1_CH1C, SPI2_SCK, I2C3_SCL, USART3_CTS, CAN2_TX, and ADC1_IN24.
27 PB14 bidirectional GPIO (FTa, 5 V tolerant when configured as input) with TMR1_CH2C, I2C3_SDA, SPI2_MISO, I2S2_MCK, USART3_RTS_DE, XMC_D0, and ADC1_IN25.
28 PB15 bidirectional GPIO (FTa, 5 V tolerant when configured as input) with ERTC_REFIN, TMR1_CH3C, TMR12_CH1C, SPI2_MOSI, TMR12_CH2, WKUP7, and ADC1_IN26.
29 PA8 bidirectional GPIO (FT, 5 V tolerant) with CLKOUT, TMR1_CH1, TMR9_BRK, I2C3_SCL, USART1_CK, USART2_TX, and OTGFS1_SOF.
30 PA9 bidirectional GPIO (FT, 5 V tolerant) with CLKOUT, TMR1_CH2, I2C3_SMBA, SPI2_SCK, USART1_TX, I2C1_SCL, TMR14_BRK, and OTGFS1_VBUS.
31 PA10 bidirectional GPIO (FT, 5 V tolerant) with ERTC_REFIN, TMR1_CH3, SPI2_MOSI, I2S2_SD, USART1_RX, I2C1_SDA, and OTGFS1_ID.
32 PA11 bidirectional GPIO (TC, standard level, not 5 V tolerant) with TMR1_CH4, I2C2_SCL, SPI2_CS, USART1_CTS, USART6_TX, CAN1_RX, and the OTGFS1_D- USB function.
33 PA12 bidirectional GPIO (TC, standard level, not 5 V tolerant) with TMR1_EXT, I2C2_SDA, SPI2_MISO, USART1_RTS_DE, USART6_RX, CAN1_TX, and the OTGFS1_D+ USB function.
34 PA13 bidirectional GPIO (FT, 5 V tolerant) multiplexed with the JTMS/SWDIO debug function, plus IR_OUT, I2C1_SDA, SPI3_MISO and OTGFS1_OE.
35 PF6 bidirectional GPIO (FT, 5 V tolerant) with TMR2_CH1, I2C2_SCL and USART7_RX.
36 VDD power_in Digital supply pin, operating at 2.4 V to 3.6 V.
37 PA14 bidirectional GPIO (FT, 5 V tolerant) multiplexed with the JTCK/SWCLK debug function, plus I2C1_SMBA, SPI3_MOSI, I2S3_SD and USART2_TX.
38 PA15 bidirectional GPIO (FT, 5 V tolerant) multiplexed with the JTDI debug function, plus TMR2_CH1, SPI1_CS, I2S1_WS, USART1_TX, USART2_RX and XMC_NE2.
39 PB3 bidirectional GPIO (FT, 5 V tolerant) multiplexed with the JTDO function and SWO trace output, plus TMR2_CH2, I2C2_SDA, SPI1_SCK, USART1_RX and USART5_TX.
40 PB4 bidirectional GPIO (FT, 5 V tolerant) multiplexed with the NJTRST debug function, plus TMR3_CH1, TMR11_BRK, I2C3_SDA, SPI1_MISO, USART1_CTS and USART5_RX.
41 PB5 bidirectional GPIO (FT, 5 V tolerant) with TMR3_CH2, TMR10_BRK, I2C3_SMBA, SPI1_MOSI, USART1_CK, CAN2_RX, and the WKUP6 wake-up function.
42 PB6 bidirectional GPIO (FT, 5 V tolerant) with TMR4_CH1, TMR10_CH1C, I2C1_SCL, I2S1_MCK, USART1_TX, USART5_TX, CAN2_TX and USART4_CK.
43 PB7 bidirectional GPIO (FT, 5 V tolerant) with TMR4_CH2, TMR11_CH1C, I2C1_SDA, SPI3_SCK, USART1_RX, USART4_CTS and XMC_NADV.
44 BOOT0 input Dedicated boot mode select pin with a built-in weak pull-down that cannot be disabled, used with the user system data nBOOT1 bit to select the startup mode.
45 PB8 bidirectional GPIO (FT, 5 V tolerant) with TMR2_CH1, TMR2_EXT, TMR4_CH3, TMR10_CH1, I2C1_SCL, SPI3_MISO, USART1_TX, USART5_RX and CAN1_RX.
46 PB9 bidirectional GPIO (FT, 5 V tolerant) with IR_OUT, TMR2_CH2, TMR4_CH4, TMR11_CH1, I2C1_SDA, SPI2_CS, I2S2_WS, SPI3_MOSI, I2C2_SDA, USART5_TX, CAN1_TX and I2S1_MCK.
47 VSS power_in Digital ground pin, which must be at the same potential as VSSA and VDD ground rails.
48 VDD power_in Digital supply pin, operating at 2.4 V to 3.6 V.

Key specifications

Parameter Value
Manufacturer ARTERY(雅特力)
Package LQFP-48(7x7)
Category Embedded Processors & Controllers
Pins 48

Electrical characteristics

Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).

Parameter Symbol Min Typ Max Unit Conditions Page
External main supply voltage VDDx-VSS -0.3 4 V 35
Input voltage on FTa pin set to input floating, input pull-up or input pull-down (min printed as VSS-0.3) VIN 6 V FTa pin set to input floating, input pull-up or input pull-down mode 35
Input voltage on TC pin (min printed as VSS-0.3) VIN 4 V TC pin 35
Voltage difference between different supply pins /ΔVDDx/ 50 mV 35
Voltage difference between different ground pins /VSSx-VSS/ 50 mV 35
Total current through VDD power line (inflow) IVDD 150 mA 35
Total current through VSS ground line (outflow) IVSS 150 mA 35
Output sink current on any GPIO and control pin IIO 25 mA 35
Output current on any GPIO and control pin (printed -25 in the same row) IIO -25 mA 35
Storage temperature range TSTG -60 150 °C 35
Maximum junction temperature TJ 125 °C 35
ADC supply voltage VDDA 2.4 3.6 V 66
Positive reference voltage (max printed as VDDA) VREF+ 2 V 66
Current on VDDA input pin IDDA 1000 1250 μA fADC = 80 MHz 66
Current on VREF+ input pin IVREF+ 470 510 μA fADC = 80 MHz 66
ADC clock frequency fADC 0.6 80 MHz VREF+ ≥ 3.0 V 66
ADC clock frequency fADC 0.6 30 MHz VREF+ < 3.0 V 66
ADC sampling rate, 12-bit, fast channel fS 0.04 5.33 MSPS resolution 12-bit, fast channel 66
ADC sampling rate, 12-bit, slow channel (single printed value; column assumed max) fS 4.21 MSPS resolution 12-bit, slow channel 66
External trigger frequency fTRIG 4.44 MHz fADC = 80 MHz 66
Conversion voltage range (min 0 with VREF- internally connected to ground; max printed as VREF+) VAIN 0 V VREF- internally connected to ground 66
Preempted trigger conversion latency tlat 37.5 ns fADC = 80 MHz 66
Preempted trigger conversion latency tlat 3 1/fADC 66
Regular trigger conversion latency tlatr 25 ns fADC = 80 MHz 66
Regular trigger conversion latency tlatr 2 1/fADC 66
Sampling time tS 0.031 8.006 μs fADC = 80 MHz 66
Sampling time tS 2.5 640.5 1/fADC 66
Total conversion time including sampling tCONV 0.188 8.163 μs fADC = 80 MHz, resolution 12-bit 66
Total conversion time including sampling tCONV 15 653 1/fADC resolution 12-bit 66
OTGFS operating voltage VDD 3 3.6 V 65
OTGFS differential input sensitivity I(OTGFS_D+/D-) VDI 0.2 V 65
OTGFS differential common-mode range (includes VDI range) VCM 0.8 2.5 V includes VDI range 65
OTGFS single-ended receiver threshold VSE 1.3 2 V 65
OTGFS static output low level VOL 0.3 V 1.24 kΩ RL connected to 3.6 V 65
OTGFS static output high level VOH 2.8 3.6 V 15 kΩ RL connected to VSS 65
OTGFS_D+ internal pull-up resistance RPU 0.97 1.24 1.58 kΩ idle state, VIN = VSS 65
OTGFS_D+ internal pull-up resistance RPU 1.66 2.26 3.09 kΩ receive state, VIN = VSS 65
OTGFS_D+/D- internal pull-down resistance RPD 15 19 25 kΩ VIN = VDD 65
OTGFS transceiver startup time tSTARTUP 1 μs 65
OTGFS rise time tr 4 20 ns CL ≤ 50 pF 65
OTGFS fall time tf 4 20 ns CL ≤ 50 pF 65
OTGFS rise/fall time matching tr/tf trfm 90 110 % 65
OTGFS output signal crossover voltage VCRS 1.3 2 V 65

CAD (KiCad official)

  • Symbol: AT32F423CCT7
  • Footprint: Package_QFP:LQFP-48_7x7mm_P0.5mm
  • 3D model: LQFP-48(7x7) (KiCad packages3D, STEP)
  • 3D model files: at32f423cct7-etched.step / at32f423cct7-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); at32f423cct7.step / at32f423cct7.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: ARTERY(雅特力) datasheet (89 pp, sha256 6d4a423ff66fe757, retrieved 2026-10-17, tier: lcsc)
  • Datasheet language: Chinese. Pin names, descriptions, and specs on this page were extracted and translated to English by ds2sf; the linked PDF is the manufacturer original.
  • Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-haiku-5-5 (text), consensus claude-sonnet-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF