# AT32F423CBT7

**ARTERY(雅特力)** · Microcontrollers (MCU/MPU/SOC) · LQFP48

AT32F423CBT7 from ARTERY(雅特力), in a LQFP48. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

## Pinout

| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | VDD | power_in | Digital power supply, 2.4 V to 3.6 V (VDD is the supply for GPIO, ERTC, LEXT, BPR and LDO; VDDA must be at the same potential as VDD). |
| 2 | PC13 | bidirectional | 5 V-tolerant GPIO (FT) supplied through a power switch that can source only 3 mA, so it must not be used as a current source such as an LED driver; also ERTC_OUT, TAMP1 and WKUP2, with usage limits given in the errata. |
| 3 | PC14 | bidirectional | Standard-level GPIO (TC, not 5 V-tolerant) supplied through the same 3 mA-limited power switch as PC13, with LEXT_IN as its additional function. |
| 4 | PC15 | bidirectional | Standard-level GPIO (TC, not 5 V-tolerant) supplied through the same 3 mA-limited power switch as PC13, with LEXT_OUT as its additional function. |
| 5 | PF0 | bidirectional | Standard-level GPIO (TC) whose additional function is the HEXT crystal input HEXT_IN; alternate functions include TMR1_CH1 and I2C1_SDA. |
| 6 | PF1 | bidirectional | Standard-level GPIO (TC) whose additional function is the HEXT crystal output HEXT_OUT; alternate functions include TMR1_CH2C, I2C1_SCL, SPI2_CS and I2S2_WS. |
| 7 | NRST | bidirectional | Active-low device reset input and internal reset output with a built-in weak pull-up (RPU typ. 40 kΩ), with VIL max 0.8 V and VIH min 2 V. |
| 8 | VSSA | power_in | Analog ground for the ADC and DAC, which must be at the same potential as VSS. |
| 9 | VDDA | power_in | Analog supply for the ADC and DAC, which must be equal to VDD (2.4 V to 3.6 V). |
| 10 | PA0 | bidirectional | 5 V-tolerant GPIO with analog function (FTa): when in analog mode the input must stay below VDD + 0.3 V; also ADC1_IN0 (fast channel), WKUP1 and TAMP2, plus TMR2_CH1 and USART2_RX/CTS. |
| 11 | PA1 | bidirectional | 5 V-tolerant GPIO with analog function (FTa): in analog mode the input must stay below VDD + 0.3 V; also ADC1_IN1 (fast channel), TMR2_CH2, I2C2_SDA and SPI3_CS. |
| 12 | PA2 | bidirectional | 5 V-tolerant GPIO with analog function (FTa): in analog mode the input must stay below VDD + 0.3 V; also ADC1_IN2, TMR2_CH3, USART2_TX and CAN2_RX. |
| 13 | PA3 | bidirectional | 5 V-tolerant GPIO with analog function (FTa): in analog mode the input must stay below VDD + 0.3 V; also ADC1_IN3, TMR2_CH4, I2S2_MCK, USART2_RX and CAN2_TX. |
| 14 | PA4 | bidirectional | 5 V-tolerant GPIO with analog function (FTa): in analog mode the input must stay below VDD + 0.3 V; also ADC1_IN4 and DAC1_OUT, with SPI1_CS, USART2_CK and OTGFS1_OE as alternate functions. |
| 15 | PA5 | bidirectional | 5 V-tolerant GPIO with analog function (FTa): in analog mode the input must stay below VDD + 0.3 V; also ADC1_IN5 and DAC2_OUT, with SPI1_SCK, I2S1_CK and USART3_CK as alternate functions. |
| 16 | PA6 | bidirectional | 5 V-tolerant GPIO with analog function (FTa): in analog mode the input must stay below VDD + 0.3 V; also ADC1_IN6, with TMR1_BRK, TMR3_CH1, SPI1_MISO and USART3_CTS as alternate functions. |
| 17 | PA7 | bidirectional | 5 V-tolerant GPIO with analog function (FTa): in analog mode the input must stay below VDD + 0.3 V; also ADC1_IN7, with TMR1_CH1C, TMR3_CH2, SPI1_MOSI and USART3_TX as alternate functions. |
| 18 | PB0 | bidirectional | 5 V-tolerant GPIO with analog function (FTa): in analog mode the input must stay below VDD + 0.3 V; also ADC1_IN8, with TMR1_CH2C, TMR3_CH3, SPI1_MISO and USART2_RX as alternate functions. |
| 19 | PB1 | bidirectional | 5 V-tolerant GPIO with analog function (FTa): in analog mode the input must stay below VDD + 0.3 V; also ADC1_IN9, with TMR1_CH3C, TMR3_CH4, SPI1_MOSI and USART3_RTS_DE as alternate functions. |
| 20 | PB2 | bidirectional | 5 V-tolerant GPIO with analog function (FTa): in analog mode the input must stay below VDD + 0.3 V; also ADC1_IN20, with TMR2_CH4, TMR3_EXT, I2C3_SMBA and SPI3_MOSI as alternate functions. |
| 21 | PB10 | bidirectional | 5 V-tolerant GPIO with analog function (FTa): in analog mode the input must stay below VDD + 0.3 V; also ADC1_IN21, with TMR2_CH3, I2C2_SCL, SPI2_SCK, USART3_TX and XMC_NOE as alternate functions. |
| 22 | PB11 | bidirectional | 5 V-tolerant GPIO with analog function (FTa): in analog mode the input must stay below VDD + 0.3 V; also ADC1_IN22, with TMR2_CH4, I2C2_SDA, USART3_RX and TMR13_BRK as alternate functions. |
| 23 | PF8 | bidirectional | 5 V-tolerant GPIO (FT) with TMR2_CH2, I2C2_SDA and USART7_TX as alternate functions. |
| 24 | VDD | power_in | Digital power supply, 2.4 V to 3.6 V. |
| 25 | PB12 | bidirectional | 5 V-tolerant GPIO with analog function (FTa): in analog mode the input must stay below VDD + 0.3 V; also ADC1_IN23, with TMR1_BRK, SPI2_CS, USART3_CK and CAN2_RX as alternate functions. |
| 26 | PB13 | bidirectional | 5 V-tolerant GPIO with analog function (FTa): in analog mode the input must stay below VDD + 0.3 V; also ADC1_IN24, with CLKOUT, TMR1_CH1C, SPI2_SCK, USART3_CTS and CAN2_TX as alternate functions. |
| 27 | PB14 | bidirectional | 5 V-tolerant GPIO with analog function (FTa): in analog mode the input must stay below VDD + 0.3 V; also ADC1_IN25, with TMR1_CH2C, SPI2_MISO, USART3_RTS_DE and XMC_D0 as alternate functions. |
| 28 | PB15 | bidirectional | 5 V-tolerant GPIO with analog function (FTa): in analog mode the input must stay below VDD + 0.3 V; also ADC1_IN26 and WKUP7, with ERTC_REFIN, TMR1_CH3C, SPI2_MOSI and TMR12_CH2 as alternate functions. |
| 29 | PA8 | bidirectional | 5 V-tolerant GPIO (FT) with CLKOUT, TMR1_CH1, USART1_CK, USART2_TX and OTGFS1_SOF as alternate functions. |
| 30 | PA9 | bidirectional | 5 V-tolerant GPIO (FT) with CLKOUT, TMR1_CH2, USART1_TX, I2C1_SCL and OTGFS1_VBUS as alternate functions. |
| 31 | PA10 | bidirectional | 5 V-tolerant GPIO (FT) with ERTC_REFIN, TMR1_CH3, USART1_RX, I2C1_SDA and OTGFS1_ID as alternate functions. |
| 32 | PA11 | bidirectional | Standard-level GPIO (TC, not 5 V-tolerant) with TMR1_CH4, USART1_CTS, CAN1_RX and OTGFS1_D- as its functions. |
| 33 | PA12 | bidirectional | Standard-level GPIO (TC, not 5 V-tolerant) with TMR1_EXT, USART1_RTS_DE, CAN1_TX and OTGFS1_D+ as its functions. |
| 34 | PA13 | bidirectional | 5 V-tolerant GPIO (FT) that is shared with the SWDIO/JTMS debug function; also IR_OUT, I2C1_SDA and OTGFS1_OE. |
| 35 | PF6 | bidirectional | 5 V-tolerant GPIO (FT) with TMR2_CH1, I2C2_SCL and USART7_RX as alternate functions. |
| 36 | VDD | power_in | Digital power supply, 2.4 V to 3.6 V. |
| 37 | PA14 | bidirectional | 5 V-tolerant GPIO (FT) that is shared with the SWCLK/JTCK debug function; also I2C1_SMBA, SPI3_MOSI, I2S3_SD and USART2_TX. |
| 38 | PA15 | bidirectional | 5 V-tolerant GPIO (FT) that is shared with the JTDI debug function; also TMR2_CH1, TMR2_EXT, SPI1_CS, USART1_TX and XMC_NE2. |
| 39 | PB3 | bidirectional | 5 V-tolerant GPIO (FT) that is shared with the JTDO/SWO debug function; also TMR2_CH2, SPI1_SCK, USART1_RX and USART5_TX. |
| 40 | PB4 | bidirectional | 5 V-tolerant GPIO (FT) that is shared with the NJTRST debug function; also TMR3_CH1, TMR11_BRK, SPI1_MISO and USART1_CTS. |
| 41 | PB5 | bidirectional | 5 V-tolerant GPIO (FT) with TMR3_CH2, TMR10_BRK, I2C3_SMBA, SPI1_MOSI, USART1_CK and CAN2_RX as alternate functions, and WKUP6 as additional function. |
| 42 | PB6 | bidirectional | 5 V-tolerant GPIO (FT) with TMR4_CH1, TMR10_CH1C, I2C1_SCL, I2S1_MCK, USART1_TX and CAN2_TX as alternate functions. |
| 43 | PB7 | bidirectional | 5 V-tolerant GPIO (FT) with TMR4_CH2, TMR11_CH1C, I2C1_SDA, SPI3_SCK, USART1_RX and XMC_NADV as alternate functions. |
| 44 | BOOT0 | input | Dedicated boot mode selection pin 0 with a built-in weak pull-down that cannot be disabled. |
| 45 | PB8 | bidirectional | 5 V-tolerant GPIO (FT) with TMR2_CH1, TMR2_EXT, TMR4_CH3, TMR10_CH1, I2C1_SCL, USART1_TX and CAN1_RX as alternate functions. |
| 46 | PB9 | bidirectional | 5 V-tolerant GPIO (FT) with IR_OUT, TMR2_CH2, TMR4_CH4, TMR11_CH1, I2C1_SDA, SPI2_CS, USART5_TX and CAN1_TX as alternate functions. |
| 47 | VSS | power_in | Digital ground. |
| 48 | VDD | power_in | Digital power supply, 2.4 V to 3.6 V. |

## Key specifications

| Parameter | Value |
|---|---|
| Manufacturer | ARTERY(雅特力) |
| Package | LQFP48 |
| Category | Embedded Processors & Controllers |
| Pins | 48 |

## Electrical characteristics

Limits as printed in the datasheet (page.json `metadata.characteristics` carries them as data).

| Parameter | Symbol | Min | Typ | Max | Unit | Conditions | Page |
|---|---|---|---|---|---|---|---|
| External main supply voltage VDDx-VSS | VDDx-VSS | -0.3 |  | 4 | V |  | 35 |
| Input voltage on FTa pin, input floating / pull-up / pull-down mode | VIN | -0.3 |  | 6 | V | FTa pin set to input floating, input pull-up or input pull-down mode; min printed as VSS-0.3 | 35 |
| Input voltage on TC pin | VIN | -0.3 |  | 4 | V | min printed as VSS-0.3 | 35 |
| Voltage difference between different VDD supply pins | /ΔVDDx/ |  |  | 50 | mV |  | 35 |
| Voltage difference between different VSS ground pins | /VSSx-VSS/ |  |  | 50 | mV |  | 35 |
| Total current through VDD supply line (inflow) | IVDD |  |  | 150 | mA |  | 35 |
| Total current through VSS ground line (outflow) | IVSS |  |  | 150 | mA |  | 35 |
| Output sink current on any GPIO and control pin | IIO |  |  | 25 | mA |  | 35 |
| Output source current on any GPIO and control pin | IIO | -25 |  |  | mA |  | 35 |
| Storage temperature range | TSTG | -60 |  | 150 | °C |  | 35 |
| Maximum junction temperature | TJ |  |  | 125 | °C |  | 35 |
| Output current limit on PC13, PC14, PC15 (supplied via power switch) |  |  |  | 3 | mA | when PC13, PC14, PC15 are used as output pins | 33 |
| OTGFS transceiver startup time | tSTARTUP |  |  | 1 | μs |  | 65 |
| OTGFS operating voltage | VDD | 3 |  | 3.6 | V |  | 65 |
| Differential input sensitivity (OTGFS_D+/D-) | VDI | 0.2 |  |  |  |  | 65 |
| Differential common-mode range | VCM | 0.8 |  | 2.5 | V | includes VDI range | 65 |
| Single-ended receiver threshold | VSE |  | 1.3 | 2 |  |  | 65 |
| Static output low level | VOL |  |  | 0.3 | V | 1.24 kΩ RL connected to 3.6 V | 65 |
| Static output high level | VOH | 2.8 |  | 3.6 | V | 15 kΩ RL connected to VSS | 65 |
| OTGFS_D+ internal pull-up resistance, idle state | RPU | 0.97 | 1.24 | 1.58 | kΩ | idle state, VIN = VSS | 65 |
| OTGFS_D+ internal pull-up resistance, receive state | RPU | 1.66 | 2.26 | 3.09 | kΩ | receive state, VIN = VSS | 65 |
| OTGFS_D+/D- internal pull-down resistance | RPD | 15 | 19 | 25 | kΩ | VIN = VDD | 65 |
| OTGFS rise time | tr | 4 |  | 20 | ns | CL ≤ 50 pF | 65 |
| OTGFS fall time | tf | 4 |  | 20 | ns | CL ≤ 50 pF | 65 |
| OTGFS rise/fall time matching | trfm | 90 |  | 110 | % |  | 65 |
| OTGFS output signal crossover voltage | VCRS |  | 1.3 | 2 | V |  | 65 |
| ADC supply voltage | VDDA | 2.4 |  | 3.6 | V |  | 66 |
| ADC positive reference voltage | VREF+ | 2 |  |  | V |  | 66 |
| Current into VDDA input pin | IDDA |  | 1000 | 1250 | μA | fADC = 80 MHz | 66 |
| Current into VREF+ input pin | IVREF+ |  | 470 | 510 | μA | fADC = 80 MHz | 66 |
| ADC clock frequency | fADC | 0.6 |  | 80 | MHz | VREF+ ≥ 3.0 V | 66 |
| ADC clock frequency | fADC | 0.6 |  | 30 | MHz | VREF+ < 3.0 V | 66 |
| ADC sampling rate, 12-bit resolution, fast channel | fS | 0.04 |  | 5.33 | MSPS | resolution 12-bit | 66 |
| ADC sampling rate, 12-bit resolution, slow channel | fS |  |  | 4.21 | MSPS | resolution 12-bit | 66 |
| ADC sampling rate, 10-bit resolution, fast channel | fS | 0.047 |  | 6.15 | MSPS | resolution 10-bit | 66 |
| ADC sampling rate, 10-bit resolution, slow channel | fS |  |  | 4.71 | MSPS | resolution 10-bit | 66 |
| ADC sampling rate, 8-bit resolution, fast channel | fS | 0.055 |  | 7.27 | MSPS | resolution 8-bit | 66 |
| ADC sampling rate, 8-bit resolution, slow channel | fS |  |  | 5.33 | MSPS | resolution 8-bit | 66 |
| ADC sampling rate, 6-bit resolution, fast channel | fS | 0.067 |  | 8.88 | MSPS | resolution 6-bit | 66 |
| ADC sampling rate, 6-bit resolution, slow channel | fS |  |  | 6.15 | MSPS | resolution 6-bit | 66 |
| ADC external trigger frequency | fTRIG |  |  | 4.44 | MHz | fADC = 80 MHz | 66 |
| ADC external trigger frequency | fTRIG |  |  | 18 | 1/fADC |  | 66 |
| ADC conversion voltage range | VAIN | 0 |  |  | V | VREF- internally connected to ground | 66 |
| ADC internal sample-and-hold capacitance | CADC |  | 10 |  | pF |  | 66 |
| ADC preemption trigger conversion latency | tlat |  |  | 37.5 | ns | fADC = 80 MHz | 66 |
| ADC preemption trigger conversion latency | tlat |  |  | 3 | 1/fADC |  | 66 |
| ADC regular trigger conversion latency | tlatr |  |  | 25 | ns | fADC = 80 MHz | 66 |
| ADC regular trigger conversion latency | tlatr |  |  | 2 | 1/fADC |  | 66 |
| ADC sampling time | tS | 0.031 |  | 8.006 | μs | fADC = 80 MHz | 66 |
| ADC sampling time | tS | 2.5 |  | 640.5 | 1/fADC |  | 66 |
| ADC total conversion time (including sampling) | tCONV | 0.188 |  | 8.163 | μs | fADC = 80 MHz, 12-bit resolution | 66 |
| ADC total conversion time (including sampling) | tCONV | 15 |  | 653 | 1/fADC | 12-bit resolution; sampling tS + successive approximation 12.5 | 66 |

## CAD (KiCad official)

- Symbol: `AT32F423CBT7`
- Footprint: `Package_QFP:LQFP-48_7x7mm_P0.5mm`
- 3D model: LQFP48 (KiCad packages3D, STEP)
- 3D model files: `at32f423cbt7-etched.step` / `at32f423cbt7-etched.glb` carry the MPN laser-etched on the die in a toggleable `Adom.LaserEtch` group (Fusion-ready); `at32f423cbt7.step` / `at32f423cbt7.glb` are the bare package body.

## Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

- **Datasheet:** [ARTERY(雅特力) datasheet](https://jlcpcb.com/api/file/downloadByFileSystemAccessId/8756343712567963648) (89 pp, sha256 `6d4a423ff66fe757`, retrieved 2026-10-20, tier: lcsc)
- **Datasheet language:** Chinese. Pin names, descriptions, and specs on this page were extracted and translated to English by ds2sf; the linked PDF is the manufacturer original.
- **Extractor:** parts-factory `2.0.0` / `extract_pins 0.3`, primary `claude-haiku-5-5` (text), consensus `claude-sonnet-5-5` (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
- **CAD:** KiCad official libraries (CC-BY-SA 4.0).

[Datasheet PDF](docs/at32f423cbt7-datasheet.pdf)