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Contents

Pinout
Key specifications
Electrical characteristics
CAD (KiCad official)
Provenance

README

markdown

AT32F421K8U7

ARTERY · Microcontrollers (MCU/MPU/SOC) · QFN-32(5x5)

AT32F421K8U7 from ARTERY, in a QFN-32(5x5). Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin	Name	Type	Function
1	VDD	power_in	Digital power supply.
2	PF0 / HEXT_IN	bidirectional	General I/O (TC standard level) with alternate function I2C1_SDA and additional function HEXT_IN, the 4 to 25 MHz external crystal input.
3	PF1 / HEXT_OUT	bidirectional	General I/O (TC standard level) with alternate function I2C1_SCL and additional function HEXT_OUT, the external crystal output.
4	NRST	bidirectional	Device reset input and internal reset output, active low, with an embedded weak pull-up resistor.
5	VDDA / VREF+	power_in	Analog power supply and positive reference voltage for the ADC.
6	PA0	bidirectional	5 V-tolerant analog-capable I/O (FTa) with ADC1_IN0, CMP1_INP2, CMP1_INM6, WKUP1, and alternate functions TMR1_EXT, USART2_CTS, I2C2_SCL and CMP1_OUT; it loses 5 V tolerance in analog mode, where the input must stay below VDD + 0.3 V.
7	PA1	bidirectional	5 V-tolerant analog-capable I/O (FTa) with ADC1_IN1 and CMP1_INP1, and alternate functions TMR15_CH1C, USART2_RTS, I2C2_SDA and EVENTOUT; the input must stay below VDD + 0.3 V in analog mode.
8	PA2	bidirectional	5 V-tolerant analog-capable I/O (FTa) with ADC1_IN2 and CMP1_INM7, and alternate functions TMR15_CH1 and USART2_TX (bootloader USART2 TX); the input must stay below VDD + 0.3 V in analog mode.
9	PA3	bidirectional	5 V-tolerant analog-capable I/O (FTa) with ADC1_IN3, and alternate functions TMR15_CH2, USART2_RX and I2S2_MCK (bootloader USART2 RX); the input must stay below VDD + 0.3 V in analog mode.
10	PA4	bidirectional	5 V-tolerant analog-capable I/O (FTa) with ADC1_IN4 and CMP1_INM4, and alternate functions TMR14_CH1, USART2_CK, SPI1_CS and I2S1_WS; the input must stay below VDD + 0.3 V in analog mode.
11	PA5	bidirectional	5 V-tolerant analog-capable I/O (FTa) with ADC1_IN5, CMP1_INP0 and CMP1_INM5, and alternate functions SPI1_SCK and I2S1_CK; the input must stay below VDD + 0.3 V in analog mode.
12	PA6	bidirectional	5 V-tolerant analog-capable I/O (FTa) with ADC1_IN6, and alternate functions TMR1_BRK, TMR3_CH1, TMR16_CH1, SPI1_MISO, I2S1_MCK, I2S2_MCK, CMP1_OUT and EVENTOUT; the input must stay below VDD + 0.3 V in analog mode.
13	PA7	bidirectional	5 V-tolerant analog-capable I/O (FTa) with ADC1_IN7, and alternate functions TMR1_CH1C, TMR3_CH2, TMR14_CH1, TMR17_CH1, SPI1_MOSI, I2S1_SD and EVENTOUT; the input must stay below VDD + 0.3 V in analog mode.
14	PB0	bidirectional	5 V-tolerant analog-capable I/O (FTa) with ADC1_IN8, and alternate functions TMR1_CH2C, TMR3_CH3, USART2_RX, I2S1_MCK and EVENTOUT; the input must stay below VDD + 0.3 V in analog mode.
15	PB1	bidirectional	5 V-tolerant analog-capable I/O (FTa) with ADC1_IN9, and alternate functions TMR1_CH3C, TMR3_CH4, TMR14_CH1, SPI2_SCK and I2S2_CK; the input must stay below VDD + 0.3 V in analog mode.
16	PB2	bidirectional	5 V-tolerant analog-capable I/O (FTa) with ADC1_IN10 and alternate function TMR3_EXT; the input must stay below VDD + 0.3 V in analog mode.
17	VDD	power_in	Digital power supply.
18	PA8	bidirectional	5 V-tolerant general-purpose I/O (FT) with alternate functions TMR1_CH1, USART1_CK, USART2_TX, I2C2_SCL, CLKOUT and EVENTOUT.
19	PA9	bidirectional	5 V-tolerant general-purpose I/O (FT) with alternate functions TMR1_CH2, TMR15_BRK, USART1_TX (bootloader USART1 TX), I2C1_SCL, I2C2_SMBA and CLKOUT.
20	PA10	bidirectional	5 V-tolerant general-purpose I/O (FT) with alternate functions TMR1_CH3, TMR17_BRK, USART1_RX (bootloader USART1 RX) and I2C1_SDA.
21	PA11	bidirectional	5 V-tolerant general-purpose I/O (FT) with alternate functions TMR1_CH4, USART1_CTS, I2C1_SMBA, I2C2_SCL, CMP1_OUT and EVENTOUT.
22	PA12	bidirectional	5 V-tolerant general-purpose I/O (FT) with alternate functions TMR1_EXT, USART1_RTS, I2C2_SDA and EVENTOUT.
23	PA13	bidirectional	5 V-tolerant general-purpose I/O (FT) that is configured as SWDIO after reset, with an internal pull-up enabled on SWDIO; alternate functions include IR_OUT, SPI2_MISO and I2S2_MCK.
24	PA14	bidirectional	5 V-tolerant general-purpose I/O (FT) that is configured as SWCLK after reset, with an internal pull-down enabled on SWCLK; alternate functions include USART2_TX, SPI2_MOSI and I2S2_SD.
25	PA15	bidirectional	5 V-tolerant general-purpose I/O (FT) with alternate functions USART2_RX, SPI1_CS, I2S1_WS, SPI2_CS, I2S2_WS and EVENTOUT.
26	PB3	bidirectional	5 V-tolerant general-purpose I/O (FT) with alternate functions SPI1_SCK, I2S1_CK, SPI2_SCK, I2S2_CK and EVENTOUT.
27	PB4	bidirectional	5 V-tolerant general-purpose I/O (FT) with alternate functions TMR3_CH1, TMR17_BRK, SPI1_MISO, I2S1_MCK, SPI2_MISO, I2S2_MCK, I2C2_SDA and EVENTOUT.
28	PB5	bidirectional	5 V-tolerant general-purpose I/O (FT) with alternate functions TMR3_CH2, TMR16_BRK, SPI1_MOSI, I2S1_SD, SPI2_MOSI, I2S2_SD and I2C1_SMBA, and additional function WKUP6.
29	PB6	bidirectional	5 V-tolerant general-purpose I/O (FT) with alternate functions TMR16_CH1C, USART1_TX, I2S1_MCK and I2C1_SCL.
30	PB7	bidirectional	5 V-tolerant general-purpose I/O (FT) with alternate functions TMR17_CH1C, USART1_RX and I2C1_SDA.
31	BOOT0	input	Dedicated boot mode selection pin 0 with an embedded weak pull-down resistor.
32	PB8	bidirectional	5 V-tolerant general-purpose I/O (FT) with alternate functions TMR16_CH1 and I2C1_SCL.
33	EPAD (VSS/VSSA)	power_in	Exposed pad serving as the digital ground and analog ground for the package.

Key specifications

Parameter	Value
Manufacturer	ARTERY
Package	QFN-32(5x5)
Category	Embedded Processors & Controllers
Pins	33

Electrical characteristics

Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).

Parameter	Symbol	Min	Typ	Max	Unit	Conditions	Page
External main supply voltage (including VDDA and VDD)	VDD-VSS	-0.3		4	V		27
Input voltage on FTa GPIO (set as input floating, input pull-up or input pull-down mode)	VIN	-0.3		6	V	set as input floating, input pull-up or input pull-down mode	27
Input voltage on TC GPIO	VIN	-0.3		4	V		27
Input voltage on FTa GPIO (set as analog mode)	VIN	-0.3		4	V	set as analog mode	27
Variations between different VDD power pins	/ΔVDDx/			50	mV		27
Variations between all the different ground pins	/VSSx-VSS/			50	mV		27
Total current into VDD power lines (source)	IVDD			150	mA		27
Total current out of VSS ground lines (sink)	IVSS			150	mA		27
Output current sunk by any GPIO and control pin	IIO			25	mA		27
Output current source by any GPIO and control pin	IIO			-25	mA		27
Storage temperature range	TSTG	-60		150	°C		27
Maximum junction temperature	TJ			125	°C		27
Electrostatic discharge voltage (human body model)	VESD(HBM)	-6000		6000	V	TA = +25 °C, conforms to JS-001-2017	28
Electrostatic discharge voltage (charge device model)	VESD(CDM)	-1000		1000	V	TA = +25 °C, conforms to JS-002-2018	28
Internal AHB clock frequency	fHCLK	0		120	MHz		29
Internal APB1/2 clock frequency	fPCLK1/2	0			MHz		29
Digital operating voltage	VDD	2.4		3.6	V		29
Power dissipation QFN32 (5 x 5 mm)	PD			503	mW	TA = 105 °C	29
Ambient temperature	TA	-40		105	°C		29
VDD rise time rate	tVDD	0			ms/V		29
VDD fall time rate		20			μs/V		29
Power-on reset threshold	VPOR	1.73	2.06	2.4	V		29
Low voltage reset threshold	VLVR	1.62	1.88	2.16	V		29
PVM current consumption	IDD (PVM)		20	30	μA		30
Programming time	TPROG		60	65	μs		31
Page erase time	tERASE		6.6	8	ms		31
Mass erase time	tME		8.2	10	ms		31
Endurance	NEND	100			kcycles	TA = -40 ~ 105 °C	31
Data retention	tRET	10			years	TA = 105 °C	31
HEXT oscillator frequency	fHEXT_IN	4	8	25	MHz		38
HEXT user external clock source frequency	fHEXT_ext	1	8	25	MHz		39
HEXT_IN duty cycle	Duty(HEXT)	45		55	%		39
LEXT user external clock source frequency	fLEXT_ext		32.768	1000	kHz		41
LEXT_IN duty cycle	Duty(LEXT)	30		70	%		41
HICK duty cycle	DuCy(HICK)	45		55	%		42
Accuracy of the HICK oscillator, user-trimmed	ACCHICK	-1		1	%	User-trimmed with the CRM_CTRL register	42
Accuracy of the HICK oscillator, factory-calibrated	ACCHICK	-2		1.5	%	TA = -40 ~ 105 °C	42
HICK oscillator power consumption	IDD(HICK)			290	μA		42
LICK frequency	fLICK	25	35	45	kHz		42
PLL input clock	fPLL_IN	2	8	16	MHz		43
PLL multiplier output clock	fPLL_OUT	16		120	MHz		43
PLL lock time	tLOCK			200	μs		43
Cycle-to-cycle jitter	Jitter			300	ps		43
GPIO input low level voltage	VIL	-0.3			V		44
FT GPIO input high level voltage	VIH			5.5	V		44
Weak pull-up equivalent resistor	RPU	65	80	130	kΩ	VIN = VSS	44
Weak pull-down equivalent resistor	RPD	65	70	130	kΩ	VIN = VDD	44
Input leakage current, FT and FTa GPIO	Ilkg	-1		1	μA	VSS ≤ VIN ≤ 5.5 V, FT and FTa GPIO	44
Output low level voltage, CMOS standard, normal strength	VOL			0.4	V	CMOS standard, IIO = 4 mA, 2.7 V ≤ VDD ≤ 3.6 V	45
Output low level voltage, TTL standard, normal strength	VOL			0.4	V	TTL standard, IIO = 2 mA, 2.7 V ≤ VDD ≤ 3.6 V	45
Output high level voltage, TTL standard, normal strength	VOH	2.4			V		45
Output low level voltage, normal strength	VOL			1.3	V	IIO = 9 mA, 2.7 V ≤ VDD ≤ 3.6 V	45
Pulse width of external signals detected by EXINT controller	tEXINTpw	10			ns		45
NRST input low level voltage	VIL(NRST)	-0.3		0.72	V		46
NRST input high level voltage	VIH(NRST)	2			V		46
NRST weak pull-up equivalent resistor	RPU	30	40	50	kΩ	VIN = VSS	46
NRST input low level invalid time	tILV(NRST)			40	μs		46
ADC clock frequency	fADC	0.6		28	MHz		51
Current on the VDDA input pin	IDDA		480	560	μA		51
Thermal resistance junction-ambient, QFN32, 5 x 5 mm	ΘJA		39.8		°C/W		70

CAD (KiCad official)

Symbol: AT32F421K8U7
Footprint: Package_DFN_QFN:QFN-32-1EP_5x5mm_P0.5mm_EP3.3x3.3mm
3D model: QFN-32(5x5) (KiCad packages3D, STEP)
3D model files: at32f421k8u7-etched.step / at32f421k8u7-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); at32f421k8u7.step / at32f421k8u7.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

Datasheet: ARTERY datasheet (73 pp, sha256 549f03d7f8d31eb7, retrieved 2026-10-17, tier: lcsc)
Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-haiku-5-5 (text), consensus claude-sonnet-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF