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AT32F421F8P7
Public Made by Adomby adom
ARTERY Microcontrollers (MCU/MPU/SOC), TSSOP-20. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.
3D Model
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Symbol & Footprint
Schematic Symbol
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PCB Footprint
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Datasheet
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README
markdownAT32F421F8P7
ARTERY · Microcontrollers (MCU/MPU/SOC) · TSSOP-20
AT32F421F8P7 from ARTERY, in a TSSOP-20. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.
Pinout
| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | BOOT0 | input | Boot mode select 0 (dedicated pin with built-in weak pull-down that cannot be disabled), used with the nBOOT1 option bit to select user flash, system memory or SRAM boot at startup. |
| 2 | PF0 / OSC_IN | bidirectional | General-purpose I/O (TC standard-level, alternate function I2C1_SDA) that doubles as the HSE oscillator input OSC_IN for a 4-25 MHz crystal or resonator (or external clock input). |
| 3 | PF1 / OSC_OUT | bidirectional | General-purpose I/O (TC standard-level, alternate function I2C1_SCL) that doubles as the HSE oscillator output OSC_OUT for a 4-25 MHz crystal or resonator. |
| 4 | NRST | bidirectional | Active-low device reset input and internal reset output with an internal pull-up (about 40 kΩ typical); the input must be pulled below the maximum VIL(NRST) of 0.72 V to reset reliably. |
| 5 | VDDA / VREF+ | power_in | Analog supply 2.4-3.6 V for the ADC and comparator, which must be connected to the same supply as VDD (up to 300 mV difference allowed), and also serves as the positive ADC reference voltage VREF+. |
| 6 | PA0 | bidirectional | 5 V-tolerant FTa I/O in input modes (not 5 V-tolerant in analog mode, where the input must stay below VDD + 0.3 V) with ADC_IN0, COMP_INP2, COMP_INM6 and WKUP1 functions, plus TMR1_ETR, USART2_CTS, I2C2_SCL and COMP_OUT alternates. |
| 7 | PA1 | bidirectional | 5 V-tolerant FTa I/O in input modes (input must stay below VDD + 0.3 V in analog mode) with ADC_IN1 and COMP_INP1 analog functions, plus TMR15_CH1N, USART2_RTS, I2C2_SDA and EVENTOUT alternates. |
| 8 | PA2 | bidirectional | 5 V-tolerant FTa I/O in input modes (input must stay below VDD + 0.3 V in analog mode) with ADC_IN2 and COMP2_INM7 analog functions, plus TMR15_CH1 and USART2_TX alternates. |
| 9 | PA3 | bidirectional | 5 V-tolerant FTa I/O in input modes (input must stay below VDD + 0.3 V in analog mode) with ADC_IN3 analog function, plus TMR15_CH2, USART2_RX and I2S2_MCK alternates. |
| 10 | PA4 | bidirectional | 5 V-tolerant FTa I/O in input modes (input must stay below VDD + 0.3 V in analog mode) with ADC_IN4 and COMP_INM4 analog functions, plus TMR14_CH1, USART2_CK, SPI1_NSS and I2S1_WS alternates. |
| 11 | PA5 | bidirectional | 5 V-tolerant FTa I/O in input modes (input must stay below VDD + 0.3 V in analog mode) with ADC_IN5, COMP_INP0 and COMP_INM5 analog functions, plus SPI1_SCK and I2S1_CK alternates. |
| 12 | PA6 | bidirectional | 5 V-tolerant FTa I/O in input modes (input must stay below VDD + 0.3 V in analog mode) with ADC_IN6 analog function, plus TMR1_BKIN, TMR3_CH1, TMR16_CH1, SPI1_MISO, I2S1_MCK, I2S2_MCK, COMP_OUT and EVENTOUT alternates. |
| 13 | PA7 | bidirectional | 5 V-tolerant FTa I/O in input modes (input must stay below VDD + 0.3 V in analog mode) with ADC_IN7 analog function, plus TMR1_CH1N, TMR3_CH2, TMR14_CH1, TMR17_CH1, SPI1_MOSI, I2S1_SD and EVENTOUT alternates. |
| 14 | PB1 | bidirectional | 5 V-tolerant FTa I/O in input modes (input must stay below VDD + 0.3 V in analog mode) with ADC_IN9 analog function, plus TMR1_CH3N, TMR3_CH4, TMR14_CH1, SPI2_SCK and I2S2_CK alternates. |
| 15 | VSS | power_in | Digital ground for the device; all VSS pins must be connected to the external ground supply within the allowed range. |
| 16 | VDD | power_in | Digital supply 2.4-3.6 V for the I/O pins, ERTC, external 32 kHz oscillator, backup registers and internal regulator; must be within the allowed range together with VDDA. |
| 17 | PA9 | bidirectional | 5 V-tolerant FT I/O with TMR1_CH2, TMR15_BKIN, USART1_TX, I2C1_SCL, I2C2_SMBA and CLKOUT alternates; on TSSOP20 this pin can instead be software-remapped to PA11 (footnote 3). |
| 18 | PA10 | bidirectional | 5 V-tolerant FT I/O with TMR1_CH3, TMR17_BKIN, USART1_RX and I2C1_SDA alternates; on TSSOP20 this pin can instead be software-remapped to PA12 (footnote 3). |
| 19 | PA13 | bidirectional | 5 V-tolerant FT I/O that after reset is configured as the SWDIO debug pin with internal pull-up enabled, with alternates IR_OUT, SPI2_MISO and I2S2_MCK. |
| 20 | PA14 | bidirectional | 5 V-tolerant FT I/O that after reset is configured as the SWCLK debug pin with internal pull-down enabled, with alternates USART2_TX, SPI2_MOSI and I2S2_SD. |
Key specifications
| Parameter | Value |
|---|---|
| Manufacturer | ARTERY |
| Package | TSSOP-20 |
| Category | Embedded Processors & Controllers |
| Pins | 20 |
CAD (KiCad official)
- Symbol:
AT32F421F8P7 - Footprint:
Package_SO:TSSOP-20_4.4x6.5mm_P0.65mm - 3D model: TSSOP-20 (KiCad packages3D, STEP)
- 3D model files:
at32f421f8p7-etched.step/at32f421f8p7-etched.glbcarry the MPN laser-etched on the die in a toggleableAdom.LaserEtchgroup (Fusion-ready);at32f421f8p7.step/at32f421f8p7.glbare the bare package body.
Provenance
Data extracted from the manufacturer datasheet, not a distributor listing:
- Datasheet: ARTERY datasheet (80 pp, sha256
13db109fb9f3fe38, retrieved 2026-10-09, tier: lcsc) - Datasheet language: Chinese. Pin names, descriptions, and specs on this page were extracted and translated to English by ds2sf; the linked PDF is the manufacturer original.
- Extractor: parts-factory
2.0.0/extract_pins 0.3, primaryclaude-haiku-5-5(text), consensusclaude-sonnet-5-5(agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish. - CAD: KiCad official libraries (CC-BY-SA 4.0).