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Contents

Pinout
Key specifications
CAD (KiCad official)
Provenance

README

markdown

AT32F421C8T7

ARTERY · Microcontrollers (MCU/MPU/SOC) · LQFP-48(7x7)

AT32F421C8T7 from ARTERY, in a LQFP-48(7x7). Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin	Name	Type	Function
1	VDD	power_in	Digital supply for I/O pins, ERTC, external 32 kHz oscillator, backup registers and internal regulator, specified at 2.4 V to 3.6 V.
2	PC13	bidirectional	5 V-tolerant (FT) general-purpose I/O with TAMPER-RTC and WKUP2 functions.
3	PC14/OSC32_IN	bidirectional	Standard-level (TC) I/O whose alternate function OSC32_IN is the input of the 32.768 kHz LSE oscillator.
4	PC15/OSC32_OUT	bidirectional	Standard-level (TC) I/O whose alternate function OSC32_OUT is the output of the 32.768 kHz LSE oscillator.
5	PF0/OSC_IN	bidirectional	Standard-level (TC) I/O whose alternate function OSC_IN is the 4-25 MHz HSE oscillator input; also I2C1_SDA.
6	PF1/OSC_OUT	bidirectional	Standard-level (TC) I/O whose alternate function OSC_OUT is the HSE oscillator output; also I2C1_SCL.
7	NRST	bidirectional	Active-low device reset input and internal reset output with a non-disconnectable internal weak pull-up (RPU typically 40 kΩ, 30-50 kΩ).
8	VSSA/VREF-	power_in	Analog ground and negative reference voltage; VSSA must be connected to VSS.
9	VDDA/VREF+	power_in	Analog supply for the ADC and COMP (2.4-3.6 V, must be connected to VDD with at most 300 mV difference) and positive ADC reference voltage.
10	PA0	bidirectional	FTa I/O (5 V-tolerant only as digital input, not in analog mode) with ADC_IN0, COMP_INP2, COMP_INM6, WKUP1, TMR1_ETR, USART2_CTS, I2C2_SCL and COMP_OUT functions.
11	PA1	bidirectional	FTa I/O (5 V-tolerant only as digital input) with ADC_IN1, COMP_INP1, TMR15_CH1N, USART2_RTS, I2C2_SDA and EVENTOUT functions.
12	PA2	bidirectional	FTa I/O (5 V-tolerant only as digital input) with ADC_IN2, COMP2_INM7, TMR15_CH1 and USART2_TX functions.
13	PA3	bidirectional	FTa I/O (5 V-tolerant only as digital input) with ADC_IN3, TMR15_CH2, USART2_RX and I2S2_MCK functions.
14	PA4	bidirectional	FTa I/O (5 V-tolerant only as digital input) with ADC_IN4, COMP_INM4, TMR14_CH1, USART2_CK, SPI1_NSS and I2S1_WS functions.
15	PA5	bidirectional	FTa I/O (5 V-tolerant only as digital input) with ADC_IN5, COMP_INP0, COMP_INM5, SPI1_SCK and I2S1_CK functions.
16	PA6	bidirectional	FTa I/O (5 V-tolerant only as digital input) with ADC_IN6, TMR1_BKIN, TMR3_CH1, TMR16_CH1, SPI1_MISO, I2S1_MCK, I2S2_MCK, COMP_OUT and EVENTOUT functions.
17	PA7	bidirectional	FTa I/O (5 V-tolerant only as digital input) with ADC_IN7, TMR1_CH1N, TMR3_CH2, TMR14_CH1, TMR17_CH1, SPI1_MOSI, I2S1_SD and EVENTOUT functions.
18	PB0	bidirectional	FTa I/O (5 V-tolerant only as digital input) with ADC_IN8, TMR1_CH2N, TMR3_CH3, USART2_RX, I2S1_MCK and EVENTOUT functions.
19	PB1	bidirectional	FTa I/O (5 V-tolerant only as digital input) with ADC_IN9, TMR1_CH3N, TMR3_CH4, TMR14_CH1, SPI2_SCK and I2S2_CK functions.
20	PB2	bidirectional	FTa I/O (5 V-tolerant only as digital input) with ADC_IN10 and TMR3_ETR functions.
21	PB10	bidirectional	5 V-tolerant (FT) I/O with SPI2_SCK, I2S2_CK and I2C2_SCL functions.
22	PB11	bidirectional	5 V-tolerant (FT) I/O with I2C2_SDA and EVENTOUT functions.
23	VSS	power_in	Digital ground.
24	VDD	power_in	Digital supply, 2.4 V to 3.6 V.
25	PB12	bidirectional	FTa I/O (5 V-tolerant only as digital input) with ADC_IN11, TMR1_BKIN, TMR15_BKIN, SPI2_NSS, I2S2_WS, I2C2_SMBA and EVENTOUT functions.
26	PB13	bidirectional	FTa I/O (5 V-tolerant only as digital input) with ADC_IN12, TMR1_CH1N, SPI2_SCK, I2S2_CK and I2C2_SCL functions.
27	PB14	bidirectional	FTa I/O (5 V-tolerant only as digital input) with ADC_IN13, TMR1_CH2N, TMR15_CH1, SPI2_MISO, I2S2_MCK and I2C2_SDA functions.
28	PB15	bidirectional	FTa I/O (5 V-tolerant only as digital input) with ADC_IN14, RTC_REFIN, WKUP7, TMR1_CH3N, TMR15_CH2, TMR15_CH1N, SPI2_MOSI and I2S2_SD functions.
29	PA8	bidirectional	5 V-tolerant (FT) I/O with TMR1_CH1, USART1_CK, UART2_TX (as printed), I2C2_SCL, CLKOUT and EVENTOUT functions.
30	PA9	bidirectional	5 V-tolerant (FT) I/O with TMR1_CH2, TMR15_BKIN, USART1_TX, I2C1_SCL, I2C2_SMBA and CLKOUT functions; USART1_TX is used by the bootloader.
31	PA10	bidirectional	5 V-tolerant (FT) I/O with TMR1_CH3, TMR17_BKIN, USART1_RX and I2C1_SDA functions; USART1_RX is used by the bootloader.
32	PA11	bidirectional	5 V-tolerant (FT) I/O with TMR1_CH4, USART1_CTS, I2C1_SMBA, I2C2_SCL, COMP_OUT and EVENTOUT functions.
33	PA12	bidirectional	5 V-tolerant (FT) I/O with TMR1_ETR, USART1_RTS, I2C2_SDA and EVENTOUT functions.
34	PA13	bidirectional	5 V-tolerant (FT) I/O that is configured as SWDIO after reset with internal pull-up enabled; also IR_OUT, SPI2_MISO and I2S2_MCK.
35	PF6	bidirectional	5 V-tolerant (FT) I/O with I2C2_SCL function.
36	PF7	bidirectional	5 V-tolerant (FT) I/O with I2C2_SDA function.
37	PA14	bidirectional	5 V-tolerant (FT) I/O that is configured as SWCLK after reset with internal pull-down enabled; also USART2_TX, SPI2_MOSI and I2S2_SD.
38	PA15	bidirectional	5 V-tolerant (FT) I/O with USART2_RX, SPI1_NSS, I2S1_WS, SPI2_NSS, I2S2_WS and EVENTOUT functions.
39	PB3	bidirectional	5 V-tolerant (FT) I/O with SPI1_SCK, I2S1_CK, SPI2_SCK, I2S2_CK and EVENTOUT functions.
40	PB4	bidirectional	5 V-tolerant (FT) I/O with TMR3_CH1, TMR17_BKIN, SPI1_MISO, I2S1_MCK, SPI2_MISO, I2S2_MCK, I2C2_SDA and EVENTOUT functions.
41	PB5	bidirectional	5 V-tolerant (FT) I/O with TMR3_CH2, TMR16_BKIN, SPI1_MOSI, I2S1_SD, SPI2_MOSI, I2S2_SD, I2C1_SMBA and WKUP6 functions.
42	PB6	bidirectional	5 V-tolerant (FT) I/O with TMR16_CH1N, USART1_TX, I2S1_MCK and I2C1_SCL functions.
43	PB7	bidirectional	5 V-tolerant (FT) I/O with TMR17_CH1N, USART1_RX and I2C1_SDA functions.
44	BOOT0	input	Boot mode selection pin 0 with a built-in weak pull-down that cannot be disabled (RPD typically 70 kΩ, 65-130 kΩ).
45	PB8	bidirectional	5 V-tolerant (FT) I/O with TMR16_CH1 and I2C1_SCL functions.
46	PB9	bidirectional	5 V-tolerant (FT) I/O with TMR17_CH1, IR_OUT, SPI2_NSS, I2S2_WS, I2S1_MCK, I2C1_SDA and EVENTOUT functions.
47	VSS	power_in	Digital ground.
48	VDD	power_in	Digital supply, 2.4 V to 3.6 V.

Key specifications

Parameter	Value
Manufacturer	ARTERY
Package	LQFP-48(7x7)
Category	Embedded Processors & Controllers
Pins	48

CAD (KiCad official)

Symbol: AT32F421C8T7
Footprint: Package_QFP:LQFP-48_7x7mm_P0.5mm
3D model: LQFP-48(7x7) (KiCad packages3D, STEP)
3D model files: at32f421c8t7-etched.step / at32f421c8t7-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); at32f421c8t7.step / at32f421c8t7.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

Datasheet: ARTERY datasheet (80 pp, sha256 13db109fb9f3fe38, retrieved 2026-10-09, tier: lcsc)
Datasheet language: Chinese. Pin names, descriptions, and specs on this page were extracted and translated to English by ds2sf; the linked PDF is the manufacturer original.
Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-haiku-5-5 (text), consensus claude-sonnet-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF