component
AT32F415RCT7
Public Made by Adomby adom
ARTERY Microcontrollers (MCU/MPU/SOC), LQFP-64(10x10). Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.
3D Model
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Symbol & Footprint
Schematic Symbol
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PCB Footprint
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Datasheet
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README
markdownAT32F415RCT7
ARTERY · Microcontrollers (MCU/MPU/SOC) · LQFP-64(10x10)
AT32F415RCT7 from ARTERY, in a LQFP-64(10x10). Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.
Pinout
| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | VBAT | power_in | Battery backup domain supply, 1.8 V to 3.6 V, which powers the LEXT, ERTC and battery-powered registers (BPR) when VDD is absent. |
| 2 | PC13 | bidirectional | GPIO with TAMPER-RTC alternate function; it is supplied through a power switch limited to 3 mA, so it must not be used as a current source such as an LED driver. |
| 3 | PC14 | bidirectional | GPIO with LEXT_IN alternate function (32.768 kHz oscillator input); supplied through a power switch limited to 3 mA, so it must not source current as an output. |
| 4 | PC15 | bidirectional | GPIO with LEXT_OUT alternate function (32.768 kHz oscillator output); supplied through a power switch limited to 3 mA, so it must not source current as an output. |
| 5 | PD0 | bidirectional | Defaults to HEXT_IN (4 to 25 MHz crystal oscillator input) after reset; software can reconfigure it as GPIO PD0; not 5 V tolerant. |
| 6 | PD1 | bidirectional | Defaults to HEXT_OUT (4 to 25 MHz crystal oscillator output) after reset; software can reconfigure it as GPIO PD1; not 5 V tolerant. |
| 7 | NRST | bidirectional | Active-low reset pin with an internal pull-up (RPU 30 to 50 kΩ); input low must be below VIL max 0.8 V for the MCU to reset. |
| 8 | PC0 | bidirectional | GPIO with ADC1_IN10 analog input and SDIO1_D0 remapped alternate function; not 5 V tolerant. |
| 9 | PC1 | bidirectional | GPIO with ADC1_IN11 analog input and SDIO1_D1 remapped alternate function; not 5 V tolerant. |
| 10 | PC2 | bidirectional | GPIO with ADC1_IN12 analog input and SDIO1_D2 remapped alternate function; not 5 V tolerant. |
| 11 | PC3 | bidirectional | GPIO with ADC1_IN13 analog input and SDIO1_D3 remapped alternate function; not 5 V tolerant. |
| 12 | VSSA/VREF- | power_in | Analog ground for ADC and CMP, which must be at the same potential as VSS, and the ADC negative reference. |
| 13 | VDDA/VREF+ | power_in | Analog supply for ADC and CMP, 2.6 V to 3.6 V, which must be at the same potential as VDD, and the ADC positive reference. |
| 14 | PA0-WKUP | bidirectional | GPIO with ADC1_IN0, WKUP wake-up input, CMP1_OUT, USART2_CTS, TMR2_CH1/TMR2_EXT and TMR5_CH1 alternate functions; remappable TMR1_EXT. |
| 15 | PA1 | bidirectional | GPIO with ADC1_IN1, CMP1_INP1, USART2_RTS, TMR2_CH2 and TMR5_CH2 alternate functions; not 5 V tolerant. |
| 16 | PA2 | bidirectional | GPIO with ADC1_IN2, CMP2_OUT, CMP2_INP2, CMP2_INM6, USART2_TX, TMR2_CH3, TMR5_CH3 and TMR9_CH1 alternate functions; remappable SDIO1_CK; not 5 V tolerant. |
| 17 | PA3 | bidirectional | GPIO with ADC1_IN3, CMP2_INP1, USART2_RX, TMR2_CH4, TMR5_CH4 and TMR9_CH2 alternate functions; remappable SDIO1_CMD; not 5 V tolerant. |
| 18 | PF4 | bidirectional | 5 V tolerant GPIO with UART4_TX and TMR5_CH1 alternate functions. |
| 19 | PF5 | bidirectional | 5 V tolerant GPIO with UART4_RX and TMR5_CH2 alternate functions. |
| 20 | PA4 | bidirectional | GPIO with ADC1_IN4, CMP1_INM4, CMP2_INM4, USART2_CK, SPI1_CS and I2S1_WS alternate functions; remappable SDIO1_D4 and SDIO1_D0; not 5 V tolerant. |
| 21 | PA5 | bidirectional | GPIO with ADC1_IN5, CMP1_INP0, CMP1_INM5, CMP2_INM5, SPI1_SCK and I2S1_CK alternate functions; remappable USART3_CK, SDIO1_D5 and SDIO1_D1; not 5 V tolerant. |
| 22 | PA6 | bidirectional | GPIO with ADC1_IN6, SPI1_MISO and TMR3_CH1 alternate functions; remappable CMP1_OUT, USART3_RX, SDIO1_D6, SDIO1_D2, TMR1_BRK and TMR10_CH1; not 5 V tolerant. |
| 23 | PA7 | bidirectional | GPIO with ADC1_IN7, CMP2_INP0, SPI1_MOSI, I2S1_SD and TMR3_CH2 alternate functions; remappable CMP2_OUT, USART3_TX, SDIO1_D7, SDIO1_D3, TMR1_CH1C and TMR11_CH1; not 5 V tolerant. |
| 24 | PC4 | bidirectional | GPIO with ADC1_IN14 analog input and SDIO1_CK alternate function; not 5 V tolerant. |
| 25 | PC5 | bidirectional | GPIO with ADC1_IN15 analog input and SDIO1_CMD alternate function; not 5 V tolerant. |
| 26 | PB0 | bidirectional | GPIO with ADC1_IN8, I2S1_MCK and TMR3_CH3 alternate functions; remappable USART3_RTS and TMR1_CH2C; not 5 V tolerant. |
| 27 | PB1 | bidirectional | GPIO with ADC1_IN9 and TMR3_CH4 alternate functions; remappable USART3_CTS and TMR1_CH3C; not 5 V tolerant. |
| 28 | PB2/BOOT1 | bidirectional | 5 V tolerant GPIO that also serves as BOOT1 boot-mode select; if unused, datasheet recommends pulling it down. |
| 29 | PB10 | bidirectional | 5 V tolerant GPIO with I2C2_SCL and USART3_TX alternate functions; remappable TMR2_CH3. |
| 30 | PB11 | bidirectional | 5 V tolerant GPIO with I2C2_SDA and USART3_RX alternate functions; remappable TMR2_CH4. |
| 31 | VSS | power_in | Digital ground, which must be at the same potential as the supply ground. |
| 32 | VDD | power_in | Digital supply, 2.6 V to 3.6 V, powering the GPIO pins and the internal LDO. |
| 33 | PB12 | bidirectional | 5 V tolerant GPIO with USART3_CK, I2C2_SMBA, SPI2_CS, I2S2_WS and TMR1_BRK alternate functions. |
| 34 | PB13 | bidirectional | 5 V tolerant GPIO with TMR1_CH1C, USART3_CTS, SPI2_SCK and I2S2_CK alternate functions. |
| 35 | PB14 | bidirectional | 5 V tolerant GPIO with TMR1_CH2C, USART3_RTS and SPI2_MISO alternate functions; remappable TMR9_CH1. |
| 36 | PB15 | bidirectional | 5 V tolerant GPIO with TMR1_CH3C, ERTC_REFIN, SPI2_MOSI and I2S2_SD alternate functions; remappable TMR9_CH2. |
| 37 | PC6 | bidirectional | 5 V tolerant GPIO with I2S2_MCK and SDIO1_D6 alternate functions; remappable TMR1_CH1 and TMR3_CH1. |
| 38 | PC7 | bidirectional | 5 V tolerant GPIO with SDIO1_D7 alternate function; remappable I2S2_MCK, TMR1_CH2 and TMR3_CH2. |
| 39 | PC8 | bidirectional | 5 V tolerant GPIO with SDIO1_D0 alternate function; remappable TMR1_CH3 and TMR3_CH3. |
| 40 | PC9 | bidirectional | 5 V tolerant GPIO with SDIO1_D1 alternate function; remappable I2C2_SDA, TMR1_CH4 and TMR3_CH4. |
| 41 | PA8 | bidirectional | 5 V tolerant GPIO with OTGFS1_SOF, CLKOUT, USART1_CK and TMR1_CH1 alternate functions; remappable I2C2_SCL. |
| 42 | PA9 | bidirectional | 5 V tolerant GPIO with OTGFS1_VBUS, USART1_TX and TMR1_CH2 alternate functions; when OTGFS1 operates as device it must stay high and cannot be used as GPIO or other alternate function (not applicable from silicon revision C). |
| 43 | PA10 | bidirectional | GPIO with OTGFS1_ID, USART1_RX and TMR1_CH3 alternate functions; not 5 V tolerant. |
| 44 | PA11 | bidirectional | GPIO with OTGFS1_D- , USART1_CTS, CAN1_RX and TMR1_CH4 alternate functions; remappable CMP1_OUT; not 5 V tolerant. |
| 45 | PA12 | bidirectional | GPIO with OTGFS1_D+, USART1_RTS, CAN1_TX and TMR1_EXT alternate functions; remappable CMP2_OUT; not 5 V tolerant. |
| 46 | PA13 | bidirectional | 5 V tolerant GPIO that defaults to the JTMS-SWDIO debug function. |
| 47 | PF6 | bidirectional | 5 V tolerant GPIO with I2C1_SCL and I2C2_SCL alternate functions. |
| 48 | PF7 | bidirectional | 5 V tolerant GPIO with I2C1_SDA and I2C2_SDA alternate functions. |
| 49 | PA14 | bidirectional | 5 V tolerant GPIO that defaults to the JTCK-SWCLK debug function. |
| 50 | PA15 | bidirectional | 5 V tolerant GPIO that defaults to the JTDI debug function; alternates SPI1_CS, I2S1_WS, SPI2_CS, I2S2_WS, TMR2_CH1 and TMR2_EXT are selectable. |
| 51 | PC10 | bidirectional | 5 V tolerant GPIO with UART4_TX and SDIO1_D2 alternate functions; remappable USART3_TX. |
| 52 | PC11 | bidirectional | 5 V tolerant GPIO with UART4_RX and SDIO1_D3 alternate functions; remappable USART3_RX. |
| 53 | PC12 | bidirectional | 5 V tolerant GPIO with UART5_TX and SDIO1_CK alternate functions; remappable USART3_CK. |
| 54 | PD2 | bidirectional | 5 V tolerant GPIO with UART5_RX, SDIO1_CMD and TMR3_EXT alternate functions. |
| 55 | PB3 | bidirectional | 5 V tolerant GPIO that defaults to the JTDO debug function; alternates SWO, SPI1_SCK, I2S1_CK, SPI2_SCK, I2S2_CK and TMR2_CH2 are available. |
| 56 | PB4 | bidirectional | 5 V tolerant GPIO that defaults to the NJTRST debug function; alternates SPI1_MISO, SPI2_MISO, I2C2_SDA and TMR3_CH1 are available. |
| 57 | PB5 | bidirectional | 5 V tolerant GPIO with I2C1_SMBA alternate function; remappable SPI1_MOSI, I2S1_SD, SPI2_MOSI, I2S2_SD and TMR3_CH2. |
| 58 | PB6 | bidirectional | 5 V tolerant GPIO with I2C1_SCL and TMR4_CH1 alternate functions; remappable USART1_TX and I2S1_MCK. |
| 59 | PB7 | bidirectional | 5 V tolerant GPIO with I2C1_SDA and TMR4_CH2 alternate functions; remappable USART1_RX. |
| 60 | BOOT0 | input | Boot mode select input (with BOOT1) sampled at startup; its weak pull-down cannot be disabled. |
| 61 | PB8 | bidirectional | 5 V tolerant GPIO with SDIO1_D4, TMR4_CH3 and TMR10_CH1 alternate functions; remappable I2C1_SCL and CAN1_RX. |
| 62 | PB9 | bidirectional | 5 V tolerant GPIO with SDIO1_D5, TMR4_CH4 and TMR11_CH1 alternate functions; remappable I2C1_SDA and CAN1_TX. |
| 63 | VSS | power_in | Digital ground, which must be at the same potential as the supply ground. |
| 64 | VDD | power_in | Digital supply, 2.6 V to 3.6 V, powering the GPIO pins and the internal LDO. |
Key specifications
| Parameter | Value |
|---|---|
| Manufacturer | ARTERY |
| Package | LQFP-64(10x10) |
| Category | Embedded Processors & Controllers |
| Pins | 64 |
Electrical characteristics
Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).
| Parameter | Symbol | Min | Typ | Max | Unit | Conditions | Page |
|---|---|---|---|---|---|---|---|
| Absolute max: external main supply voltage (VDD-VSS, incl. VDDA and VDD) | VDD-VSS | -0.3 | 4 | V | 30 | ||
| Absolute max: input voltage on 5 V tolerant pins | VIN | 6 | V | 5 V tolerant pins; printed minimum is VSS-0.3 | 30 | ||
| Absolute max: input voltage on other pins | VIN | 4 | V | other pins; printed minimum is VSS-0.3 | 30 | ||
| Absolute max: voltage difference between supply pins | /ΔVDDx/ | 50 | mV | 30 | |||
| Absolute max: voltage difference between ground pins | /VSSx-VSS/ | 50 | mV | 30 | |||
| Absolute max: total current through VDD supply line (inflow) | IVDD | 150 | mA | 30 | |||
| Absolute max: total current through VSS ground line (outflow) | IVSS | 150 | mA | 30 | |||
| Absolute max: output sink current on any GPIO and control pin | IIO | 25 | mA | 30 | |||
| Absolute max: output source current on any GPIO and control pin (printed with sign) | IIO | -25 | mA | 30 | |||
| Absolute max: storage temperature range | TSTG | -60 | 150 | °C | 30 | ||
| Absolute max: maximum junction temperature | TJ | 125 | °C | 30 | |||
| OTGFS transceiver startup time | tSTARTUP | 1 | μs | design guaranteed, not production tested | 56 | ||
| OTGFS operating voltage | VDD | 3 | 3.6 | V | 56 | ||
| Differential input sensitivity (OTGFS_D+/D-) | VDI | 0.2 | V | 56 | |||
| Differential common-mode range | VCM | 0.8 | 2.5 | V | includes VDI range | 56 | |
| Single-ended receiver threshold | VSE | 1.3 | 2 | V | 56 | ||
| Static output low level | VOL | 0.3 | V | 1.24 kΩ RL to 3.6 V | 56 | ||
| Static output high level | VOH | 2.8 | 3.6 | V | 15 kΩ RL to VSS | 56 | |
| OTGFS_D+ internal pull-up resistor | RPU | 0.97 | 1.24 | 1.58 | kΩ | VIN = VSS | 56 |
| OTGFS_D+/D- internal pull-down resistor | RPD | 15 | 19 | 25 | kΩ | VIN = VDD | 56 |
| OTGFS data rise time | tr | 4 | 20 | ns | CL ≤ 50 pF | 56 | |
| OTGFS data fall time | tf | 4 | 20 | ns | CL ≤ 50 pF | 56 | |
| OTGFS rise/fall time matching (tr/tf) | trfm | 90 | 110 | % | 56 | ||
| OTGFS output signal crossover voltage | VCRS | 1.3 | 2 | V | 56 | ||
| SD/MMC data transfer clock frequency | fPP | 0 | 48 | MHz | 55 | ||
| SD/MMC clock low time | tW(CKL) | 32 | ns | fPP = 16 MHz | 55 | ||
| SD/MMC clock high time | tW(CKH) | 30 | ns | fPP = 16 MHz | 55 | ||
| SD/MMC clock rise time | tr | 4 | ns | 55 | |||
| SD/MMC clock fall time | tf | 5 | ns | 55 | |||
| SD/MMC CMD, D input valid time (input setup) | tISU | 2 | ns | 55 | |||
| SD/MMC CMD, D input hold time | tIH | 0 | ns | 55 | |||
| SD/MMC CMD, D output valid time (MMC and SD high-speed) | tOV | 6 | ns | 55 | |||
| SD/MMC CMD, D output hold time (MMC and SD high-speed) | tOH | 0 | ns | 55 | |||
| SD/MMC CMD, D output valid default time (SD default mode) | tOVD | 7 | ns | 55 | |||
| SD/MMC CMD, D output hold default time (SD default mode) | tOHD | 0.5 | ns | 55 | |||
| ADC supply voltage | VDDA | 2.6 | 3.6 | V | 57 | ||
| Current on VDDA input pin | IDDA | 560 | 660 | μA | 57 | ||
| ADC clock frequency | fADC | 0.6 | 28 | MHz | 57 | ||
| ADC sampling rate | fS | 0.05 | 2 | MHz | design guaranteed, not production tested | 57 | |
| ADC external trigger frequency | fTRIG | 1.65 | MHz | fADC = 28 MHz | 57 | ||
| ADC external trigger frequency | fTRIG | 17 | 1/fADC | 57 | |||
| ADC conversion voltage range (minimum) | VAIN | 0 | V | VREF- connected internally to ground | 57 | ||
| ADC internal sample and hold capacitance | CADC | 15 | pF | design guaranteed, not production tested | 57 | ||
| ADC injected trigger conversion latency | tlat | 107 | ns | fADC = 28 MHz | 57 | ||
| ADC injected trigger conversion latency | tlat | 3 | 1/fADC | 57 | |||
| ADC regular trigger conversion latency | tlatr | 71.4 | ns | fADC = 28 MHz | 57 | ||
| ADC regular trigger conversion latency | tlatr | 2 | 1/fADC | 57 | |||
| ADC sampling time | tS | 0.053 | 8.55 | μs | fADC = 28 MHz | 57 | |
| ADC sampling time | tS | 1.5 | 239.5 | 1/fADC | 57 | ||
| ADC total conversion time (including sampling time) | tCONV | 0.5 | 9 | μs | fADC = 28 MHz | 57 |
CAD (KiCad official)
- Symbol:
AT32F415RCT7 - Footprint:
Package_QFP:LQFP-64_10x10mm_P0.5mm - 3D model: LQFP-64(10x10) (KiCad packages3D, STEP)
- 3D model files:
at32f415rct7-etched.step/at32f415rct7-etched.glbcarry the MPN laser-etched on the die in a toggleableAdom.LaserEtchgroup (Fusion-ready);at32f415rct7.step/at32f415rct7.glbare the bare package body.
Provenance
Data extracted from the manufacturer datasheet, not a distributor listing:
- Datasheet: ARTERY datasheet (75 pp, sha256
7bd001051ee57bd1, retrieved 2026-10-17, tier: lcsc) - Datasheet language: Chinese. Pin names, descriptions, and specs on this page were extracted and translated to English by ds2sf; the linked PDF is the manufacturer original.
- Extractor: parts-factory
2.0.0/extract_pins 0.3, primaryclaude-haiku-5-5(text), consensusclaude-sonnet-5-5(agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish. - CAD: KiCad official libraries (CC-BY-SA 4.0).