component

AT32F415RBT7-7

Public Made by Adom

by adom

ARTERY Microcontrollers (MCU/MPU/SOC), LQFP-64(7x7). Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.

componentembedded processors & controllersat32f415rbt7-7factory-2.0.0extractor-text
Overview Files Discover Packages Releases Dependencies Issues Breadcrumbs Pull Requests Activity
main
Download ZIP Propose a change
Generated by kicad-footprint-generator · KiCad file format 20260206
Name Last commit message Last updated
docs Publish 0.1.0 · Ray 8d ago
viewers at32f415rbt7-7: viewers · Ray 8d ago
at32f415rbt7-7-etched.glb Publish 0.1.0 · Ray 8d ago
at32f415rbt7-7-etched.step at32f415rbt7-7: factory component page (tier=lcsc) · Ray 8d ago
at32f415rbt7-7-hero.glb at32f415rbt7-7: hero GLB from the etched model (keeps the MPN mark) · Ray 8d ago
at32f415rbt7-7-hero.overlay.json Publish 0.1.0 · Ray 8d ago
at32f415rbt7-7.glb Publish 0.1.0 · Ray 8d ago
at32f415rbt7-7.kicad_mod Publish 0.1.0 · Ray 8d ago
at32f415rbt7-7.kicad_sym Publish 0.1.0 · Ray 8d ago
at32f415rbt7-7.lbr Publish 0.1.0 · Ray 8d ago
at32f415rbt7-7.step Publish 0.1.0 · Ray 8d ago
package.json Publish 0.1.0 · Ray 8d ago
page.json Set visibility: public · Ray 8d ago
README.md Publish 0.1.0 · Ray 8d ago

AT32F415RBT7-7

ARTERY · Microcontrollers (MCU/MPU/SOC) · LQFP-64(7x7)

AT32F415RBT7-7 from ARTERY, in a LQFP-64(7x7). Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 VBAT power_in Backup-domain supply of 1.8 to 3.6 V that powers the LEXT, ERTC and battery-backed registers when VDD is absent.
2 PC13 bidirectional GPIO with TAMPER-RTC function (not 5 V tolerant); it is fed through a power switch limited to 3 mA, so it cannot act as a current source such as an LED driver.
3 PC14 bidirectional GPIO with LEXT_IN 32 kHz oscillator input (not 5 V tolerant); same 3 mA power-switch limit as PC13.
4 PC15 bidirectional GPIO with LEXT_OUT 32 kHz oscillator output (not 5 V tolerant); same 3 mA power-switch limit as PC13.
5 PD0 bidirectional GPIO that defaults to HEXT_IN after reset (not 5 V tolerant) and can be reconfigured to PD0 by software.
6 PD1 bidirectional GPIO that defaults to HEXT_OUT after reset (not 5 V tolerant) and can be reconfigured to PD1 by software.
7 NRST bidirectional Active-low reset pin with an internal pull-up of 30 to 50 kΩ; the input low level must be at or below 0.8 V for a reset to be recognised.
8 PC0 bidirectional GPIO (not 5 V tolerant) with ADC1_IN10 analog input and SDIO1_D0 alternate function.
9 PC1 bidirectional GPIO (not 5 V tolerant) with ADC1_IN11 analog input and SDIO1_D1 alternate function.
10 PC2 bidirectional GPIO (not 5 V tolerant) with ADC1_IN12 analog input and SDIO1_D2 alternate function.
11 PC3 bidirectional GPIO (not 5 V tolerant) with ADC1_IN13 analog input and SDIO1_D3 alternate function.
12 VSSA / VREF- power_in Analog ground for the ADC and comparators that must be at the same potential as VSS, also serving as the negative ADC reference VREF-.
13 VDDA / VREF+ power_in Analog supply of 2.6 to 3.6 V for the ADC and comparators that must be at the same potential as VDD, also serving as the positive ADC reference VREF+.
14 PA0-WKUP bidirectional GPIO (not 5 V tolerant) with WKUP wake-up input, ADC1_IN0 and CMP1_OUT alternate functions; a rising edge on WKUP exits standby mode.
15 PA1 bidirectional GPIO (not 5 V tolerant) with ADC1_IN1, CMP1_INP1 and USART2_RTS alternate functions.
16 PA2 bidirectional GPIO (not 5 V tolerant) with ADC1_IN2, CMP2_OUT and USART2_TX alternate functions; it is also a bootloader UART pin.
17 PA3 bidirectional GPIO (not 5 V tolerant) with ADC1_IN3, CMP2_INP1 and USART2_RX alternate functions.
18 PF4 bidirectional 5 V tolerant GPIO with UART4_TX and TMR5_CH1 alternate functions.
19 PF5 bidirectional 5 V tolerant GPIO with UART4_RX and TMR5_CH2 alternate functions.
20 PA4 bidirectional GPIO (not 5 V tolerant) with ADC1_IN4, USART2_CK, SPI1_CS and I2S1_WS alternate functions.
21 PA5 bidirectional GPIO (not 5 V tolerant) with ADC1_IN5, SPI1_SCK and I2S1_CK alternate functions.
22 PA6 bidirectional GPIO (not 5 V tolerant) with ADC1_IN6, SPI1_MISO and TMR3_CH1 alternate functions.
23 PA7 bidirectional GPIO (not 5 V tolerant) with ADC1_IN7, SPI1_MOSI, I2S1_SD and TMR3_CH2 alternate functions.
24 PC4 bidirectional GPIO (not 5 V tolerant) with ADC1_IN14 analog input and SDIO1_CK alternate function.
25 PC5 bidirectional GPIO (not 5 V tolerant) with ADC1_IN15 analog input and SDIO1_CMD alternate function.
26 PB0 bidirectional GPIO (not 5 V tolerant) with ADC1_IN8, I2S1_MCK, TMR3_CH3 and USART3_RTS alternate functions.
27 PB1 bidirectional GPIO (not 5 V tolerant) with ADC1_IN9, TMR3_CH4 and USART3_CTS alternate functions.
28 PB2 bidirectional 5 V tolerant GPIO that also serves as BOOT1; the datasheet recommends a pull-down on PB2 when it is unused.
29 PB10 bidirectional 5 V tolerant GPIO with I2C2_SCL, USART3_TX and TMR2_CH3 alternate functions.
30 PB11 bidirectional 5 V tolerant GPIO with I2C2_SDA, USART3_RX and TMR2_CH4 alternate functions.
31 VSS power_in Digital ground of the device.
32 VDD power_in Digital supply of 2.6 to 3.6 V for the GPIO pins and the internal LDO.
33 PB12 bidirectional 5 V tolerant GPIO with USART3_CK, I2C2_SMBA, SPI2_CS, I2S2_WS and TMR1_BRK alternate functions.
34 PB13 bidirectional 5 V tolerant GPIO with TMR1_CH1C, USART3_CTS, SPI2_SCK and I2S2_CK alternate functions.
35 PB14 bidirectional 5 V tolerant GPIO with TMR1_CH2C, USART3_RTS, SPI2_MISO and TMR9_CH1 alternate functions.
36 PB15 bidirectional 5 V tolerant GPIO with TMR1_CH3C, ERTC_REFIN, SPI2_MOSI, I2S2_SD and TMR9_CH2 alternate functions.
37 PC6 bidirectional 5 V tolerant GPIO with I2S2_MCK, SDIO1_D6, TMR1_CH1 and TMR3_CH1 alternate functions.
38 PC7 bidirectional 5 V tolerant GPIO with SDIO1_D7, I2S2_MCK, TMR1_CH2 and TMR3_CH2 alternate functions.
39 PC8 bidirectional 5 V tolerant GPIO with SDIO1_D0, TMR1_CH3 and TMR3_CH3 alternate functions.
40 PC9 bidirectional 5 V tolerant GPIO with SDIO1_D1, I2C2_SDA, TMR1_CH4 and TMR3_CH4 alternate functions.
41 PA8 bidirectional 5 V tolerant GPIO with OTGFS1_SOF, CLKOUT, USART1_CK, TMR1_CH1 and I2C2_SCL alternate functions.
42 PA9 bidirectional 5 V tolerant GPIO with OTGFS1_VBUS, USART1_TX and TMR1_CH2; when OTGFS1 operates as a device it must be held high and cannot be used as GPIO (silicon revision C and later are exempt).
43 PA10 bidirectional GPIO (not 5 V tolerant) with OTGFS1_ID, USART1_RX and TMR1_CH3 alternate functions.
44 PA11 bidirectional GPIO (not 5 V tolerant) with OTGFS1_D-, USART1_CTS, CAN1_RX, TMR1_CH4 and CMP1_OUT alternate functions.
45 PA12 bidirectional GPIO (not 5 V tolerant) with OTGFS1_D+, USART1_RTS, CAN1_TX, TMR1_EXT and CMP2_OUT alternate functions.
46 PA13 bidirectional 5 V tolerant GPIO that doubles as the JTMS/SWDIO debug pin.
47 PF6 bidirectional 5 V tolerant GPIO with I2C1_SCL and I2C2_SCL alternate functions.
48 PF7 bidirectional 5 V tolerant GPIO with I2C1_SDA and I2C2_SDA alternate functions.
49 PA14 bidirectional 5 V tolerant GPIO that doubles as the JTCK/SWCLK debug pin.
50 PA15 bidirectional 5 V tolerant GPIO with JTDI, SPI1_CS, I2S1_WS, SPI2_CS, I2S2_WS and TMR2_CH1 alternate functions.
51 PC10 bidirectional 5 V tolerant GPIO with UART4_TX, SDIO1_D2 and remapped USART3_TX alternate functions.
52 PC11 bidirectional 5 V tolerant GPIO with UART4_RX, SDIO1_D3 and remapped USART3_RX alternate functions.
53 PC12 bidirectional 5 V tolerant GPIO with UART5_TX, SDIO1_CK and remapped USART3_CK alternate functions.
54 PD2 bidirectional 5 V tolerant GPIO with UART5_RX, SDIO1_CMD and TMR3_EXT alternate functions.
55 PB3 bidirectional 5 V tolerant GPIO that doubles as the JTDO/SWO trace pin, with SPI1_SCK, I2S1_CK, SPI2_SCK, I2S2_CK and TMR2_CH2 alternate functions.
56 PB4 bidirectional 5 V tolerant GPIO that doubles as the NJTRST debug pin, with SPI1_MISO, SPI2_MISO, I2C2_SDA and TMR3_CH1 alternate functions.
57 PB5 bidirectional 5 V tolerant GPIO with I2C1_SMBA, SPI1_MOSI, I2S1_SD, SPI2_MOSI, I2S2_SD and TMR3_CH2 alternate functions.
58 PB6 bidirectional 5 V tolerant GPIO with I2C1_SCL, TMR4_CH1, USART1_TX and I2S1_MCK alternate functions.
59 PB7 bidirectional 5 V tolerant GPIO with I2C1_SDA, TMR4_CH2 and USART1_RX alternate functions.
60 BOOT0 input Boot-mode select input sampled at start-up together with BOOT1; its weak pull-down cannot be disabled.
61 PB8 bidirectional 5 V tolerant GPIO with SDIO1_D4, TMR4_CH3, TMR10_CH1, I2C1_SCL and CAN1_RX alternate functions.
62 PB9 bidirectional 5 V tolerant GPIO with SDIO1_D5, TMR4_CH4, TMR11_CH1, I2C1_SDA and CAN1_TX alternate functions.
63 VSS power_in Digital ground of the device.
64 VDD power_in Digital supply of 2.6 to 3.6 V for the GPIO pins and the internal LDO.

Key specifications

Parameter Value
Manufacturer ARTERY
Package LQFP-64(7x7)
Category Embedded Processors & Controllers
Pins 64

Electrical characteristics

Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).

Parameter Symbol Min Typ Max Unit Conditions Page
外部主供电电压（包含VDDA和VDD） VDD-VSS -0.3 4 V 30
在5 V容忍的引脚上的输入电压 VIN 6 V 5 V容忍的引脚 30
在其它引脚上的输入电压 VIN 4 V 其它引脚 30
不同供电引脚之间的电压差 /ΔVDDx/ 50 mV 30
不同接地引脚之间的电压差 /VSSx-VSS/ 50 mV 30
经过VDD电源线的总电流（流入电流） IVDD 150 mA 30
经过VSS地线的总电流（流出电流） IVSS 150 mA 30
任意GPIO和控制引脚上的输出灌电流 IIO 25 mA 30
任意GPIO和控制引脚上的输出电流 IIO -25 mA 30
储存温度范围 TSTG -60 150 °C 30
最大结温度 TJ 125 °C 30
供电电压 (ADC) VDDA 2.6 3.6 V 57
在VDDA输入脚上的电流 (ADC) IDDA 560 660 μA 57
ADC时钟频率 fADC 0.6 28 MHz 57
采样速率 fS 0.05 2 MHz 57
外部触发频率 fTRIG 1.65 MHz fADC = 28 MHz 57
外部触发频率 fTRIG 17 1/fADC 57
转换电压范围 VAIN 0 V 57
注入触发转换时延 tlat 107 ns fADC = 28 MHz 57
注入触发转换时延 tlat 3 1/fADC 57
常规触发转换时延 tlatr 71.4 ns fADC = 28 MHz 57
常规触发转换时延 tlatr 2 1/fADC 57
采样时间 tS 0.053 8.55 μs fADC = 28 MHz 57
采样时间 tS 1.5 239.5 1/fADC 57
总转换时间（包括采样时间） tCONV 0.5 9 μs fADC = 28 MHz 57
总转换时间（包括采样时间） tCONV 14 252 1/fADC 57
OTGFS收发器启动时间 tSTARTUP 1 μs 56
OTGFS操作电压 VDD 3 3.6 V 56
差分输入灵敏度 VDI 0.2 V I（OTGFS_D+/D-） 56
差分共模范围 VCM 0.8 2.5 V 包含VDI范围 56
单端接收器阈值 VSE 1.3 2 V 56
静态输出低电平 VOL 0.3 V 1.24 kΩ的RL接至3.6 V 56
静态输出高电平 VOH 2.8 3.6 V 15 kΩ的RL接至VSS 56
OTGFS_D+内部上拉电阻 RPU 0.97 1.24 1.58 kΩ VIN = VSS 56
OTGFS_D+/D-内部下拉电阻 RPD 15 19 25 kΩ VIN = VDD 56
数据传输模式下的时钟频率 fPP 0 48 MHz 55
时钟低时间 tW(CKL) 32 ns fPP = 16 MHz 55
时钟高时间 tW(CKH) 30 ns fPP = 16 MHz 55
时钟上升时间 tr 4 ns 55
时钟下降时间 tf 5 ns 55
CMD、D输入输入有效时间（参照CK） tISU 2 ns 55
CMD、D输入输入保持时间（参照CK） tIH 0 ns 55
MMC和SD高速模式CMD、D输出有效时间（参照CK） tOV 6 ns 55
MMC和SD高速模式CMD、D输出保持时间（参照CK） tOH 0 ns 55
SD默认模式CMD、D输出有效默认时间（参照CK） tOVD 7 ns 55
SD默认模式CMD、D输出保持默认时间（参照CK） tOHD 0.5 ns 55
上升时间 tr 4 20 ns CL ≤ 50 pF 56
下降时间 tf 4 20 ns CL ≤ 50 pF 56
上升下降时间匹配 tr/tf trfm 90 110 % 56
输出信号交叉电压 VCRS 1.3 2 V 56

CAD (KiCad official)

  • Symbol: AT32F415RBT7-7
  • Footprint: Package_QFP:LQFP-64_7x7mm_P0.4mm
  • 3D model: LQFP-64(7x7) (KiCad packages3D, STEP)
  • 3D model files: at32f415rbt7-7-etched.step / at32f415rbt7-7-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); at32f415rbt7-7.step / at32f415rbt7-7.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: ARTERY datasheet (75 pp, sha256 7bd001051ee57bd1, retrieved 2026-10-19, tier: lcsc)
  • Datasheet language: Chinese. Pin names, descriptions, and specs on this page were extracted and translated to English by ds2sf; the linked PDF is the manufacturer original.
  • Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-haiku-5-5 (text), consensus claude-sonnet-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF