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AT32F415RBT7

Public Made by Adom

by adom

ARTERY Microcontrollers (MCU/MPU/SOC), LQFP-64(10x10). Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.

componentembedded processors & controllersat32f415rbt7factory-2.0.0extractor-text
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3D Model

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Symbol & Footprint

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Datasheet

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Contents

README

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AT32F415RBT7

ARTERY · Microcontrollers (MCU/MPU/SOC) · LQFP-64(10x10)

AT32F415RBT7 from ARTERY, in a LQFP-64(10x10). Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 VBAT power_in Backup-domain supply input (1.8-3.6 V) that powers ERTC, LEXT and the battery-backed registers when VDD is absent.
2 PC13 bidirectional GPIO PC13 (not 5 V tolerant), alternate function TAMPER-RTC; it is fed through a power switch limited to 3 mA, so it must not be used as a current source such as an LED driver.
3 PC14 bidirectional GPIO PC14 (not 5 V tolerant), alternate function LEXT_IN; it is fed through a power switch limited to 3 mA and must not be used as a current source.
4 PC15 bidirectional GPIO PC15 (not 5 V tolerant), alternate function LEXT_OUT; it is fed through a power switch limited to 3 mA and must not be used as a current source.
5 PD0 bidirectional Pin is HEXT_IN (4-25 MHz crystal/resonator input) after reset and can be reconfigured by software as GPIO PD0.
6 PD1 bidirectional Pin is HEXT_OUT (crystal/resonator output) after reset and can be reconfigured by software as GPIO PD1.
7 NRST input Active-low reset input with a non-disconnectable internal pull-up (30-50 kΩ); the external reset network must pull it below VIL(NRST) max 0.8 V for the MCU to reset.
8 PC0 bidirectional GPIO PC0 (not 5 V tolerant) with ADC1_IN10 and SDIO1_D0 listed as its alternate functions.
9 PC1 bidirectional GPIO PC1 (not 5 V tolerant) with ADC1_IN11 and SDIO1_D1 listed as its alternate functions.
10 PC2 bidirectional GPIO PC2 (not 5 V tolerant) with ADC1_IN12 and SDIO1_D2 listed as its alternate functions.
11 PC3 bidirectional GPIO PC3 (not 5 V tolerant) with ADC1_IN13 and SDIO1_D3 listed as its alternate functions.
12 VSSA / VREF- power_in Analog ground and negative ADC reference input; VSSA must be at the same potential as VSS.
13 VDDA / VREF+ power_in Analog supply (2.6-3.6 V) for the ADC and comparators, which must be at the same potential as VDD; also the positive ADC reference input VREF+.
14 PA0-WKUP bidirectional GPIO PA0 with WKUP wake-up input (rising edge exits standby mode), ADC1_IN0, CMP1_OUT, USART2_CTS, TMR2_CH1, TMR2_EXT and TMR5_CH1 functions; remap TMR1_EXT.
15 PA1 bidirectional GPIO PA1 (not 5 V tolerant) with ADC1_IN1, CMP1_INP1, USART2_RTS, TMR2_CH2 and TMR5_CH2 functions.
16 PA2 bidirectional GPIO PA2 (not 5 V tolerant) with ADC1_IN2, CMP2_OUT, CMP2_INP2, CMP2_INM6, USART2_TX, TMR2_CH3, TMR5_CH3 and TMR9_CH1; remap SDIO1_CK.
17 PA3 bidirectional GPIO PA3 (not 5 V tolerant) with ADC1_IN3, CMP2_INP1, USART2_RX, TMR2_CH4, TMR5_CH4 and TMR9_CH2 functions; remap SDIO1_CMD.
18 PF4 bidirectional GPIO PF4, 5 V tolerant (FT), with UART4_TX and TMR5_CH1 functions.
19 PF5 bidirectional GPIO PF5, 5 V tolerant (FT), with UART4_RX and TMR5_CH2 functions.
20 PA4 bidirectional GPIO PA4 (not 5 V tolerant) with ADC1_IN4, CMP1_INM4, CMP2_INM4, USART2_CK, SPI1_CS and I2S1_WS functions; remap SDIO1_D4 / SDIO1_D0.
21 PA5 bidirectional GPIO PA5 (not 5 V tolerant) with ADC1_IN5, CMP1_INP0, CMP1_INM5, CMP2_INM5, SPI1_SCK and I2S1_CK functions; remap USART3_CK, SDIO1_D5 / SDIO1_D1.
22 PA6 bidirectional GPIO PA6 (not 5 V tolerant) with ADC1_IN6, SPI1_MISO and TMR3_CH1 functions; remap CMP1_OUT, USART3_RX, SDIO1_D6 / SDIO1_D2, TMR1_BRK and TMR10_CH1.
23 PA7 bidirectional GPIO PA7 (not 5 V tolerant) with ADC1_IN7, CMP2_INP0, SPI1_MOSI, I2S1_SD and TMR3_CH2 functions; remap CMP2_OUT, USART3_TX, SDIO1_D7 / SDIO1_D3, TMR1_CH1C and TMR11_CH1.
24 PC4 bidirectional GPIO PC4 (not 5 V tolerant) with ADC1_IN14 and SDIO1_CK listed as its alternate functions.
25 PC5 bidirectional GPIO PC5 (not 5 V tolerant) with ADC1_IN15 and SDIO1_CMD listed as its alternate functions.
26 PB0 bidirectional GPIO PB0 (not 5 V tolerant) with ADC1_IN8, I2S1_MCK and TMR3_CH3 functions; remap USART3_RTS and TMR1_CH2C.
27 PB1 bidirectional GPIO PB1 (not 5 V tolerant) with ADC1_IN9 and TMR3_CH4 functions; remap USART3_CTS and TMR1_CH3C.
28 PB2 / BOOT1 bidirectional GPIO PB2 (5 V tolerant, FT) that doubles as the BOOT1 boot-mode input; if unused, the datasheet recommends pulling PB2 down.
29 PB10 bidirectional GPIO PB10 (5 V tolerant, FT) with I2C2_SCL and USART3_TX functions; remap TMR2_CH3.
30 PB11 bidirectional GPIO PB11 (5 V tolerant, FT) with I2C2_SDA and USART3_RX functions; remap TMR2_CH4.
31 VSS power_in Digital ground; must be connected to the same ground potential as the other VSS pins.
32 VDD power_in Digital supply (2.6-3.6 V) for the GPIO pins and the internal LDO.
33 PB12 bidirectional GPIO PB12 (5 V tolerant, FT) with USART3_CK, I2C2_SMBA, SPI2_CS, I2S2_WS and TMR1_BRK functions.
34 PB13 bidirectional GPIO PB13 (5 V tolerant, FT) with TMR1_CH1C, USART3_CTS, SPI2_SCK and I2S2_CK functions.
35 PB14 bidirectional GPIO PB14 (5 V tolerant, FT) with TMR1_CH2C, USART3_RTS and SPI2_MISO functions; remap TMR9_CH1.
36 PB15 bidirectional GPIO PB15 (5 V tolerant, FT) with TMR1_CH3C, ERTC_REFIN, SPI2_MOSI and I2S2_SD functions; remap TMR9_CH2.
37 PC6 bidirectional GPIO PC6 (5 V tolerant, FT) with I2S2_MCK and SDIO1_D6 functions; remap TMR1_CH1 and TMR3_CH1.
38 PC7 bidirectional GPIO PC7 (5 V tolerant, FT) with SDIO1_D7 function; remap I2S2_MCK, TMR1_CH2 and TMR3_CH2.
39 PC8 bidirectional GPIO PC8 (5 V tolerant, FT) with SDIO1_D0 function; remap TMR1_CH3 and TMR3_CH3.
40 PC9 bidirectional GPIO PC9 (5 V tolerant, FT) with SDIO1_D1 function; remap I2C2_SDA, TMR1_CH4 and TMR3_CH4.
41 PA8 bidirectional GPIO PA8 (5 V tolerant, FT) with OTGFS1_SOF, CLKOUT, USART1_CK and TMR1_CH1 functions; remap I2C2_SCL.
42 PA9 bidirectional GPIO PA9 (5 V tolerant, FT) with OTGFS1_VBUS, USART1_TX and TMR1_CH2 functions; when OTGFS1 operates as a device, PA9 must stay high and cannot be used as GPIO or another function (not applicable from silicon revision C).
43 PA10 bidirectional GPIO PA10 (not 5 V tolerant) with OTGFS1_ID, USART1_RX and TMR1_CH3 functions.
44 PA11 bidirectional GPIO PA11 (not 5 V tolerant) with OTGFS1_D-, USART1_CTS, CAN1_RX and TMR1_CH4 functions; remap CMP1_OUT.
45 PA12 bidirectional GPIO PA12 (not 5 V tolerant) with OTGFS1_D+, USART1_RTS, CAN1_TX and TMR1_EXT functions; remap CMP2_OUT.
46 PA13 bidirectional GPIO PA13 (5 V tolerant, FT) with the JTMS-SWDIO debug function.
47 PF6 bidirectional GPIO PF6 (5 V tolerant, FT) with I2C1_SCL and I2C2_SCL functions.
48 PF7 bidirectional GPIO PF7 (5 V tolerant, FT) with I2C1_SDA and I2C2_SDA functions.
49 PA14 bidirectional GPIO PA14 (5 V tolerant, FT) with the JTCK-SWCLK debug function.
50 PA15 bidirectional GPIO PA15 (5 V tolerant, FT) with JTDI as default function; remap SPI1_CS, I2S1_WS, SPI2_CS, I2S2_WS, TMR2_CH1 and TMR2_EXT.
51 PC10 bidirectional GPIO PC10 (5 V tolerant, FT) with UART4_TX and SDIO1_D2 functions; remap USART3_TX.
52 PC11 bidirectional GPIO PC11 (5 V tolerant, FT) with UART4_RX and SDIO1_D3 functions; remap USART3_RX.
53 PC12 bidirectional GPIO PC12 (5 V tolerant, FT) with UART5_TX and SDIO1_CK functions; remap USART3_CK.
54 PD2 bidirectional GPIO PD2 (5 V tolerant, FT) with UART5_RX, SDIO1_CMD and TMR3_EXT functions.
55 PB3 bidirectional GPIO PB3 (5 V tolerant, FT) with the JTDO debug function as default; remap SWO, SPI1_SCK, I2S1_CK, SPI2_SCK, I2S2_CK and TMR2_CH2.
56 PB4 bidirectional GPIO PB4 (5 V tolerant, FT) with the NJTRST debug function as default; remap SPI1_MISO, SPI2_MISO, I2C2_SDA and TMR3_CH1.
57 PB5 bidirectional GPIO PB5 (5 V tolerant, FT) with I2C1_SMBA function; remap SPI1_MOSI, I2S1_SD, SPI2_MOSI, I2S2_SD and TMR3_CH2.
58 PB6 bidirectional GPIO PB6 (5 V tolerant, FT) with I2C1_SCL and TMR4_CH1 functions; remap USART1_TX and I2S1_MCK.
59 PB7 bidirectional GPIO PB7 (5 V tolerant, FT) with I2C1_SDA and TMR4_CH2 functions; remap USART1_RX.
60 BOOT0 input Boot mode selection input (together with BOOT1) sampled at startup; it has a weak pull-down that cannot be disabled.
61 PB8 bidirectional GPIO PB8 (5 V tolerant, FT) with SDIO1_D4, TMR4_CH3 and TMR10_CH1 functions; remap I2C1_SCL and CAN1_RX.
62 PB9 bidirectional GPIO PB9 (5 V tolerant, FT) with SDIO1_D5, TMR4_CH4 and TMR11_CH1 functions; remap I2C1_SDA and CAN1_TX.
63 VSS power_in Digital ground; must be connected to the same ground potential as the other VSS pins.
64 VDD power_in Digital supply (2.6-3.6 V) for the GPIO pins and the internal LDO.

Key specifications

Parameter Value
Manufacturer ARTERY
Package LQFP-64(10x10)
Category Embedded Processors & Controllers
Pins 64

Electrical characteristics

Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).

Parameter Symbol Min Typ Max Unit Conditions Page
外部主供电电压（包含VDDA和VDD） VDD-VSS -0.3 4 V 30
在5 V容忍的引脚上的输入电压 VIN 6 V 5 V tolerant pins; printed min is VSS-0.3 30
在其它引脚上的输入电压 VIN 4 V other pins; printed min is VSS-0.3 30
不同供电引脚之间的电压差 /ΔVDDx/ 50 mV 30
不同接地引脚之间的电压差 /VSSx-VSS/ 50 mV 30
经过VDD电源线的总电流（流入电流） IVDD 150 mA 30
经过VSS地线的总电流（流出电流） IVSS 150 mA 30
任意GPIO和控制引脚上的输出灌电流 IIO 25 mA 30
任意GPIO和控制引脚上的输出电流 -25 mA 30
储存温度范围 TSTG -60 150 °C 30
最大结温度 TJ 125 °C 30
数据传输模式下的时钟频率 fPP 0 48 MHz 55
时钟低时间 tW(CKL) 32 ns fPP = 16 MHz 55
时钟高时间 tW(CKH) 30 ns fPP = 16 MHz 55
时钟上升时间 tr 4 ns 55
时钟下降时间 tf 5 ns 55
输入有效时间 tISU 2 ns CMD、D输入（参照CK） 55
输入保持时间 tIH 0 ns CMD、D输入（参照CK） 55
输出有效时间 tOV 6 ns 在MMC和SD高速模式CMD、D输出（参照CK） 55
输出保持时间 tOH 0 ns 在MMC和SD高速模式CMD、D输出（参照CK） 55
输出有效默认时间 tOVD 7 ns 在SD默认模式CMD、D输出（参照CK） 55
输出保持默认时间 tOHD 0.5 ns 在SD默认模式CMD、D输出（参照CK） 55
OTGFS收发器启动时间 tSTARTUP 1 μs 56
OTGFS操作电压 VDD 3 3.6 V 56
差分输入灵敏度 VDI 0.2 V I（OTGFS_D+/D-） 56
差分共模范围 VCM 0.8 2.5 V 包含VDI范围 56
单端接收器阈值 VSE 1.3 2 V 56
静态输出低电平 VOL 0.3 V 1.24 kΩ的RL接至3.6 V 56
静态输出高电平 VOH 2.8 3.6 V 15 kΩ的RL接至VSS 56
OTGFS_D+内部上拉电阻 RPU 0.97 1.24 1.58 kΩ VIN = VSS 56
OTGFS_D+/D-内部下拉电阻 RPD 15 19 25 kΩ VIN = VDD 56
上升时间 tr 4 20 ns CL ≤ 50 pF 56
下降时间 tf 4 20 ns CL ≤ 50 pF 56
上升下降时间匹配 tr/tf trfm 90 110 % 56
输出信号交叉电压 VCRS 1.3 2 V 56
供电电压 VDDA 2.6 3.6 V 57
在VDDA输入脚上的电流 IDDA 560 660 μA 57
ADC时钟频率 fADC 0.6 28 MHz 57
采样速率 fS 0.05 2 MHz 57
外部触发频率 fTRIG 1.65 MHz fADC = 28 MHz 57
外部触发频率 fTRIG 17 1/fADC 57
转换电压范围 VAIN 0 V VREF-内部连接到地; max is VREF+ (symbolic, not numeric) 57
注入触发转换时延 tlat 107 ns fADC = 28 MHz 57
注入触发转换时延 tlat 3 1/fADC 57
常规触发转换时延 tlatr 71.4 ns fADC = 28 MHz 57
常规触发转换时延 tlatr 2 1/fADC 57
采样时间 tS 0.053 8.55 μs fADC = 28 MHz 57
采样时间 tS 1.5 239.5 1/fADC 57
总转换时间（包括采样时间） tCONV 0.5 9 μs fADC = 28 MHz 57
总转换时间（包括采样时间） tCONV 14 252 1/fADC 采样tS + 逐步逼近12.5 57

CAD (KiCad official)

  • Symbol: AT32F415RBT7
  • Footprint: Package_QFP:LQFP-64_10x10mm_P0.5mm
  • 3D model: LQFP-64(10x10) (KiCad packages3D, STEP)
  • 3D model files: at32f415rbt7-etched.step / at32f415rbt7-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); at32f415rbt7.step / at32f415rbt7.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: ARTERY datasheet (75 pp, sha256 7bd001051ee57bd1, retrieved 2026-10-18, tier: lcsc)
  • Datasheet language: Chinese. Pin names, descriptions, and specs on this page were extracted and translated to English by ds2sf; the linked PDF is the manufacturer original.
  • Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-haiku-5-5 (text), consensus claude-sonnet-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF