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AT32F415CCT7

Public Made by Adom

by adom

ARTERY Microcontroller Units (MCUs/MPUs/SOCs), LQFP-48(7x7). Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.

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AT32F415CCT7

ARTERY · Microcontroller Units (MCUs/MPUs/SOCs) · LQFP-48(7x7)

AT32F415CCT7 from ARTERY, in a LQFP-48(7x7). Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 VBAT power_in Battery backup supply input of 1.8 to 3.6 V that powers ERTC, LEXT and BPR when VDD is absent.
2 PC13 bidirectional GPIO PC13 (TAMPER-RTC) powered through a power switch that can source only 3 mA, so it must not drive current-source loads such as LEDs when used as output.
3 PC14 bidirectional GPIO PC14 (LEXT_IN) powered through a power switch limited to 3 mA source current, so it must not drive current-source loads when used as output.
4 PC15 bidirectional GPIO PC15 (LEXT_OUT) powered through a power switch limited to 3 mA source current, so it must not drive current-source loads when used as output.
5 PD0 bidirectional GPIO PD0 whose default function after reset is HEXT_IN for a 4 to 25 MHz crystal oscillator input, reconfigurable to PD0 by software.
6 PD1 bidirectional GPIO PD1 whose default function after reset is HEXT_OUT for a 4 to 25 MHz crystal oscillator output, reconfigurable to PD1 by software.
7 NRST bidirectional Active-low reset pin with internal pull-up RPU of 30 to 50 kOhm (typ. 40 kOhm); low level must last at least 66.7 us to be recognized as a valid reset.
8 VSSA/VREF- power_in Analog ground for ADC and CMP, which must be at the same potential as VSS.
9 VDDA/VREF+ power_in Analog supply of 2.6 to 3.6 V for ADC and CMP, which must be at the same potential as VDD.
10 PA0-WKUP bidirectional GPIO PA0 with WKUP wake-up input, where a rising edge exits standby mode, and ADC1_IN0 analog input.
11 PA1 bidirectional GPIO PA1 with ADC1_IN1 analog input, CMP1_INP1 comparator input and USART2_RTS function.
12 PA2 bidirectional GPIO PA2 that is not 5 V tolerant, with ADC1_IN2 analog input and USART2_TX (bootloader pin).
13 PA3 bidirectional GPIO PA3 that is not 5 V tolerant, with ADC1_IN3 analog input and USART2_RX (bootloader pin).
14 PA4 bidirectional GPIO PA4 that is not 5 V tolerant, with ADC1_IN4 analog input and SPI1_CS/I2S1_WS alternate functions.
15 PA5 bidirectional GPIO PA5 that is not 5 V tolerant, with ADC1_IN5 analog input and SPI1_SCK/I2S1_CK alternate functions.
16 PA6 bidirectional GPIO PA6 that is not 5 V tolerant, with ADC1_IN6 analog input and SPI1_MISO/TMR3_CH1 alternate functions.
17 PA7 bidirectional GPIO PA7 that is not 5 V tolerant, with ADC1_IN7 analog input and SPI1_MOSI/I2S1_SD alternate functions.
18 PB0 bidirectional GPIO PB0 that is not 5 V tolerant, with ADC1_IN8 analog input and I2S1_MCK/TMR3_CH3 alternate functions.
19 PB1 bidirectional GPIO PB1 that is not 5 V tolerant, with ADC1_IN9 analog input and TMR3_CH4/USART3_CTS alternate functions.
20 PB2 bidirectional 5 V tolerant GPIO PB2 that doubles as BOOT1; if unused, the datasheet recommends pulling it down.
21 PB10 bidirectional 5 V tolerant GPIO PB10 with I2C2_SCL and USART3_TX alternate functions.
22 PB11 bidirectional 5 V tolerant GPIO PB11 with I2C2_SDA and USART3_RX alternate functions.
23 VSS power_in Digital ground.
24 VDD power_in Digital supply of 2.6 to 3.6 V for GPIO pins and internal LDO.
25 PB12 bidirectional 5 V tolerant GPIO PB12 with SPI2_CS/I2S2_WS, USART3_CK and TMR1_BRK alternate functions.
26 PB13 bidirectional 5 V tolerant GPIO PB13 with SPI2_SCK/I2S2_CK, USART3_CTS and TMR1_CH1C alternate functions.
27 PB14 bidirectional 5 V tolerant GPIO PB14 with SPI2_MISO, USART3_RTS and TMR9_CH1 alternate functions.
28 PB15 bidirectional 5 V tolerant GPIO PB15 with SPI2_MOSI/I2S2_SD, ERTC_REFIN and TMR9_CH2 alternate functions.
29 PA8 bidirectional 5 V tolerant GPIO PA8 with OTGFS1_SOF, CLKOUT, USART1_CK, TMR1_CH1 and I2C2_SCL alternate functions.
30 PA9 bidirectional 5 V tolerant GPIO PA9 with USART1_TX and TMR1_CH2; when OTGFS1 is used as device it must stay high (exception from silicon revision C onward).
31 PA10 bidirectional GPIO PA10 that is not 5 V tolerant, with OTGFS1_ID, USART1_RX and TMR1_CH3 alternate functions.
32 PA11 bidirectional GPIO PA11 that is not 5 V tolerant, with OTGFS1_D-, USART1_CTS, CAN1_RX and TMR1_CH4 alternate functions.
33 PA12 bidirectional GPIO PA12 that is not 5 V tolerant, with OTGFS1_D+, USART1_RTS, CAN1_TX and TMR1_EXT alternate functions.
34 PA13 bidirectional 5 V tolerant GPIO PA13 that carries the JTMS/SWDIO debug function.
35 PF6 bidirectional 5 V tolerant GPIO PF6 with I2C1_SCL and I2C2_SCL alternate functions.
36 PF7 bidirectional 5 V tolerant GPIO PF7 with I2C1_SDA and I2C2_SDA alternate functions.
37 PA14 bidirectional 5 V tolerant GPIO PA14 that carries the JTCK/SWCLK debug function.
38 PA15 bidirectional 5 V tolerant GPIO PA15 with JTDI default function and SPI1_CS, I2S1_WS, SPI2_CS and TMR2_CH1 alternate functions.
39 PB3 bidirectional 5 V tolerant GPIO PB3 with JTDO/SWO default function and SPI1_SCK, I2S1_CK and TMR2_CH2 alternate functions.
40 PB4 bidirectional 5 V tolerant GPIO PB4 with NJTRST default function and SPI1_MISO, SPI2_MISO, I2C2_SDA and TMR3_CH1 alternate functions.
41 PB5 bidirectional 5 V tolerant GPIO PB5 with I2C1_SMBA and SPI1_MOSI/I2S1_SD, SPI2_MOSI and TMR3_CH2 alternate functions.
42 PB6 bidirectional 5 V tolerant GPIO PB6 with I2C1_SCL, TMR4_CH1, USART1_TX and I2S1_MCK alternate functions.
43 PB7 bidirectional 5 V tolerant GPIO PB7 with I2C1_SDA, TMR4_CH2 and USART1_RX alternate functions.
44 BOOT0 input Boot mode select input that sets the startup memory mapping; its weak pull-down cannot be disabled.
45 PB8 bidirectional 5 V tolerant GPIO PB8 with SDIO1_D4, TMR4_CH3, TMR10_CH1, I2C1_SCL and CAN1_RX alternate functions.
46 PB9 bidirectional 5 V tolerant GPIO PB9 with SDIO1_D5, TMR4_CH4, TMR11_CH1, I2C1_SDA and CAN1_TX alternate functions.
47 VSS power_in Digital ground.
48 VDD power_in Digital supply of 2.6 to 3.6 V for GPIO pins and internal LDO.

Key specifications

Parameter Value
Manufacturer ARTERY
Package LQFP-48(7x7)
Category Single Chip Microcomputer/Microcontroller
Pins 48

Electrical characteristics

Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).

Parameter Symbol Min Typ Max Unit Conditions Page
External main supply voltage (VDD-VSS, incl. VDDA and VDD) VDD-VSS -0.3 4 V 30
Input voltage on 5 V tolerant pins VIN 6 V min printed as VSS-0.3 30
Input voltage on other pins VIN 4 V min printed as VSS-0.3 30
Voltage difference between supply pins /ΔVDDx/ 50 mV 30
Voltage difference between ground pins /VSSx-VSS/ 50 mV 30
Total current through VDD supply line (inflow) IVDD 150 mA 30
Total current through VSS ground line (outflow) IVSS 150 mA 30
Output sink current on any GPIO and control pin IIO 25 mA 30
Output source current on any GPIO and control pin IIO -25 mA 30
Storage temperature range TSTG -60 150 °C 30
Maximum junction temperature TJ 125 °C 30
Supply voltage VDD 2.6 3.6 V 1
Operating temperature range -40 105 °C 1
ADC supply voltage VDDA 2.6 3.6 V 57
ADC current on VDDA input pin IDDA 560 660 μA 57
ADC clock frequency fADC 0.6 28 MHz 57
ADC sampling rate fS 0.05 2 MHz 57
External trigger frequency fTRIG 1.65 MHz fADC = 28 MHz 57
External trigger frequency fTRIG 17 1/fADC 57
Internal sampling and hold capacitance CADC 15 pF 57
ADC calibration time tCAL 6.14 μs fADC = 28 MHz 57
Injected trigger conversion latency tlat 107 ns fADC = 28 MHz 57
Regular trigger conversion latency tlatr 71.4 ns fADC = 28 MHz 57
ADC sampling time tS 0.053 8.55 μs fADC = 28 MHz 57
Total conversion time (including sampling time) tCONV 0.5 9 μs fADC = 28 MHz 57
OTGFS transceiver startup time tSTARTUP 1 μs 56
OTGFS operating voltage VDD 3 3.6 V 56
Differential input sensitivity VDI 0.2 V I(OTGFS_D+/D-) 56
Differential common mode range VCM 0.8 2.5 V includes VDI range 56
Single-ended receiver threshold VSE 1.3 2 V 56
Static output low level VOL 0.3 V 1.24 kΩ RL to 3.6 V 56
Static output high level VOH 2.8 3.6 V 15 kΩ RL to VSS 56
OTGFS_D+ internal pull-up resistance RPU 0.97 1.24 1.58 kΩ VIN = VSS 56
OTGFS_D+/D- internal pull-down resistance RPD 15 19 25 kΩ VIN = VDD 56
Rise time tr 4 20 ns CL ≤ 50 pF 56
Fall time tf 4 20 ns CL ≤ 50 pF 56
Rise/fall time matching trfm 90 110 % tr/tf 56
Output signal crossover voltage VCRS 1.3 2 V 56
SD/MMC clock frequency in data transfer mode fPP 0 48 MHz 55
Clock low time tW(CKL) 32 ns fPP = 16 MHz 55
Clock high time tW(CKH) 30 ns fPP = 16 MHz 55
Clock rise time tr 4 ns 55
Clock fall time tf 5 ns 55
CMD, D input valid time tISU 2 ns referenced to CK 55
CMD, D input hold time tIH 0 ns referenced to CK 55
CMD, D output valid time (MMC and SD high-speed mode) tOV 6 ns referenced to CK 55
CMD, D output hold time (MMC and SD high-speed mode) tOH 0 ns referenced to CK 55
CMD, D output valid default time (SD default mode) tOVD 7 ns referenced to CK 55
CMD, D output hold default time (SD default mode) tOHD 0.5 ns referenced to CK 55

CAD (KiCad official)

  • Symbol: AT32F415CCT7
  • Footprint: Package_QFP:LQFP-48_7x7mm_P0.5mm
  • 3D model: LQFP-48(7x7) (KiCad packages3D, STEP)
  • 3D model files: at32f415cct7-etched.step / at32f415cct7-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); at32f415cct7.step / at32f415cct7.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: ARTERY datasheet (75 pp, sha256 7bd001051ee57bd1, retrieved 2026-10-28, tier: lcsc)
  • Datasheet language: Chinese. Pin names, descriptions, and specs on this page were extracted and translated to English by ds2sf; the linked PDF is the manufacturer original.
  • Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-haiku-5-5 (text), consensus claude-sonnet-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF