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AT32F413RCT7

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ARTERY Microcontrollers (MCU/MPU/SOC), LQFP-64(10x10). Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.

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AT32F413RCT7

ARTERY · Microcontrollers (MCU/MPU/SOC) · LQFP-64(10x10)

AT32F413RCT7 from ARTERY, in a LQFP-64(10x10). Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 VBAT power_in Backup-domain supply, 1.8 to 3.6 V, that powers the RTC, the external 32 kHz oscillator and the backup registers when VDD is off.
2 PC13 bidirectional General-purpose I/O also used as TAMPER-RTC; powered through a power switch limited to about 3 mA, so as an output it may only use medium drive, max 30 pF load, and must not source LED current; 5 V tolerant.
3 PC14 bidirectional General-purpose I/O also used as OSC32_IN for the 32.768 kHz LSE crystal; same 3 mA backup-switch output limits as PC13; 5 V tolerant.
4 PC15 bidirectional General-purpose I/O also used as OSC32_OUT for the LSE crystal; same 3 mA backup-switch output limits as PC13; 5 V tolerant.
5 PD0 bidirectional Reset default is OSC_IN (HSE 4 to 25 MHz oscillator input); software can reconfigure it as GPIO PD0; standard (not 5 V tolerant) I/O.
6 PD1 bidirectional Reset default is OSC_OUT (HSE oscillator output); software can reconfigure it as GPIO PD1; standard (not 5 V tolerant) I/O.
7 NRST bidirectional Active-low reset pin with an internal pull-up of 30 to 50 kΩ; input low must be at or below 0.8 V and input high at or above 2 V, and pulses shorter than 25 µs are filtered.
8 PC0 bidirectional General-purpose I/O with alternate functions ADC12_IN10 and SDIO_D0.
9 PC1 bidirectional General-purpose I/O with alternate functions ADC12_IN11 and SDIO_D1.
10 PC2 bidirectional General-purpose I/O with alternate functions ADC12_IN12 and SDIO_D2.
11 PC3 bidirectional General-purpose I/O with alternate functions ADC12_IN13 and SDIO_D3.
12 VSSA power_in Analog ground for the ADC and must be connected to VSS.
13 VDDA power_in Analog supply for the ADC, 2.6 to 3.6 V, which must be connected to VDD (up to 300 mV difference allowed).
14 PA0-WKUP bidirectional General-purpose I/O with ADC12_IN0, TMR2/TMR5/TMR8 timer and USART2_CTS alternate functions, and the WKUP wake-up input for standby mode (rising edge).
15 PA1 bidirectional General-purpose I/O with alternate functions ADC12_IN1, TMR2_CH2, TMR5_CH2 and USART2_RTS.
16 PA2 bidirectional General-purpose I/O with alternate functions ADC12_IN2, TMR2_CH3, TMR5_CH3, TMR9_CH1 and USART2_TX; remap SDIO_CK.
17 PA3 bidirectional General-purpose I/O with alternate functions ADC12_IN3, TMR2_CH4, TMR5_CH4, TMR9_CH2 and USART2_RX; remap SDIO_CMD.
18 PF4 bidirectional 5 V tolerant general-purpose I/O with alternate functions UART4_TX and TMR5_CH1.
19 PF5 bidirectional 5 V tolerant general-purpose I/O with alternate functions UART4_RX and TMR5_CH2.
20 PA4 bidirectional General-purpose I/O with alternate functions ADC12_IN4, USART2_CK, SPI1_NSS and I2S1_WS; remap SDIO_D4/SDIO_D0.
21 PA5 bidirectional General-purpose I/O with alternate functions ADC12_IN5, SPI1_SCK and I2S1_CK; remap SDIO_D5/SDIO_D1.
22 PA6 bidirectional General-purpose I/O with alternate functions ADC12_IN6, TMR3_CH1, SPI1_MISO and TMR8_BKIN; remap SDIO_D6/SDIO_D2, TMR1_BKIN, TMR10_CH1.
23 PA7 bidirectional General-purpose I/O with alternate functions ADC12_IN7, TMR3_CH2, TMR8_CH1N, SPI1_MOSI and I2S1_SD; remap SDIO_D7/SDIO_D3, TMR1_CH1N, TMR11_CH1.
24 PC4 bidirectional General-purpose I/O with alternate functions ADC12_IN14 and SDIO_CK.
25 PC5 bidirectional General-purpose I/O with alternate functions ADC12_IN15 and SDIO_CMD.
26 PB0 bidirectional General-purpose I/O with alternate functions ADC12_IN8, TMR3_CH3, TMR8_CH2N and I2S1_MCK; remap TMR1_CH2N.
27 PB1 bidirectional General-purpose I/O with alternate functions ADC12_IN9, TMR3_CH4, TMR8_CH3N and SPIM_SCK; remap TMR1_CH3N.
28 PB2/BOOT1 bidirectional 5 V tolerant general-purpose I/O that also latches the BOOT1 boot-mode selection at startup.
29 PB10 bidirectional 5 V tolerant general-purpose I/O with alternate functions I2C2_SCL and USART3_TX; remap TMR2_CH3 and SPIM_IO0.
30 PB11 bidirectional 5 V tolerant general-purpose I/O with alternate functions I2C2_SDA and USART3_RX; remap TMR2_CH4 and SPIM_IO1.
31 VSS power_in Digital ground.
32 VDD power_in Digital supply for I/O pins and the internal regulator, 2.6 to 3.6 V.
33 PB12 bidirectional 5 V tolerant general-purpose I/O with alternate functions USART3_CK, I2C2_SMBA, SPI2_NSS, I2S2_WS, TMR1_BKIN and CAN2_RX.
34 PB13 bidirectional 5 V tolerant general-purpose I/O with alternate functions TMR1_CH1N, SPI2_SCK, I2S2_CK, USART3_CTS and CAN2_TX.
35 PB14 bidirectional 5 V tolerant general-purpose I/O with alternate functions TMR1_CH2N, USART3_RTS and SPI2_MISO; remap TMR9_CH1.
36 PB15 bidirectional 5 V tolerant general-purpose I/O with alternate functions TMR1_CH3N, SPI2_MOSI and I2S2_SD; remap TMR9_CH2.
37 PC6 bidirectional 5 V tolerant general-purpose I/O with alternate functions TMR8_CH1, I2S2_MCK and SDIO_D6; remap TMR3_CH1.
38 PC7 bidirectional 5 V tolerant general-purpose I/O with alternate functions TMR8_CH2 and SDIO_D7; remap TMR3_CH2 and I2S2_MCK.
39 PC8 bidirectional 5 V tolerant general-purpose I/O with alternate functions TMR8_CH3 and SDIO_D0; remap TMR3_CH3.
40 PC9 bidirectional 5 V tolerant general-purpose I/O with alternate functions TMR8_CH4 and SDIO_D1; remap TMR3_CH4 and I2C2_SDA.
41 PA8 bidirectional 5 V tolerant general-purpose I/O with alternate functions TMR1_CH1, CLKOUT, USART1_CK and SPIM_NSS; remap I2C2_SCL.
42 PA9 bidirectional 5 V tolerant general-purpose I/O with alternate functions TMR1_CH2 and USART1_TX (bootloader pin); remap I2C2_SMBA.
43 PA10 bidirectional 5 V tolerant general-purpose I/O with alternate functions TMR1_CH3 and USART1_RX (bootloader pin).
44 PA11 bidirectional Standard (not 5 V tolerant) I/O with alternate functions USB_DM, TMR1_CH4, SPIM_IO0, USART1_CTS and CAN1_RX; it has an extra non-disablable 330 kΩ pull-down.
45 PA12 bidirectional Standard (not 5 V tolerant) I/O with alternate functions USB_DP, CAN1_TX, USART1_RTS, SPIM_IO1 and TMR1_ETR; it has an extra non-disablable 330 kΩ pull-down.
46 PA13 bidirectional 5 V tolerant I/O that serves as the JTMS-SWDIO serial-wire debug data pin by default.
47 PF6 bidirectional 5 V tolerant general-purpose I/O with alternate functions I2C1_SCL and I2C2_SCL.
48 PF7 bidirectional 5 V tolerant general-purpose I/O with alternate functions I2C1_SDA and I2C2_SDA.
49 PA14 bidirectional 5 V tolerant I/O that serves as the JTCK-SWCLK serial-wire debug clock pin by default.
50 PA15 bidirectional 5 V tolerant I/O with JTDI by default and alternate functions TMR2_CH1, TMR2_ETR, SPI1_NSS, I2S1_WS, SPI2_NSS and I2S2_WS.
51 PC10 bidirectional 5 V tolerant general-purpose I/O with alternate functions UART4_TX and SDIO_D2; remap USART3_TX.
52 PC11 bidirectional 5 V tolerant general-purpose I/O with alternate functions UART4_RX and SDIO_D3; remap USART3_RX.
53 PC12 bidirectional 5 V tolerant general-purpose I/O with alternate functions UART5_TX and SDIO_CK; remap USART3_CK.
54 PD2 bidirectional 5 V tolerant general-purpose I/O with alternate functions UART5_RX, SDIO_CMD and TMR3_ETR.
55 PB3 bidirectional 5 V tolerant I/O that serves as JTDO by default, with alternate functions TRACESWO, TMR2_CH2, SPI1_SCK, I2S1_CK, SPI2_SCK and I2S2_CK.
56 PB4 bidirectional 5 V tolerant I/O that serves as NJTRST by default, with alternate functions TMR3_CH1, SPI1_MISO, SPI2_MISO and I2C2_SDA.
57 PB5 bidirectional Standard (not 5 V tolerant) general-purpose I/O with alternate functions I2C1_SMBA, TMR3_CH2, SPI1_MOSI, I2S1_SD, SPI2_MOSI, I2S2_SD and CAN2_RX.
58 PB6 bidirectional 5 V tolerant general-purpose I/O with alternate functions TMR4_CH1, I2C1_SCL and SPIM_IO3; remap USART1_TX, CAN2_TX and I2S1_MCK.
59 PB7 bidirectional 5 V tolerant general-purpose I/O with alternate functions TMR4_CH2, I2C1_SDA and SPIM_IO2; remap USART1_RX.
60 BOOT0 input Boot-mode selection input sampled at startup; its weak pull-down cannot be disabled.
61 PB8 bidirectional 5 V tolerant general-purpose I/O with alternate functions TMR4_CH3, TMR10_CH1 and SDIO_D4; remap I2C1_SCL and CAN1_RX.
62 PB9 bidirectional 5 V tolerant general-purpose I/O with alternate functions TMR4_CH4, TMR11_CH1 and SDIO_D5; remap I2C1_SDA and CAN1_TX.
63 VSS power_in Digital ground.
64 VDD power_in Digital supply for I/O pins and the internal regulator, 2.6 to 3.6 V.

Key specifications

Parameter Value
Manufacturer ARTERY
Package LQFP-64(10x10)
Category Embedded Processors & Controllers
Pins 64

Electrical characteristics

Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).

Parameter Symbol Min Typ Max Unit Conditions Page
数据传输模式下的时钟频率 fPP 0 48 MHz CL ≤ 30 pF 62
时钟低时间 tW(CKL) 32 ns CL ≤ 30 pF 62
时钟高时间 tW(CKH) 30 ns CL ≤ 30 pF 62
时钟上升时间 tr 4 ns CL ≤ 30 pF 62
时钟下降时间 tf 5 ns CL ≤ 30 pF 62
CMD、D输入建立时间 (printed label: 时钟上升时间) tISU 2 ns CL ≤ 30 pF 62
CMD、D输入保持时间 (printed label: 时钟下降时间) tIH 0 ns CL ≤ 30 pF 62
输出有效时间 (MMC和SD高速模式CMD、D输出) tOV 6 ns CL ≤ 30 pF 62
输出保持时间 (MMC和SD高速模式CMD、D输出) tOH 0 ns CL ≤ 30 pF 62
输出有效默认时间 (SD默认模式CMD、D输出) tOVD 7 ns CL ≤ 30 pF 62
输出保持默认时间 (SD默认模式CMD、D输出) tOHD 0.5 ns CL ≤ 30 pF 62
USB收发器启动时间 tSTARTUP 1 μs 63
USB操作电压 VDD 3 3.6 V 63
差分输入灵敏度 VDI 0.2 V I (USB_DP，USB_DM) 63
差分共模范围 VCM 0.8 2.5 V 包含VDI范围 63
单端接收器阀值 VSE 1.3 2 V 63
静态输出低电平 VOL 0.3 V 内部1.24 kΩ的RL接至3.6 V 63
静态输出高电平 VOH 2.8 3.6 V 15 kΩ的RL接至VSS 63
USB_DP内部上拉电阻 RPU 0.97 1.24 1.58 kΩ VIN = VSS 63
上升时间 tr 4 20 ns CL ≤ 50 pF 63
下降时间 tf 4 20 ns CL ≤ 50 pF 63
上升下降时间匹配 trfm 90 110 % 63
输出信号交叉电压 VCRS 1.3 2 V 63
供电电压 VDDA 2.6 3.6 V 64
ADC时钟频率 fADC 0.6 28 MHz 64
采样速率 fS 0.05 2 MHz 64
外部触发频率 fTRIG 1.65 MHz fADC = 28 MHz 64
外部触发频率 fTRIG 17 1/fADC 64
转换电压范围 VAIN 0 V VREF-内部连接到地; max = VREF+ (symbolic, not numeric) 64
注入触发转换时延 tlat 107 ns fADC = 28 MHz 64
注入触发转换时延 tlat 3 1/fADC 64
常规触发转换时延 tlatr 71.4 μs fADC = 28 MHz 64
常规触发转换时延 tlatr 2 1/fADC 64
采样时间 tS 0.053 8.55 μs fADC = 28 MHz 64
采样时间 tS 1.5 239.5 1/fADC 64
总转换时间 (包括采样时间) tCONV 0.5 9 μs fADC = 28 MHz 64
总转换时间 (包括采样时间) tCONV 14 252 1/fADC 采样tS + 逐步逼近12.5 (printed as 14~252) 64
内部采样和保持电容 CADC 15 pF 64

CAD (KiCad official)

  • Symbol: AT32F413RCT7
  • Footprint: Package_QFP:LQFP-64_10x10mm_P0.5mm
  • 3D model: LQFP-64(10x10) (KiCad packages3D, STEP)
  • 3D model files: at32f413rct7-etched.step / at32f413rct7-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); at32f413rct7.step / at32f413rct7.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: ARTERY datasheet (79 pp, sha256 9bb4b2403763a132, retrieved 2026-10-18, tier: lcsc)
  • Datasheet language: Chinese. Pin names, descriptions, and specs on this page were extracted and translated to English by ds2sf; the linked PDF is the manufacturer original.
  • Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-haiku-5-5 (text), consensus claude-sonnet-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF