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AT32F413CCU7

Public Made by Adom

by adom

ARTERY Microcontroller Units (MCUs/MPUs/SOCs), QFN-48-EP(6x6). Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.

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AT32F413CCU7

ARTERY · Microcontroller Units (MCUs/MPUs/SOCs) · QFN-48-EP(6x6)

AT32F413CCU7 from ARTERY, in a QFN-48-EP(6x6). Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 VBAT power_in Battery supply of 1.8 to 3.6 V for the RTC, LEXT and backup registers, used when VDD is absent.
2 PC13/TAMPER-RTC bidirectional PC13 I/O with TAMPER-RTC function, supplied through a power switch limited to 3 mA, so it cannot source current such as an LED when used as output.
3 PC14/LEXT_IN bidirectional PC14 I/O with LEXT_IN function, supplied through a power switch limited to 3 mA, so it cannot source current when used as output.
4 PC15/LEXT_OUT bidirectional PC15 I/O with LEXT_OUT function, supplied through a power switch limited to 3 mA, so it cannot source current when used as output.
5 PD0/HEXT_IN bidirectional PD0 defaults to HEXT_IN (4 to 25 MHz crystal input) after reset and can be reconfigured as PD0 GPIO; not 5 V tolerant.
6 PD1/HEXT_OUT bidirectional PD1 defaults to HEXT_OUT (crystal output) after reset and can be reconfigured as PD1 GPIO; not 5 V tolerant.
7 NRST input Active-low reset input with internal pull-up of 30 to 50 kOhm (typ. 40 kOhm); VIL maximum 0.8 V.
8 VSSA/VREF- power_in Analog ground, which must be at the same potential as VSS; negative ADC reference.
9 VDDA/VREF+ power_in Analog supply of 2.6 to 3.6 V for the ADC, which must be at the same potential as VDD; positive ADC reference.
10 PA0/WKUP bidirectional PA0 with ADC12_IN0 analog input and WKUP wake-up function; not 5 V tolerant.
11 PA1 bidirectional PA1 with ADC12_IN1 analog input and USART2_RTS alternate function; not 5 V tolerant.
12 PA2 bidirectional PA2 with ADC12_IN2 analog input and USART2_TX alternate function; not 5 V tolerant.
13 PA3 bidirectional PA3 with ADC12_IN3 analog input and USART2_RX alternate function; not 5 V tolerant.
14 PA4 bidirectional PA4 with ADC12_IN4 analog input and USART2_CK/SPI1_CS alternate functions; not 5 V tolerant.
15 PA5 bidirectional PA5 with ADC12_IN5 analog input and SPI1_SCK alternate function; not 5 V tolerant.
16 PA6 bidirectional PA6 with ADC12_IN6 analog input and SPI1_MISO alternate function; not 5 V tolerant.
17 PA7 bidirectional PA7 with ADC12_IN7 analog input and SPI1_MOSI alternate function; not 5 V tolerant.
18 PB0 bidirectional PB0 with ADC12_IN8 analog input and I2S1_MCK alternate function; not 5 V tolerant.
19 PB1 bidirectional PB1 with ADC12_IN9 analog input and SPIM_SCK alternate function; not 5 V tolerant.
20 PB2/BOOT1 bidirectional PB2 is 5 V tolerant and doubles as BOOT1; if booting from internal flash and PB2 is unused, pull-down to ground is recommended.
21 PB10 bidirectional PB10 is 5 V tolerant with I2C2_SCL and USART3_TX alternate functions.
22 PB11 bidirectional PB11 is 5 V tolerant with I2C2_SDA and USART3_RX alternate functions.
23 VSS power_in Ground pin, connected to the board ground.
24 VDD power_in Digital supply of 2.6 to 3.6 V for the GPIO pins and the internal regulator (LDO).
25 PB12 bidirectional PB12 is 5 V tolerant with SPI2_CS, I2S2_WS, CAN2_RX and USART3_CK alternate functions.
26 PB13 bidirectional PB13 is 5 V tolerant with SPI2_SCK, I2S2_CK and CAN2_TX alternate functions.
27 PB14 bidirectional PB14 is 5 V tolerant with USART3_RTS and SPI2_MISO alternate functions.
28 PB15 bidirectional PB15 is 5 V tolerant with SPI2_MOSI and I2S2_SD alternate functions.
29 PA8 bidirectional PA8 is 5 V tolerant with CLKOUT, USART1_CK, USBFS1_SOF and TMR1_CH1 alternate functions.
30 PA9 bidirectional PA9 is 5 V tolerant with USART1_TX and TMR1_CH2 alternate functions and is used for boot loader USART1 communication.
31 PA10 bidirectional PA10 is 5 V tolerant with USART1_RX and TMR1_CH3 alternate functions.
32 PA11 bidirectional PA11 is not 5 V tolerant, with USBFS1_D- and CAN1_RX alternate functions, and has an extra non-disableable 330 kOhm weak pull-down.
33 PA12 bidirectional PA12 is not 5 V tolerant, with USBFS1_D+ and CAN1_TX alternate functions, and has an extra non-disableable 330 kOhm weak pull-down.
34 PA13 bidirectional PA13 is 5 V tolerant and carries the JTMS-SWDIO debug function.
35 PF6 bidirectional PF6 is 5 V tolerant with I2C1_SCL and I2C2_SCL alternate functions.
36 PF7 bidirectional PF7 is 5 V tolerant with I2C1_SDA and I2C2_SDA alternate functions.
37 PA14 bidirectional PA14 is 5 V tolerant and carries the JTCK-SWCLK debug function.
38 PA15 bidirectional PA15 is 5 V tolerant with JTDI debug function and SPI1_CS, I2S1_WS, SPI2_CS, I2S2_WS and TMR2_CH1 alternate functions.
39 PB3 bidirectional PB3 is 5 V tolerant and carries the JTDO function with SWO, SPI1_SCK and I2S1_CK alternate functions.
40 PB4 bidirectional PB4 is 5 V tolerant and carries the NJTRST function with SPI1_MISO and I2C2_SDA alternate functions.
41 PB5 bidirectional PB5 is 5 V tolerant with I2C1_SMBA, SPI1_MOSI, I2S1_SD and CAN2_RX alternate functions.
42 PB6 bidirectional PB6 is 5 V tolerant with I2C1_SCL, USART1_TX, CAN2_TX and I2S1_MCK alternate functions.
43 PB7 bidirectional PB7 is 5 V tolerant with I2C1_SDA and USART1_RX alternate functions.
44 BOOT0 input Boot mode selection input with a weak pull-down that cannot be disabled; not 5 V tolerant.
45 PB8 bidirectional PB8 is 5 V tolerant with TMR10_CH1, SDIO1_D4, I2C1_SCL and CAN1_RX alternate functions.
46 PB9 bidirectional PB9 is 5 V tolerant with TMR11_CH1, SDIO1_D5, I2C1_SDA and CAN1_TX alternate functions.
47 VSS power_in Ground pin, connected to the board ground.
48 VDD power_in Digital supply of 2.6 to 3.6 V for the GPIO pins and the internal regulator (LDO).
49 EPAD power_in Exposed thermal pad, internally connected to VSS.

Key specifications

Parameter Value
Manufacturer ARTERY
Package QFN-48-EP(6x6)
Category Single Chip Microcomputer/Microcontroller
Pins 49

Electrical characteristics

Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).

Parameter Symbol Min Typ Max Unit Conditions Page
Supply voltage range VDD 2.6 3.6 V Power supply, per features list 1
Operating temperature range -40 105 °C Temperature range, per features list 1
External supply voltage (VDD-VSS) VDD-VSS -0.3 4 V Including VDDA and VDD 28
Input voltage on FT pins VIN 6 V Min printed as VSS-0.3; FT pins 28
Input voltage on other pins VIN 4 V Min printed as VSS-0.3; other pins 28
Voltage difference between supply pins /ΔVDDx/ 50 mV Between different supply pins 28
Voltage difference between ground pins /VSSx-VSS/ 50 mV Between different ground pins 28
Total current through VDD line IVDD 150 mA Inflow current 28
Total current through VSS line IVSS 150 mA Outflow current 28
Output sink current on any GPIO and control pin IIO 25 mA Sink current 28
Output source current on any GPIO and control pin IIO -25 mA Output current 28
Storage temperature range TSTG -60 150 °C Storage temperature 28
Maximum junction temperature TJ 125 °C Maximum junction temperature 28
HICK accuracy at 25 °C -1 1 % 48 MHz HICK, 25 °C, factory-trimmed 1
HICK accuracy over temperature -2.5 2.5 % 48 MHz HICK, -40 °C to +105 °C 1
SDIO data transfer clock frequency fPP 0 48 MHz Data transfer mode 52
SDIO clock low time tW(CKL) 32 ns - 52
SDIO clock high time tW(CKH) 30 ns - 52
SDIO clock rise time tr 4 ns - 52
SDIO clock fall time tf 5 ns - 52
CMD/D input clock setup time tISU 2 ns - 52
CMD/D input clock hold time tIH 0 ns - 52
CMD/D output valid time (MMC and SD high speed) tOV 6 ns Referenced to CK 52
CMD/D output hold time (MMC and SD high speed) tOH 0 ns Referenced to CK 52
CMD/D output valid default time (SD default mode) tOVD 7 ns Referenced to CK; see SDIO_CLKCTRL 52
CMD/D output hold default time (SD default mode) tOHD 0.5 ns Referenced to CK; see SDIO_CLKCTRL 52
USBFS transceiver startup time tSTARTUP 1 μs Guaranteed by design 53
USBFS operating voltage VDD 3 3.6 V USBFS operating voltage 53
USBFS differential input sensitivity VDI 0.2 V USBFS_D+, USBFS_D- 53
USBFS differential common-mode range VCM 0.8 2.5 V Includes VDI range 53
USBFS single-ended receiver threshold VSE 1.3 2 V - 53
USBFS static output low level VOL 0.3 V 1.24 kΩ RL to 3.6 V 53
USBFS static output high level VOH 2.8 3.6 V 15 kΩ RL to VSS 53
USBFS_D+ internal pull-up resistor RPU 0.97 1.24 1.58 kΩ VIN = VSS 53
USBFS rise time tr 4 20 ns CL ≤ 50 pF 53
USBFS fall time tf 4 20 ns CL ≤ 50 pF 53
USBFS rise/fall time matching trfm 90 110 % tr/tf 53
USBFS output signal crossover voltage VCRS 1.3 2 V - 53
ADC supply voltage VDDA 2.6 3.6 V - 54
ADC current on VDDA input pin IDDA 900 μA - 54
ADC clock frequency fADC 0.6 28 MHz - 54
ADC sampling rate fS 0.05 2 MSPS - 54
ADC external trigger frequency fTRIG 1.65 MHz fADC = 28 MHz 54
ADC conversion voltage range VAIN 0 V Max is VREF+ (internally connected to ground on low side) 54
ADC internal sampling and hold capacitance CADC 15 pF - 54
ADC preempted trigger conversion latency tlat 107 ns fADC = 28 MHz 54
ADC regular trigger conversion latency tlatr 71.4 ns fADC = 28 MHz 54
ADC sampling time tS 0.053 8.55 μs fADC = 28 MHz 54
ADC total conversion time tCONV 0.5 9 μs fADC = 28 MHz, including sampling time 54

CAD (KiCad official)

  • Symbol: AT32F413CCU7
  • Footprint: Package_DFN_QFN:QFN-48-1EP_6x6mm_P0.4mm_EP4.2x4.2mm
  • 3D model: QFN-48-EP(6x6) (KiCad packages3D, STEP)
  • 3D model files: at32f413ccu7-etched.step / at32f413ccu7-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); at32f413ccu7.step / at32f413ccu7.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: ARTERY datasheet (70 pp, sha256 e147658295e71a3a, retrieved 2026-10-28, tier: lcsc)
  • Datasheet language: Chinese. Pin names, descriptions, and specs on this page were extracted and translated to English by ds2sf; the linked PDF is the manufacturer original.
  • Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-haiku-5-5 (text), consensus claude-sonnet-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF