component
AT32F413CBT7
Public Made by Adomby adom
ARTERY Microcontrollers (MCU/MPU/SOC), LQFP-48(7x7). Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.
3D Model
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Symbol & Footprint
Schematic Symbol
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PCB Footprint
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Datasheet
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README
markdownAT32F413CBT7
ARTERY · Microcontrollers (MCU/MPU/SOC) · LQFP-48(7x7)
AT32F413CBT7 from ARTERY, in a LQFP-48(7x7). Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.
Pinout
| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | VBAT | power_in | Backup-domain supply for the RTC, LSE oscillator and backup registers, 1.8 to 3.6 V, used when VDD is off. |
| 2 | PC13 | bidirectional | GPIO PC13, not 5 V tolerant, also TAMPER-RTC; it is fed from a power switch limited to 3 mA, so as an output it is moderate drive only, 30 pF maximum load, and cannot source current to LEDs. |
| 3 | PC14 | bidirectional | GPIO PC14, not 5 V tolerant, also OSC32_IN; it is fed from the same 3 mA backup power switch, so as an output it is moderate drive only, 30 pF maximum load, and cannot act as a current source. |
| 4 | PC15 | bidirectional | GPIO PC15, not 5 V tolerant, also OSC32_OUT; it is fed from the same 3 mA backup power switch, so as an output it is moderate drive only, 30 pF maximum load, and cannot act as a current source. |
| 5 | PD0 | bidirectional | PD0 defaults to OSC_IN (HSE 4 to 25 MHz oscillator input) after reset and can be reassigned to the PD0 GPIO function by software; not 5 V tolerant. |
| 6 | PD1 | bidirectional | PD1 defaults to OSC_OUT (HSE oscillator output) after reset and can be reassigned to the PD1 GPIO function by software; not 5 V tolerant. |
| 7 | NRST | input | Active-low reset input with internal pull-up (RPU 30 to 50 kΩ); the input must be pulled below VIL(NRST) max 0.8 V for the MCU to reset. |
| 8 | VSSA | power_in | Analog ground for the ADC and temperature sensor; must be connected to VSS. |
| 9 | VDDA | power_in | Analog supply for the ADC and temperature sensor, 2.6 to 3.6 V; must be connected to VDD (up to 300 mV difference allowed during power-up and operation). |
| 10 | PA0-WKUP | bidirectional | GPIO PA0, not 5 V tolerant; alternate functions ADC12_IN0, TMR2_CH1/TMR2_ETR, TMR5_CH1, WKUP wake-up input, USART2_CTS and TMR8_ETR. |
| 11 | PA1 | bidirectional | GPIO PA1, not 5 V tolerant; alternate functions ADC12_IN1, TMR2_CH2, TMR5_CH2 and USART2_RTS. |
| 12 | PA2 | bidirectional | GPIO PA2, not 5 V tolerant (also USART2_TX, the bootloader pin); alternate functions ADC12_IN2, TMR2_CH3, TMR5_CH3, TMR9_CH1 and SDIO_CK. |
| 13 | PA3 | bidirectional | GPIO PA3, not 5 V tolerant (also USART2_RX, the bootloader pin); alternate functions ADC12_IN3, TMR2_CH4, TMR5_CH4, TMR9_CH2 and SDIO_CMD. |
| 14 | PA4 | bidirectional | GPIO PA4, not 5 V tolerant; alternate functions ADC12_IN4, USART2_CK, SPI1_NSS, I2S1_WS, SDIO_D4 and SDIO_D0. |
| 15 | PA5 | bidirectional | GPIO PA5, not 5 V tolerant; alternate functions ADC12_IN5, SPI1_SCK, I2S1_CK, SDIO_D5 and SDIO_D1. |
| 16 | PA6 | bidirectional | GPIO PA6, not 5 V tolerant; alternate functions ADC12_IN6, TMR3_CH1, SPI1_MISO and TMR8_BKIN, with remaps SDIO_D6/SDIO_D2, TMR1_BKIN and TMR10_CH1. |
| 17 | PA7 | bidirectional | GPIO PA7, not 5 V tolerant; alternate functions ADC12_IN7, TMR3_CH2, TMR8_CH1N, SPI1_MOSI and I2S1_SD, with remaps SDIO_D7/SDIO_D3, TMR1_CH1N and TMR11_CH1. |
| 18 | PB0 | bidirectional | GPIO PB0, not 5 V tolerant; alternate functions ADC12_IN8, TMR3_CH3, TMR8_CH2N and I2S1_MCK, with remap TMR1_CH2N. |
| 19 | PB1 | bidirectional | GPIO PB1, not 5 V tolerant; alternate functions ADC12_IN9, TMR3_CH4, TMR8_CH3N and SPIM_SCK, with remap TMR1_CH3N. |
| 20 | PB2/BOOT1 | bidirectional | GPIO PB2, 5 V tolerant, also used as the BOOT1 boot-configuration pin. |
| 21 | PB10 | bidirectional | GPIO PB10, 5 V tolerant; alternate functions I2C2_SCL and USART3_TX, with remaps TMR2_CH3 and SPIM_IO0. |
| 22 | PB11 | bidirectional | GPIO PB11, 5 V tolerant; alternate functions I2C2_SDA and USART3_RX, with remaps TMR2_CH4 and SPIM_IO1. |
| 23 | VSS | power_in | Ground reference for the digital I/O and core logic. |
| 24 | VDD | power_in | Supply for the I/O pins and internal regulator, 2.6 to 3.6 V. |
| 25 | PB12 | bidirectional | GPIO PB12, 5 V tolerant; alternate functions USART3_CK, I2C2_SMBA, SPI2_NSS, I2S2_WS, TMR1_BKIN and CAN2_RX. |
| 26 | PB13 | bidirectional | GPIO PB13, 5 V tolerant; alternate functions TMR1_CH1N, SPI2_SCK, I2S2_CK, USART3_CTS and CAN2_TX. |
| 27 | PB14 | bidirectional | GPIO PB14, 5 V tolerant; alternate functions TMR1_CH2N, USART3_RTS and SPI2_MISO, with remap TMR9_CH1. |
| 28 | PB15 | bidirectional | GPIO PB15, 5 V tolerant; alternate functions TMR1_CH3N, SPI2_MOSI and I2S2_SD, with remap TMR9_CH2. |
| 29 | PA8 | bidirectional | GPIO PA8, 5 V tolerant; alternate functions TMR1_CH1, CLKOUT, USART1_CK, SPIM_NSS and I2C2_SCL. |
| 30 | PA9 | bidirectional | GPIO PA9, 5 V tolerant; alternate functions TMR1_CH2, USART1_TX (bootloader pin) and I2C2_SMBA. |
| 31 | PA10 | bidirectional | GPIO PA10, 5 V tolerant; alternate functions TMR1_CH3 and USART1_RX (bootloader pin). |
| 32 | PA11 | bidirectional | GPIO PA11, not 5 V tolerant; alternate functions USB_DM (bootloader pin), TMR1_CH4, SPIM_IO0, USART1_CTS and CAN1_RX, and it has an additional non-disableable 330 kΩ pull-down. |
| 33 | PA12 | bidirectional | GPIO PA12, not 5 V tolerant; alternate functions USB_DP (bootloader pin), CAN1_TX, USART1_RTS, SPIM_IO1 and TMR1_ETR, and it has an additional non-disableable 330 kΩ pull-down. |
| 34 | PA13 | bidirectional | GPIO PA13, 5 V tolerant; default function JTMS-SWDIO, the serial-wire debug data pin. |
| 35 | PF6 | bidirectional | GPIO PF6, 5 V tolerant; alternate functions I2C1_SCL and I2C2_SCL. |
| 36 | PF7 | bidirectional | GPIO PF7, 5 V tolerant; alternate functions I2C1_SDA and I2C2_SDA. |
| 37 | PA14 | bidirectional | GPIO PA14, 5 V tolerant; default function JTCK-SWCLK, the serial-wire debug clock pin. |
| 38 | PA15 | bidirectional | GPIO PA15, 5 V tolerant; default function JTDI, with alternate functions TMR2_CH1, TMR2_ETR, SPI1_NSS, I2S1_WS, SPI2_NSS and I2S2_WS. |
| 39 | PB3 | bidirectional | GPIO PB3, 5 V tolerant; default function JTDO, with alternate functions TRACESWO, TMR2_CH2, SPI1_SCK, I2S1_CK, SPI2_SCK and I2S2_CK. |
| 40 | PB4 | bidirectional | GPIO PB4, 5 V tolerant; default function NJTRST, with alternate functions TMR3_CH1, SPI1_MISO, SPI2_MISO and I2C2_SDA. |
| 41 | PB5 | bidirectional | GPIO PB5, not 5 V tolerant; alternate functions I2C1_SMBA, TMR3_CH2, SPI1_MOSI, I2S1_SD, SPI2_MOSI, I2S2_SD and CAN2_RX. |
| 42 | PB6 | bidirectional | GPIO PB6, 5 V tolerant; alternate functions TMR4_CH1, I2C1_SCL and SPIM_IO3, with remaps USART1_TX, CAN2_TX and I2S1_MCK. |
| 43 | PB7 | bidirectional | GPIO PB7, 5 V tolerant; alternate functions TMR4_CH2, I2C1_SDA and SPIM_IO2, with remap USART1_RX. |
| 44 | BOOT0 | input | Boot-mode selection input; it has a weak pull-down that cannot be disabled. |
| 45 | PB8 | bidirectional | GPIO PB8, 5 V tolerant; alternate functions TMR4_CH3, TMR10_CH1, SDIO_D4, I2C1_SCL and CAN1_RX. |
| 46 | PB9 | bidirectional | GPIO PB9, 5 V tolerant; alternate functions TMR4_CH4, TMR11_CH1, SDIO_D5, I2C1_SDA and CAN1_TX. |
| 47 | VSS | power_in | Ground reference for the digital I/O and core logic. |
| 48 | VDD | power_in | Supply for the I/O pins and internal regulator, 2.6 to 3.6 V. |
Key specifications
| Parameter | Value |
|---|---|
| Manufacturer | ARTERY |
| Package | LQFP-48(7x7) |
| Category | Embedded Processors & Controllers |
| Pins | 48 |
Electrical characteristics
Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).
| Parameter | Symbol | Min | Typ | Max | Unit | Conditions | Page |
|---|---|---|---|---|---|---|---|
| Clock frequency in data transfer mode (SDIO) | fPP | 0 | 48 | MHz | CL ≤ 30 pF | 62 | |
| Clock low time (SDIO) | tW(CKL) | 32 | ns | CL ≤ 30 pF | 62 | ||
| Clock high time (SDIO) | tW(CKH) | 30 | ns | CL ≤ 30 pF | 62 | ||
| Clock rise time (SDIO) | tr | 4 | ns | CL ≤ 30 pF | 62 | ||
| Clock fall time (SDIO) | tf | 5 | ns | CL ≤ 30 pF | 62 | ||
| CMD, D input setup time vs CK (SDIO) | tISU | 2 | ns | CL ≤ 30 pF | 62 | ||
| CMD, D input hold time vs CK (SDIO) | tIH | 0 | ns | CL ≤ 30 pF | 62 | ||
| CMD, D output valid time, MMC/SD high speed (SDIO) | tOV | 6 | ns | CL ≤ 30 pF | 62 | ||
| CMD, D output hold time, MMC/SD high speed (SDIO) | tOH | 0 | ns | CL ≤ 30 pF | 62 | ||
| CMD, D output valid default time, SD default mode (SDIO) | tOVD | 7 | ns | CL ≤ 30 pF | 62 | ||
| CMD, D output hold default time, SD default mode (SDIO) | tOHD | 0.5 | ns | CL ≤ 30 pF | 62 | ||
| USB transceiver startup time | tSTARTUP | 1 | μs | Design guaranteed, not production tested | 63 | ||
| USB operating voltage | VDD | 3 | 3.6 | V | USB operation; correct USB function guaranteed at 2.6 V per footnote (2) | 63 | |
| Differential input sensitivity | VDI | 0.2 | V | I (USB_DP, USB_DM) | 63 | ||
| Differential common-mode range | VCM | 0.8 | 2.5 | V | Includes VDI range | 63 | |
| Single-ended receiver threshold | VSE | 1.3 | 2 | V | 63 | ||
| Static output low level | VOL | 0.3 | V | Internal 1.24 kΩ RL to 3.6 V | 63 | ||
| Static output high level | VOH | 2.8 | 3.6 | V | 15 kΩ RL to VSS | 63 | |
| USB_DP internal pull-up resistance | RPU | 0.97 | 1.24 | 1.58 | kΩ | VIN = VSS | 63 |
| USB full-speed rise time | tr | 4 | 20 | ns | CL ≤ 50 pF; 10% to 90%; design guaranteed | 63 | |
| USB full-speed fall time | tf | 4 | 20 | ns | CL ≤ 50 pF; 10% to 90%; design guaranteed | 63 | |
| USB rise/fall time matching | trfm | 90 | 110 | % | tr/tf; design guaranteed | 63 | |
| USB output signal crossover voltage | VCRS | 1.3 | 2 | V | Design guaranteed | 63 | |
| ADC supply voltage | VDDA | 2.6 | 3.6 | V | 64 | ||
| Current on VDDA input pin (ADC) | IDDA | 900 | μA | Printed value 790 and 900 μA both appear; see review_required | 64 | ||
| ADC clock frequency | fADC | 0.6 | 28 | MHz | 64 | ||
| ADC sampling rate | fS | 0.05 | 2 | MHz | Design guaranteed | 64 | |
| External trigger frequency | fTRIG | 1.65 | MHz | fADC = 28 MHz | 64 | ||
| External trigger frequency (cycles) | fTRIG | 17 | 1/fADC | 64 | |||
| Sampling time | tS | 0.053 | 8.55 | μs | fADC = 28 MHz | 64 | |
| Sampling time (cycles) | tS | 1.5 | 239.5 | 1/fADC | 64 | ||
| Total conversion time including sampling | tCONV | 0.5 | 9 | μs | fADC = 28 MHz | 64 | |
| Total conversion time including sampling (cycles) | tCONV | 14 | 252 | 1/fADC | Sampling tS + successive approximation 12.5 cycles | 64 | |
| Injected trigger conversion latency | tlat | 107 | ns | fADC = 28 MHz | 64 | ||
| Injected trigger conversion latency (cycles) | tlat | 3 | 1/fADC | Footnote (4): add one 1/fPCLK2 delay for external trigger | 64 | ||
| Regular trigger conversion latency | tlatr | 71.4 | μs | fADC = 28 MHz; printed as μs in source | 64 | ||
| Regular trigger conversion latency (cycles) | tlatr | 2 | 1/fADC | Footnote (4): add one 1/fPCLK2 delay for external trigger | 64 |
CAD (KiCad official)
- Symbol:
AT32F413CBT7 - Footprint:
Package_QFP:LQFP-48_7x7mm_P0.5mm - 3D model: LQFP-48(7x7) (KiCad packages3D, STEP)
- 3D model files:
at32f413cbt7-etched.step/at32f413cbt7-etched.glbcarry the MPN laser-etched on the die in a toggleableAdom.LaserEtchgroup (Fusion-ready);at32f413cbt7.step/at32f413cbt7.glbare the bare package body.
Provenance
Data extracted from the manufacturer datasheet, not a distributor listing:
- Datasheet: ARTERY datasheet (79 pp, sha256
9bb4b2403763a132, retrieved 2026-10-19, tier: lcsc) - Datasheet language: Chinese. Pin names, descriptions, and specs on this page were extracted and translated to English by ds2sf; the linked PDF is the manufacturer original.
- Extractor: parts-factory
2.0.0/extract_pins 0.3, primaryclaude-haiku-5-5(text), consensusclaude-sonnet-5-5(agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish. - CAD: KiCad official libraries (CC-BY-SA 4.0).